JPH04199721A - ワイヤボンディグ方式半導体装置 - Google Patents
ワイヤボンディグ方式半導体装置Info
- Publication number
- JPH04199721A JPH04199721A JP2333073A JP33307390A JPH04199721A JP H04199721 A JPH04199721 A JP H04199721A JP 2333073 A JP2333073 A JP 2333073A JP 33307390 A JP33307390 A JP 33307390A JP H04199721 A JPH04199721 A JP H04199721A
- Authority
- JP
- Japan
- Prior art keywords
- wire
- pad
- semiconductor device
- chip
- pads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 27
- 230000001681 protective effect Effects 0.000 claims abstract description 8
- 229910052751 metal Inorganic materials 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims description 2
- 238000007373 indentation Methods 0.000 abstract description 4
- 230000007547 defect Effects 0.000 abstract description 2
- 238000000034 method Methods 0.000 description 8
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 3
- 230000002159 abnormal effect Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
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Abstract
め要約のデータは記録されません。
Description
、特に多端子化に好適なボンディング・パッド電極を有
する半導体装置に関する。
集積化は、必然的にLSIの多端子化を招くが、能動素
子が組み込まれているアクティブ領域は半導体集積回路
の微細加工技術の進歩によりそれほど大きくならない。
し続けると入力端子数の増大によりLSIのチップ上の
ボンディング領域に無駄な部分を生じると共に、チップ
サイズの増加を招き、実装密度や製造コスト等さまさま
な点で問題となる。
るには、パッドピッチを小さくするとか、アクティブ領
域の上までパッドを設けるとかしなければならない。こ
れら多端子化に対応する方法としてフリップチップ方式
やテープキャリア方式等のワイヤレスボンディングの技
術が注目されている。しかし、これらの方式ではチップ
の形状、チップ内部の配線状態、及びパッドの構造を、
現状のワイヤボンディング方式から大幅に変更する必要
かあり、LSIの品種が変わっモ場合のフレキシビリテ
ィがないこと、動作時に発生ずる熱の放散に難点がある
こと等の問題がある。このために、一部特種なデバイス
にしか使用されておらす、量産品種には、ワイヤホンデ
ィング方式が相当多端子のものまで依然として採用され
ている。
+i、而図で面る。
ニウムから成るボンデ、インク・パット電極J02(以
下、j)tにパッド102と称す)が形成されており、
ここからホンディング・ワイヤ104(以ド、単にワイ
ヤ102と称す)が導出され、インナーリーF’+06
に接続されている。
ッド102のピッチか、ボンディング装置のギヤピラリ
の直径、角度やワイヤの直径、ループの高さ、角度やボ
ンディングの精度等により制約される。パッドピッチが
縮小されたり、ワイヤの入線角度θが増したりすると、
隣接するパッドとワイヤとの圧痕や、隣接するパッドと
ワイヤのテイルとの接触等か懸念される。
されるように、チップ100上に形成されたパッド10
2とワイヤ1.04とが交差していると、工程中の外観
チエツクにおいて異常と判断され、不良品となってしま
う。
おいて多端子化が進行すると、パッドピッチ縮小やワイ
ヤの入線角度の増大が招かれ、これにより、隣接するパ
ッドとワイヤとの圧痕、及び隣接するパッドとワイヤの
テイルとの接触等が懸念されてきている。
の目的は、パッドピッチ縮小や、ワイヤの入線角度が増
大しても、隣接するパッドとのワイヤとの圧痕、及び隣
接するパッドとワイヤのテイルとの接触等を防止でき、
アセンブリ歩留りを向上できるワイヤボンディング方式
半導体装置を提供することにある。
体チップ上のボンディング・パッド電極とリードフレー
ムのインナーリード部とを金属細線で結線するワイヤボ
ンディング方式半導体装置において、前記パッド電極も
しくはパッド電極上の保護膜開口部が持つ角部のうち、
前記チップ端面に而した角部の少なくとも一つが鈍角で
あることを特徴とする。
ては、チップ端面に面したパッド電極もしくはパッド電
極」二の保護膜開口部の角部が所謂“面取り”あるいは
“角取り“された形状となる。
大によった隣接するパッドとワイヤとの圧痕や、隣接す
るバンドとワイヤのテイルとの接触等が防止され、アセ
ンブリ歩留りが向上する。
。
ィング方式半導体装置の平面図である。
参照符号を付し、異なる部分についてのみ説明する。
イヤ104の入線方向であるチップ100端面に面した
パッド+−02の2つの角部が鈍角とされ、パッド10
2が“面取り“あるいは“角取り” (以下、統一して
面取りと称す)と呼ばれる形状にされたものである。
端面に沿って配置される全てのパッド102について為
されている。
プ100端面に面したパッド1.02の2つの角部が鈍
角とされることにより、ワイヤ104の入線角度が増し
ても、例えばワイヤ104とパッド102が交差するこ
とがない。又、図示せぬキャピラリによってワイヤ10
4がパッド】02に導かれる際にも、ワイヤ104がパ
ッド1.02近傍上を通過しなくなる。これらにより、
外観チエツクにおいて異常と判断され難くなると共に、
隣接するパッド102とワイヤ104との圧痕や、隣接
するパッド102とワイヤ104のテイルとの接触等を
防止できる。
ィング方式半導体装置の平面図である。
照符号を付し、異なる部分についてのみ説明する。
角部に配置されたパッド102のみ、上記のような面取
りが施されている。
のみ、上記のような形状のパッドが配置されても、第1
の実施例と同等な効果を得ることができる。
ィング方式半導体装置の要部を示す図である。第4図に
おいて第2図と同一の部分には同一の参照符号を付し、
異なる部分についてのみ説明する。
イヤ104の入線方向に沿うような方向のみ、行われて
も良い。
ィング方式半導体装置の要部を示す斜視図である。第5
図において第1図と同一の部分には同一の参照符号を付
し、異なる部分についてのみ説明する。
層以上のアルミニウムにより、パッドを形成した例であ
る。第1層アルミニウムから成る配線110がチップ1
00の端面付近まで形成されており、その先端は通常の
パッドと類似した形状に加工されている。この加工され
た部分の上に、配線110と接続され、上層アルミニウ
ムから成るパッド102が形成されている。このパッド
102の、図示せぬワイヤが入線される方向であるチッ
プ100の端面に面した角部が面取りされている。
パッドを形成する場合にも、この発明を適用することが
できる。
ィング方式半導体装置の要部を示す斜視図である。第6
図において第5図と同一の部分には同一の参照符号を付
し、異なる部分についてのみ説明する。
明したパッド102 “面取り”、″角取り”と呼ば
れる形状を、パッド102上の保護膜112の開口部1
14に形成した例である。パッド102の先端は通常の
パッドと類似した形状の加工されており、この加工され
た部分の上に開口部114が形成されている。この開口
部114の、図示せぬワイヤが入線される方向であるチ
ップ100端面に面した− つ − 角部か面取りされている。
14を面取りした形状にしても、上記実施例と同等の効
果を得ることができる。
ば、パッド、もしくはパッド上の保護膜開口部の、特に
ワイヤの入線方向であるチップ端面に面した角部のうち
、少なくとも一つを鈍角として面取りすることにより、
パッドピッチ縮小や、ワイヤの入線角度の増大に起因し
た隣接したパッドとワイヤとの圧痕や、隣接したパッド
とワイヤのテイルとの接触等の点を改善できる。これに
より多端子化に伴うパッドピッチ縮小化に好適な半導体
装置が得られる。又、パッドや保護膜開口部の角部を面
取りしてもパッドとワイヤとの接合面積は変イっること
がなく、この発明の実施に際し、その接合強度は下がる
ことはない。
の主旨を逸脱しない範囲で種々変更できることは勿論で
ある。
小や、ワイヤの入線角度の増大による隣接するパッドと
ワイヤとの圧痕や、隣接するパッドとワイヤのテイルと
の接触等を防止でき、アセンブリ歩留りを向」二できる
ワイヤボンディング方式半導体装置を提供できる。
ィング方式>1’−導体装置の平面図、第2図は第1図
の要部を示す図、第3図はこの発明の第2の実施例に係
わるワイヤボンディング方式半導体装置の平面図、第4
図はこの発明の第3の実施例に係わるワイヤホンディン
グ方式半導体装置の要部を示す図、第5図はこの発明の
第4の実施例に係わるワイヤボンディング方式半導体装
置の要部を示す斜視図、第6図はこの発明の第5の実施
例に係わるワイヤボンディング方式半導体装置の要部を
示す斜視図、第7図は従来のワイヤホンディング方式半
導体装置の東面図、第8図は第7図= 11 = の要部を示す拡大図である。 100・・チップ、102・・パッド、104 ・・
ワイヤ、】06・・インナーリード。 出願人代理人 弁理士 鈴江武彦 第1図 第2図 第3図 第4図 第7区 □ 第8区
Claims (1)
- 【特許請求の範囲】 半導体チップ上のボンディング・パッド電極とリードフ
レームのインナーリード部とを金属細線で結線するワイ
ヤボンディング方式半導体装置において、 前記パッド電極もしくはパッド電極上の保護膜開口部が
持つ角部のうち、前記チップ端面に面した角部の少なく
とも一つが鈍角であることを特徴とするワイヤボンディ
ング方式半導体装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2333073A JP2768822B2 (ja) | 1990-11-29 | 1990-11-29 | ワイヤボンディグ方式半導体装置 |
KR1019910021071A KR920010803A (ko) | 1990-11-29 | 1991-11-25 | 와이어본딩방식 반도체장치 |
EP91120207A EP0488186A1 (en) | 1990-11-29 | 1991-11-26 | Shape of bonding pad of semiconductor device bonded by wire bonding method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2333073A JP2768822B2 (ja) | 1990-11-29 | 1990-11-29 | ワイヤボンディグ方式半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH04199721A true JPH04199721A (ja) | 1992-07-20 |
JP2768822B2 JP2768822B2 (ja) | 1998-06-25 |
Family
ID=18261964
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2333073A Expired - Lifetime JP2768822B2 (ja) | 1990-11-29 | 1990-11-29 | ワイヤボンディグ方式半導体装置 |
Country Status (3)
Country | Link |
---|---|
EP (1) | EP0488186A1 (ja) |
JP (1) | JP2768822B2 (ja) |
KR (1) | KR920010803A (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6911112B2 (en) | 2001-11-29 | 2005-06-28 | Samsung Electronics Co., Ltd. | Method of and apparatus for performing sequential processes requiring different amounts of time in the manufacturing of semiconductor devices |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5309025A (en) * | 1992-07-27 | 1994-05-03 | Sgs-Thomson Microelectronics, Inc. | Semiconductor bond pad structure and method |
JP3022819B2 (ja) * | 1997-08-27 | 2000-03-21 | 日本電気アイシーマイコンシステム株式会社 | 半導体集積回路装置 |
KR100334053B1 (ko) * | 1999-11-05 | 2002-04-25 | 신원식 | 폐수 처리제 및 그 제조방법 |
JP3790995B2 (ja) * | 2004-01-22 | 2006-06-28 | 有限会社ボンドテック | 接合方法及びこの方法により作成されるデバイス並びに接合装置 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5555541A (en) * | 1978-10-20 | 1980-04-23 | Hitachi Ltd | Semiconductor element |
FR2616964B1 (fr) * | 1987-06-19 | 1990-03-02 | Thomson Composants Militaires | Puce de circuit integre avec plots d'entree-sortie allonges |
US4959706A (en) * | 1988-05-23 | 1990-09-25 | United Technologies Corporation | Integrated circuit having an improved bond pad |
-
1990
- 1990-11-29 JP JP2333073A patent/JP2768822B2/ja not_active Expired - Lifetime
-
1991
- 1991-11-25 KR KR1019910021071A patent/KR920010803A/ko not_active IP Right Cessation
- 1991-11-26 EP EP91120207A patent/EP0488186A1/en not_active Withdrawn
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6911112B2 (en) | 2001-11-29 | 2005-06-28 | Samsung Electronics Co., Ltd. | Method of and apparatus for performing sequential processes requiring different amounts of time in the manufacturing of semiconductor devices |
Also Published As
Publication number | Publication date |
---|---|
JP2768822B2 (ja) | 1998-06-25 |
EP0488186A1 (en) | 1992-06-03 |
KR920010803A (ko) | 1992-06-27 |
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