JPH0567646A - 半導体集積回路装置 - Google Patents

半導体集積回路装置

Info

Publication number
JPH0567646A
JPH0567646A JP3255770A JP25577091A JPH0567646A JP H0567646 A JPH0567646 A JP H0567646A JP 3255770 A JP3255770 A JP 3255770A JP 25577091 A JP25577091 A JP 25577091A JP H0567646 A JPH0567646 A JP H0567646A
Authority
JP
Japan
Prior art keywords
integrated circuit
semiconductor integrated
circuit device
pad
bonding pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3255770A
Other languages
English (en)
Inventor
Tadayuki Matsumura
忠幸 松村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP3255770A priority Critical patent/JPH0567646A/ja
Publication of JPH0567646A publication Critical patent/JPH0567646A/ja
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49431—Connecting portions the connecting portions being staggered on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10157—Shape being other than a cuboid at the active surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】 【構成】 複数に配列したボンディングパッドのうち、
外側のボンディングパッド２ａを内側のボンディングパ
ッド２ｂより低い位置に配置する。 【効果】 ボンディングパッド２ａ，２ｂとリードフレ
ームとを接続するワイヤ３ａ，３ｂ同士の短絡、及びワ
イヤ３ｂとボンディングパッド２ａとの短絡を防ぐ。

Description

【発明の詳細な説明】
【０００１】
【産業上の利用分野】この発明は半導体集積回路装置に
関し、特にリードフレームとの接続部分（以下、ボンデ
ィングパッドと称する）の改良に関するものである。
【０００２】
【従来の技術】図２は従来の半導体集積回路装置のチッ
プの平面図であり、図３はその断面図である。図におい
て、１１は半導体集積回路装置の内部チップの基板、１
２ｂ，１２ａは基板１１の周囲に設けられた内側と外側
のボンディングパッド、１３ｂ，１３ａはボンディング
パッド１２ｂ，１２ａと図示しないリードフレームとを
接続する導線（以下、ワイヤと称する）である。図３に
示すように、従来の半導体集積回路装置は外側のボンデ
ィングパッド２ａと内側のボンディングパッド２ｂが同
じ高さで配置されている。
【０００３】
【発明が解決しようとする課題】従来の半導体集積回路
装置は以上のように構成されているので、内側のボンデ
ィングパッドから出るワイヤと外側のボンディングパッ
ド及びそれより出るワイヤとが短絡する可能性があると
いう問題点があった。
【０００４】この発明は上記のような問題点を解消する
ためになされたもので、ワイヤ同士及びワイヤとボンデ
ィングパッドとが短絡するのを防ぐことのできる半導体
集積回路装置を得ることを目的とする。
【０００５】
【課題を解決するための手段】この発明に係る半導体集
積回路装置は、複数列配置されたボンディングパッドの
うち外側のボンディングパッドを内側のボンディングパ
ッドより低い位置に配置したものである。
【０００６】
【作用】この発明においては、外側のボンディングパッ
ドを内側のボンディングパッドより低い位置に配置した
ので、ワイヤ同士及びワイヤと他のボンディングパッド
との短絡を防ぐことができる。
【０００７】
【実施例】図１はこの発明の一実施例による半導体集積
回路装置のチップの断面図である。図において、１は半
導体集積回路装置の内部チップの基板、２ｂ，２ａは基
板１の周囲に設けられた内側と外側のボンディングパッ
ド、３ｂ，３ａはボンディングパッド２ｂ，２ａと図示
しないリードフレームとを接続するワイヤである。
【０００８】図に示すように、外側のボンディングパッ
ド２ａを内側のボンディングパッド２ｂより低い位置に
配置してあり、ぞれぞれ外側のワイヤ３ａ，内側のワイ
ヤ３ｂにてリードフレームと接続している。
【０００９】このように、外側のボンディングパッド２
ａを内側のボンディングパッド２ｂより低い位置に配置
することにより、内側のボンディングパッド２ｂから出
るワイヤ３ｂと外側のボンディングパッド２ａとの短
絡、及び外側のボンディングパッド２ａより出るワイヤ
３ａとの短絡を防ぐことができる。
【００１０】
【発明の効果】以上のようにこの発明に係る半導体集積
回路装置によれば、複数配列したボンディングパッドの
うち外側のボンディングパッドを内側のボンディングパ
ッドより低い位置に配置したので、ワイヤ同士及びワイ
ヤと他のボンディングパッドとの短絡を防ぐことがで
き、短絡の心配のない複数列配置を実現することができ
るという効果がある。
【図面の簡単な説明】
【図１】この発明の一実施例による半導体集積回路装置
のチップの断面図である。
【図２】従来の半導体集積回路装置のチップの平面図で
ある。
【図３】従来の半導体集積回路装置のチップの断面図で
ある。
【符号の説明】
１ 半導体集積回路装置の基板 ２ａ 外側のボンディングパッド ２ｂ 内側のボンディングパッド ３ａ 外側のワイヤ ３ｂ 内側のワイヤ

Claims (1)

    【特許請求の範囲】
  1. 【請求項１】 半導体基板の周囲に沿って複数列配置さ
    れたリードフレームとの接続部分を有する半導体集積回
    路装置において、 上記複数列の接続部分のうち外側の接合部分を、内側の
    接合部分より低く配置したことを特徴とする半導体集積
    回路装置。
JP3255770A 1991-09-06 1991-09-06 半導体集積回路装置 Pending JPH0567646A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3255770A JPH0567646A (ja) 1991-09-06 1991-09-06 半導体集積回路装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3255770A JPH0567646A (ja) 1991-09-06 1991-09-06 半導体集積回路装置

Publications (1)

Publication Number Publication Date
JPH0567646A true JPH0567646A (ja) 1993-03-19

Family

ID=17283382

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3255770A Pending JPH0567646A (ja) 1991-09-06 1991-09-06 半導体集積回路装置

Country Status (1)

Country Link
JP (1) JPH0567646A (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009021184A2 (en) * 2007-08-08 2009-02-12 Texas Instruments Incorporated Methods and apparatus to support an overhanging region of a stacked die

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009021184A2 (en) * 2007-08-08 2009-02-12 Texas Instruments Incorporated Methods and apparatus to support an overhanging region of a stacked die
WO2009021184A3 (en) * 2007-08-08 2009-03-26 Texas Instruments Inc Methods and apparatus to support an overhanging region of a stacked die

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