JP2768822B2 - ワイヤボンディグ方式半導体装置 - Google Patents
ワイヤボンディグ方式半導体装置Info
- Publication number
- JP2768822B2 JP2768822B2 JP2333073A JP33307390A JP2768822B2 JP 2768822 B2 JP2768822 B2 JP 2768822B2 JP 2333073 A JP2333073 A JP 2333073A JP 33307390 A JP33307390 A JP 33307390A JP 2768822 B2 JP2768822 B2 JP 2768822B2
- Authority
- JP
- Japan
- Prior art keywords
- wire
- pad
- semiconductor device
- type semiconductor
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 27
- 230000001681 protective effect Effects 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims description 2
- 238000000034 method Methods 0.000 description 10
- 238000007373 indentation Methods 0.000 description 7
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 238000003780 insertion Methods 0.000 description 6
- 230000037431 insertion Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000005856 abnormality Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
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- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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Description
り、特に多端子化に好適なボンディング・パッド電極を
有する半導体装置に関する。
集積化は、必然的にLSIの多端子化を招くが、能動素子
が組み込まれているアクティブ領域は半導体集積回路の
微細加工技術の進歩によりそれほど大きくならない。よ
って、従来のパッドレイアウトルールをそのまま適用し
続けると入力端子数の増大によりLSIのチップ上のボン
ディング領域に無駄な部分を生じると共に、チップサイ
ズの増加を招き、実装密度や製造コスト等さまざまな点
で問題となる。
図るには、パッドピッチを小さくするとか、アクティブ
領域の上までパッドを設けるとかしなければならない。
これら多端子化に対応する方法としてはフリップチップ
方式やテープキャリア方式等のワイヤレスボンディング
の技術が注目されている。しかし、これらの方式ではチ
ップの形状、チップ内部の配線状態、及びパッドの構造
を、現状のワイヤボンディング方式から大幅に変更する
必要があり、LSIの品種が変わった場合のフレキシビリ
ティがないこと、動作時に発生する熱の放散に難点があ
ること等の問題がある。このために、一部特種なデバイ
スにしか使用されておらず、量産品種には、ワイヤボン
ディング方式が相当多端子のものまで依然として採用さ
れている。
平面図である。
ニウムから成るボンディング・パッド電極102(以下、
単にパッド102と称す)が形成されており、ここからボ
ンディング・ワイヤ104(以下、単にワイヤ102と称す)
が導出され、インナーリード106に接続されている。
パッド102のピッチが、ボンディング装置のキャピラリ
の直径、角度やワイヤの直径、ループの高さ、角度やボ
ンディングの精度等により制約される。パッドピッチが
縮小されたり、ワイヤの入線角度θが増したりすると、
隣接するパッドとワイヤとの圧痕や、隣接するパッドと
ワイヤのテイルとの接触等が懸念される。
示されるように、チップ100上に形成されたパッド102と
ワイヤ104とが交差していると、工程中の外観チェック
において異常と判断され、不良品となってしまう。
おいて多端子化が進行すると、パッドピッチ縮小やワイ
ヤの入線角度の増大が招かれ、これにより、隣接するパ
ッドとワイヤとの圧痕、及び隣接するパッドとワイヤの
テイルとの接触等が懸念されてきている。
その目的は、パッドピッチ縮小や、ワイヤの入線角度が
増大しても、隣接するパッドとワイヤとの圧痕、及び隣
接するパッドとワイヤのテイルとの接触等を防止でき、
アセンブリ歩留りを向上できるワイヤボンディング方式
半導体装置を提供することにある。
導体チップ上のボンディング・パッド電極とリードフレ
ームのインナーリード部とを金属細線で結線するワイヤ
ボンディング方式半導体装置において、前記パッド電極
もしくはパッド電極上の保護膜開口部が持つ角部のう
ち、前記チップ端面に面した角部の少なくとも一つが鈍
角であることを特徴とする。
っては、チップ端面に面したパッド電極もしくはパッド
電極上の保護膜開口部の角部が所謂“面取り”あるいは
“角取り”された形状となる。これによりパッドピッチ
縮小や、ワイヤの入線角度の増大によった隣接するパッ
ドとワイヤとの圧痕や、隣接するパッドとワイヤのテイ
ルとの接触等が防止され、アセンブリ歩留りが向上す
る。
る。
ディング方式半導体装置の平面図である。第1図におい
て、第7図と同一の部分については同一の参照符号を付
し、異なる部分についてのみ説明する。
ワイヤ104の入線方向であるチップ100端面に面したパッ
ド102の2つの角部が鈍角とされ、パッド102が“面取
り”あるいは“角取り”(以下、統一として面取りと称
す)と呼ばれる形状にされたものである。
プ端面に沿って配置される全てのパッド102について為
されている。
プ100端面に面したパッド102の2つの角部が鈍角とされ
ることにより、ワイヤ104の入線角度が増しても、例え
ばワイヤ104とパッド102が交差することがない。又、図
示せぬキャピラリによってワイヤ104がパッド102に導か
れる際にも、ワイヤ104がパッド102近傍上を通過しなく
なる。これらにより、外観チェックにおいて異常と判断
され難くなると共に、隣接するパッド102とワイヤ104と
の圧痕や、隣接するパッド102とワイヤ104のテイルとの
接触等を防止できる。
ディング方式半導体装置の平面図である。第3図におい
て、第1図と同一部分については同一の参照符号を付
し、異なる部分についてのみ説明する。
角部に配置されたパッド102のみ、上記のような面取り
が施されている。
にのみ、上記のような形状のパッドが配置されても、第
1の実施例と同等な効果を得ることができる。
ディング方式半導体装置の要部を示す図である。第4図
において第2図と同一の部分には同一の参照符号を付
し、異なる部分についてのみ説明する。
イヤ104の入線方向に沿うような方向のみ、行われても
良い。
ディング方式半導体装置の要部を示す斜視図である。第
5図において第1図と同一の部分には同一の参照符号を
付し、異なる部分についてのみ説明する。
2層以上のアルミニウムにより、パッドを形成した例で
ある。第1層アルミニウムから成る配線110がチップ100
の端面付近まで形成されており、その先端は通常のパッ
ドと類似した形状に加工されている。この加工された部
分の上に、配線110と接続され、上層アルミニウムから
成るパッド102が形成されている。このパッド102の、図
示せぬワイヤが入線される方向であるチップ100の端面
に面した角部が面取りされている。
グパッドを形成する場合にも、この発明を適用すること
ができる。
ディング方式半導体装置の要部を示す斜視図である。第
6図において第5図と同一の部分には同一の参照符号を
付し、異なる部分についてのみ説明する。
説明したパッド102“面取り”、“角取り”と呼ばれる
形状を、パッド102上の保護膜112の開口部114に形成し
た例である。パッド102の先端は通常のパッドと類似し
た形状の加工されており、この加工された部分の上に開
口部114が形成されている。この開口部114の、図示せぬ
ワイヤが入線される方向であるチップ100端面に面した
角部が面取りされている。
面取りした形状にしても、上記実施例と同等の効果を得
ることができる。
れば、パッド、もしくはパッド上の保護膜開口部の、特
にワイヤの入線方向であるチップ端面に面した角部のう
ち、少なくとも一つを鈍角として面取りすることによ
り、パッドピッチ縮小や、ワイヤの入線角度の増大に起
因した隣接したパッドとワイヤとの圧痕や、隣接したパ
ッドとワイヤのテイルとの接触等の点を改善できる。こ
れにより多端子化に伴うパッドピッチ縮小化に好適な半
導体装置が得られる。又、パッドや保護膜開口部の角部
を面取りしてもパッドとワイヤとの接合面積は変わるこ
とがなく、この発明の実施に際し、その接合強度は下が
ることはない。
その主旨を逸脱しない範囲で種々変更できることは勿論
である。
縮小や、ワイヤの入線角度の増大による隣接するパッド
とワイヤとの圧痕や、隣接するパッドとワイヤのテイル
との接触等を防止でき、アセンブリ歩留りを向上できる
ワイヤボンディング方式半導体装置を提供できる。
ィング方式半導体装置の平面図、第2図は第1図の要部
を示す図、第3図はこの発明の第2の実施例に係わるワ
イヤボンディング方式半導体装置の平面図、第4図はこ
の発明の第3の実施例に係わるワイヤボンディング方式
半導体装置の要部を示す図、第5図はこの発明の第4の
実施例に係わるワイヤボンディング方式半導体装置の要
部を示す斜視図、第6図はこの発明の第5の実施例に係
わるワイヤボンディング方式半導体装置の要部を示す斜
視図、第7図は従来のワイヤボンディング方式半導体装
置の平面図、第8図は第7図の要部を示す拡大図であ
る。 100……チップ、102……パッド、104……ワイヤ、106…
…インナーリード。
Claims (1)
- 【請求項1】半導体チップ上のボンディング・パッド電
極とリードフレームのインナーリード部とを金属細線で
結線するワイヤボンディング方式半導体装置において、 前記パッド電極もしくはパッド電極上の保護膜開口部が
持つ角部のうち、前記チップ端面に面した角部の少なく
とも一つが鈍角であることを特徴とするワイヤボンディ
ング方式半導体装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2333073A JP2768822B2 (ja) | 1990-11-29 | 1990-11-29 | ワイヤボンディグ方式半導体装置 |
KR1019910021071A KR920010803A (ko) | 1990-11-29 | 1991-11-25 | 와이어본딩방식 반도체장치 |
EP91120207A EP0488186A1 (en) | 1990-11-29 | 1991-11-26 | Shape of bonding pad of semiconductor device bonded by wire bonding method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2333073A JP2768822B2 (ja) | 1990-11-29 | 1990-11-29 | ワイヤボンディグ方式半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH04199721A JPH04199721A (ja) | 1992-07-20 |
JP2768822B2 true JP2768822B2 (ja) | 1998-06-25 |
Family
ID=18261964
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2333073A Expired - Lifetime JP2768822B2 (ja) | 1990-11-29 | 1990-11-29 | ワイヤボンディグ方式半導体装置 |
Country Status (3)
Country | Link |
---|---|
EP (1) | EP0488186A1 (ja) |
JP (1) | JP2768822B2 (ja) |
KR (1) | KR920010803A (ja) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5309025A (en) * | 1992-07-27 | 1994-05-03 | Sgs-Thomson Microelectronics, Inc. | Semiconductor bond pad structure and method |
JP3022819B2 (ja) * | 1997-08-27 | 2000-03-21 | 日本電気アイシーマイコンシステム株式会社 | 半導体集積回路装置 |
KR100334053B1 (ko) * | 1999-11-05 | 2002-04-25 | 신원식 | 폐수 처리제 및 그 제조방법 |
KR100443121B1 (ko) | 2001-11-29 | 2004-08-04 | 삼성전자주식회사 | 반도체 공정의 수행 방법 및 반도체 공정 장치 |
JP3790995B2 (ja) * | 2004-01-22 | 2006-06-28 | 有限会社ボンドテック | 接合方法及びこの方法により作成されるデバイス並びに接合装置 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5555541A (en) * | 1978-10-20 | 1980-04-23 | Hitachi Ltd | Semiconductor element |
FR2616964B1 (fr) * | 1987-06-19 | 1990-03-02 | Thomson Composants Militaires | Puce de circuit integre avec plots d'entree-sortie allonges |
US4959706A (en) * | 1988-05-23 | 1990-09-25 | United Technologies Corporation | Integrated circuit having an improved bond pad |
-
1990
- 1990-11-29 JP JP2333073A patent/JP2768822B2/ja not_active Expired - Lifetime
-
1991
- 1991-11-25 KR KR1019910021071A patent/KR920010803A/ko not_active IP Right Cessation
- 1991-11-26 EP EP91120207A patent/EP0488186A1/en not_active Withdrawn
Also Published As
Publication number | Publication date |
---|---|
KR920010803A (ko) | 1992-06-27 |
JPH04199721A (ja) | 1992-07-20 |
EP0488186A1 (en) | 1992-06-03 |
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