JPH0330347A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPH0330347A
JPH0330347A JP1164533A JP16453389A JPH0330347A JP H0330347 A JPH0330347 A JP H0330347A JP 1164533 A JP1164533 A JP 1164533A JP 16453389 A JP16453389 A JP 16453389A JP H0330347 A JPH0330347 A JP H0330347A
Authority
JP
Japan
Prior art keywords
bonding
semiconductor device
oxide film
copper group
copper
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1164533A
Other languages
English (en)
Other versions
JPH0682704B2 (ja
Inventor
Tadaaki Ono
大野　忠秋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP1164533A priority Critical patent/JPH0682704B2/ja
Priority to EP90112253A priority patent/EP0405501B1/en
Priority to KR1019900009536A priority patent/KR930011456B1/ko
Priority to DE69034071T priority patent/DE69034071T2/de
Publication of JPH0330347A publication Critical patent/JPH0330347A/ja
Priority to US08/037,184 priority patent/US5293073A/en
Publication of JPH0682704B2 publication Critical patent/JPH0682704B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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  • Engineering & Computer Science (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 ［発明の目的］ （産業上の利用分野） 本発明は、銅系ワイヤをボンディングワイヤとして使用
する半導体装置の電極に関するものである。
（従来の技術） 一般に、高周波用半導体装置や集積回路などは、電極を
ＡＮ　　（アルミニウム）によって取りだしている。ま
た、このＡｐによって、酸化膜上にボンディングパット
を形成している。
第３図は従来の半導体装置の断面図を示すものである。
シリコン基板１１の表面領域にはＰ／Ｎジャンクション
を有する素子（例えばトランジスタ）１３が形成されて
いる。また、シリコン基板１１上には酸化膜１２が形成
されている。この酸化膜１２には所定の場所に電極を取
り出すためのコンタクトホル１４が形成されている。そ
して、コンタクトホール１４を介してＡＩＩＸ極１５極
数５出され、ボンディングパットが酸化膜１２上に形成
されている。
また、第４図は前記半導体装置を用いて銅系ワイヤをボ
ンディングしたときの半導体チップの断面図を示すもの
である。なお、第４図において、前記第３図と同一の部
分には同じ符号が付しである。
前記半導体装置が形成された半導体チ・ツブｌＢは、リ
ードフレーム１７にマウントされる。この後、銅系（銅
、銅合金等）のワイヤ１８により、ｌ電極１５と外部リ
ードとが接続されることになる。ところが、銅系ワイヤ
はボンディングワイヤのなかでは硬く、へΩ電極１５を
変形させて接合することになる。このため、半導体チッ
プ１Ｇへのダメージが強く、ボンディング部直下の酸化
膜１２に、又はその下のシリコン基板１１までクラック
１９を生じやすいという欠点がある。
なお、酸化１１％１２にクラック１９が発生すれば絶縁
が保てなくなり、クラック１９を通じて電極間リフ又は
ショートに至り、不都合である。
（発明が解決しようとするＫｍ） このように、従来は、銅系ワイヤをボンディングワイヤ
として使用をすると、半導体チップにダメージを与え、
クラック等が発生するという欠点があった。
よって、本発明は、銅系ワイヤのボンディングにおいて
も、そのダメージに耐えることができるボンディングパ
ットを提供することを目的とす上記し１的を達成するた
めに、本発明の半導体装置は、半導体素子の電極を金属
膜によって取りだしこの金属膜によりボンディング）々
・ントを形成するものであり、半導体基板と、この半導
体基板上に形成される絶縁酸化膜と、この絶縁酸化膜上
に形成される、前記絶縁酸化膜よりも硬い、窒素又は炭
素を含むケイ素化合物よりなる膜と、このケイ素化合物
よりなる膜上に形成される前記金属膜よりなるボンディ
ングパットとを有している。
（作用） このような半導体装置によれば、絶縁酸化膜とボンディ
ングパットとの間に、前記絶縁酸化膜よりも硬い、ケイ
素化合物よりなる膜が設けられている。これにより、前
記バットと外部リードとを銅系のワイヤを用いてワイヤ
ボンディングを行っても、バット上での局部的な応力集
中を避けることができ、そのダメージに耐えることがで
きる。
（実施例） 以下、図面を参照して本発明の一実施例を詳細に説明す
る。
第１図は本発明の半導体装置を示すものである。なお、
第１図において、前記第３図に示した従来の半導体装置
と同一の部分には同じ符号を付して詳細な説明を省略す
る。
シリコン基板１１の表面領域にはＰ／Ｎジャンクション
を有する素子（例えばトランジスタ）　１３が形成され
ている。シリコン基板１１上には絶縁酸化１ｆ！ｌ（例
えば５ｉ０２）１２が形成されている。この酸化膜１２
には所定の場所に電極を取り出すためのコンタクトホー
ル１４が形成されている。また、ボンディングパットの
直下になる酸化膜１２上には、酸化１１１１２よりも硬
いケイ素化合物、例えば窒化膜（ＳｉｓＮ４）２０が形
成されている。そして、コンタクトホール１４を介して
Ａｇ電極１５が積り出され、ボンディングパットが酸化
膜１２上に窒化膜２０を介して形成されている。
第２図は前記半導体装置を用いて銅系ワイヤをボンディ
ングしたときの半導体チップの断面図を示すものである
。なお、第２図において、前記第１図の半導体装置と同
一の部分には同じ符号が付しである。
まず、前記半導体装置が形成された半導体チップ１Ｂは
、リードフレーム１７にマウントされる。
この後、リードフレーム１７は２００℃〜４５０℃に加
熱される。そして、銅系ワイヤ１８は、熱圧着又は振動
（超音波）により半導体チップ１６のボンディングパッ
トに接合される。
この時、銅系ワイヤ１８のボールｌ１ｌａとボンディン
グパットのＡｇ電極１５は変形し、下部にダメージや歪
みを与える。しかし、銅系ワイヤ１８がボンディングさ
れるＡｇ電極１５の下部には、酸化膜１２よりも硬い窒
化膜２０が存在している。即ち、この窒化膜２０を設け
ることにより、局部的な応力集中を避けることができ、
衝撃緩和の効果が得られる。
これにより、従来、組立後の初期特性として、リーク不
良、耐圧不良が共に５〜３０％も発生していたのが、本
発明によって、これらの不良を０．０１％以下にするこ
とができる。また、寿命試験においても、高温放置テス
ト、熱サイクルテスト等で１０倍以上の寿命を得ること
ができる。
次に、前記第１図に示した半導体装置の製造方法につい
て、同図を参照しながら説明する。
まず、シリコン基板１１上に酸化膜１２を形成する。酸
化膜１２には所定の場所にコンタクトホールを開孔する
。次に、プラズマＣＶＤ法により窒化膜２０を堆積形成
する。また、ＰＥＰ　（写真蝕刻工程）により、この窒
化膜２０をバターニングする。
この後、ＡＩＪＩ！Ｉを堆積形成し、バターニングを行
ってボンディングパットを何するＡｇ電極１５を形成す
る。
ここで、Ａｇ電極１５のステップカバレージを良くする
ため、窒化膜２０上にはＣＶＤ法により酸化膜を形成す
るのも効果的である。
また、ボンディングパット直下になるケイ素化合物の厚
さは、この化合物によりワイヤボンディング時における
衝撃緩和の効果が得られる範囲が良い。なお、前記化合
物が窒化膜２０の場合には、その厚さは少なくとも１０
００Å以上あるのがよく、又３０００〜１５０００人が
効果的である。
ところで、前記実施例では、ボンディングパット直下に
設ける衝撃緩和のための化合物とｊ、て窒化膜（例えば
５ｉｉＮ４）２０について説明してきたが、酸化膜１２
よりも硬い化合物であれば、これに限られない。例えば
、５ｉＯＮ等の窒素化合物若しくは炭化ケイ素（ＳｉＣ
）等の炭化物又はこれらの複合化合物によるケイ素化合
物であれば、同様の効果が得られる。
また、本発明が適用できる半導体素子としては、トラン
ジスタ、ダイオード、集積回路素子等はもちろん、全て
の半導体素子について適用できることは言うまでもない
。
［発明の効果］ 以上、説明したように、本発明の半導体装置によれば、
次のような効果を奏する。
ボンディングパットになるＡＩ）？Ｉｉ極と、絶縁酸化
膜との間に、前記絶縁酸化膜よりも硬いケイ素化合物、
例えばＳｉ３Ｎ４を設けている。よって、銅系ワイヤの
ボンディングにおいても、そのダメージに耐えることが
できるボンディングパットを形成することができる。
【図面の簡単な説明】
第１図は本発明の一実施例に係わる半導体装置を示す断
面図、第２図は前記第１図の半導体装置を用いて銅系ワ
イヤをボンディングしたときの半導体チップを示す断面
図、第３図は従来の半導体装置を示す断面図、第４図は
前記第３図の半導体装置を用いて銅系ワイヤをボンディ
ングしたときの半導体チップを示す断面図である。 １２・・・酸化膜、１５・・・Ａｇ７ｉｉ極、１８・・
・銅系ワイヤ、２０・・・窒化膜。 ３ 第１図

Claims (1)

    【特許請求の範囲】
  1. 半導体素子の電極を金属膜によって取りだしこの金属膜
    によりボンディングパットを形成する半導体装置であっ
    て、半導体基板と、この半導体基板上に形成される絶縁
    酸化膜と、この絶縁酸化膜上に形成される、前記絶縁酸
    化膜よりも硬い、窒素又は炭素を含むケイ素化合物より
    なる膜と、このケイ素化合物よりなる膜上に形成される
    前記金属膜よりなるボンディングパットとを具備する半
    導体装置。
JP1164533A 1989-06-27 1989-06-27 半導体装置 Expired - Lifetime JPH0682704B2 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP1164533A JPH0682704B2 (ja) 1989-06-27 1989-06-27 半導体装置
EP90112253A EP0405501B1 (en) 1989-06-27 1990-06-27 Semiconductor device
KR1019900009536A KR930011456B1 (ko) 1989-06-27 1990-06-27 반도체장치
DE69034071T DE69034071T2 (de) 1989-06-27 1990-06-27 Halbleiteranordnung
US08/037,184 US5293073A (en) 1989-06-27 1993-03-24 Electrode structure of a semiconductor device which uses a copper wire as a bonding wire

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1164533A JPH0682704B2 (ja) 1989-06-27 1989-06-27 半導体装置

Publications (2)

Publication Number Publication Date
JPH0330347A true JPH0330347A (ja) 1991-02-08
JPH0682704B2 JPH0682704B2 (ja) 1994-10-19

Family

ID=15794971

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1164533A Expired - Lifetime JPH0682704B2 (ja) 1989-06-27 1989-06-27 半導体装置

Country Status (4)

Country Link
EP (1) EP0405501B1 (ja)
JP (1) JPH0682704B2 (ja)
KR (1) KR930011456B1 (ja)
DE (1) DE69034071T2 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6603207B2 (en) 1995-07-14 2003-08-05 Matsushita Electric Industrial Co., Ltd. Electrode structure for semiconductor device, method for forming the same, mounted body including semiconductor device and semiconductor device

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6875687B1 (en) 1999-10-18 2005-04-05 Applied Materials, Inc. Capping layer for extreme low dielectric constant films
EP1094506A3 (en) * 1999-10-18 2004-03-03 Applied Materials, Inc. Capping layer for extreme low dielectric constant films
US7612457B2 (en) 2007-06-21 2009-11-03 Infineon Technologies Ag Semiconductor device including a stress buffer

Citations (6)

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Publication number Priority date Publication date Assignee Title
JPS5886733A (ja) * 1981-11-18 1983-05-24 Nec Corp 半導体装置
JPS6031243A (ja) * 1983-08-01 1985-02-18 Nec Corp 半導体装置
JPS61196552A (ja) * 1985-02-26 1986-08-30 Nec Corp 半導体集積回路装置
JPS6218060A (ja) * 1985-07-16 1987-01-27 Nec Corp 半導体装置
JPS6232617A (ja) * 1985-08-02 1987-02-12 Matsushita Electronics Corp 半導体装置およびその製造方法
JPS6484724A (en) * 1987-09-28 1989-03-30 Nec Corp Semiconductor device

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Publication number Priority date Publication date Assignee Title
JPS57113235A (en) * 1980-12-29 1982-07-14 Nec Corp Semiconductor device
US4949150A (en) * 1986-04-17 1990-08-14 Exar Corporation Programmable bonding pad with sandwiched silicon oxide and silicon nitride layers
JPS63148646A (ja) * 1986-12-12 1988-06-21 Toshiba Corp 半導体装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5886733A (ja) * 1981-11-18 1983-05-24 Nec Corp 半導体装置
JPS6031243A (ja) * 1983-08-01 1985-02-18 Nec Corp 半導体装置
JPS61196552A (ja) * 1985-02-26 1986-08-30 Nec Corp 半導体集積回路装置
JPS6218060A (ja) * 1985-07-16 1987-01-27 Nec Corp 半導体装置
JPS6232617A (ja) * 1985-08-02 1987-02-12 Matsushita Electronics Corp 半導体装置およびその製造方法
JPS6484724A (en) * 1987-09-28 1989-03-30 Nec Corp Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6603207B2 (en) 1995-07-14 2003-08-05 Matsushita Electric Industrial Co., Ltd. Electrode structure for semiconductor device, method for forming the same, mounted body including semiconductor device and semiconductor device

Also Published As

Publication number Publication date
EP0405501A2 (en) 1991-01-02
EP0405501A3 (en) 1991-07-24
KR930011456B1 (ko) 1993-12-08
JPH0682704B2 (ja) 1994-10-19
DE69034071T2 (de) 2004-01-08
KR910001924A (ko) 1991-01-31
DE69034071D1 (de) 2003-06-18
EP0405501B1 (en) 2003-05-14

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