JPH0323995B2 - - Google Patents
Info
- Publication number
- JPH0323995B2 JPH0323995B2 JP57233906A JP23390682A JPH0323995B2 JP H0323995 B2 JPH0323995 B2 JP H0323995B2 JP 57233906 A JP57233906 A JP 57233906A JP 23390682 A JP23390682 A JP 23390682A JP H0323995 B2 JPH0323995 B2 JP H0323995B2
- Authority
- JP
- Japan
- Prior art keywords
- stage decoder
- decoder
- stage
- circuit
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/10—Decoders
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Static Random-Access Memory (AREA)
- Semiconductor Memories (AREA)
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57233906A JPS59124092A (ja) | 1982-12-29 | 1982-12-29 | メモリ装置 |
| EP83307901A EP0115187B1 (en) | 1982-12-29 | 1983-12-22 | Semiconductor memory device with decoder means |
| DE8383307901T DE3382163D1 (de) | 1982-12-29 | 1983-12-22 | Halbleiterspeicheranordnung mit dekodiermitteln. |
| US06/566,323 US4617653A (en) | 1982-12-29 | 1983-12-28 | Semiconductor memory device utilizing multi-stage decoding |
| IE3081/83A IE56715B1 (en) | 1982-12-29 | 1983-12-29 | Semiconductor memory device with decoder means |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57233906A JPS59124092A (ja) | 1982-12-29 | 1982-12-29 | メモリ装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59124092A JPS59124092A (ja) | 1984-07-18 |
| JPH0323995B2 true JPH0323995B2 (cg-RX-API-DMAC7.html) | 1991-04-02 |
Family
ID=16962433
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57233906A Granted JPS59124092A (ja) | 1982-12-29 | 1982-12-29 | メモリ装置 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US4617653A (cg-RX-API-DMAC7.html) |
| EP (1) | EP0115187B1 (cg-RX-API-DMAC7.html) |
| JP (1) | JPS59124092A (cg-RX-API-DMAC7.html) |
| DE (1) | DE3382163D1 (cg-RX-API-DMAC7.html) |
| IE (1) | IE56715B1 (cg-RX-API-DMAC7.html) |
Families Citing this family (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6148192A (ja) * | 1984-08-11 | 1986-03-08 | Fujitsu Ltd | 半導体記憶装置 |
| JPS6167154A (ja) * | 1984-09-11 | 1986-04-07 | Fujitsu Ltd | 半導体記憶装置 |
| JPS61199297A (ja) * | 1985-02-28 | 1986-09-03 | Toshiba Corp | 半導体記憶装置 |
| JPS61265794A (ja) * | 1985-05-20 | 1986-11-25 | Fujitsu Ltd | 半導体記憶装置のデコ−ダ回路 |
| JP2603205B2 (ja) * | 1987-03-16 | 1997-04-23 | シーメンス、アクチエンゲゼルシヤフト | 多段集積デコーダ装置 |
| DE3884492T2 (de) * | 1987-07-15 | 1994-02-17 | Hitachi Ltd | Integrierte Halbleiterschaltungsanordnung. |
| US5257234A (en) * | 1987-07-15 | 1993-10-26 | Hitachi, Ltd. | Semiconductor integrated circuit device |
| KR930001737B1 (ko) * | 1989-12-29 | 1993-03-12 | 삼성전자 주식회사 | 반도체 메모리 어레이의 워드라인 배열방법 |
| KR920010344B1 (ko) * | 1989-12-29 | 1992-11-27 | 삼성전자주식회사 | 반도체 메모리 어레이의 구성방법 |
| KR930001738B1 (ko) * | 1989-12-29 | 1993-03-12 | 삼성전자주식회사 | 반도체 메모리장치의 워드라인 드라이버 배치방법 |
| US5652723A (en) * | 1991-04-18 | 1997-07-29 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device |
| EP0596198B1 (en) * | 1992-07-10 | 2000-03-29 | Sony Corporation | Flash eprom with erase verification and address scrambling architecture |
| JP2001126475A (ja) * | 1999-10-25 | 2001-05-11 | Mitsubishi Electric Corp | 半導体記憶装置 |
| US8755213B2 (en) | 2012-02-29 | 2014-06-17 | International Business Machines Corporation | Decoding scheme for bipolar-based diode three-dimensional memory requiring bipolar programming |
| US8842491B2 (en) | 2012-07-17 | 2014-09-23 | International Business Machines Corporation | Decoding scheme for bipolar-based diode three-dimensional memory requiring unipolar programming |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3599182A (en) * | 1969-01-15 | 1971-08-10 | Ibm | Means for reducing power consumption in a memory device |
| US3688280A (en) * | 1970-09-22 | 1972-08-29 | Ibm | Monolithic memory system with bi-level powering for reduced power consumption |
| US4027285A (en) * | 1973-12-26 | 1977-05-31 | Motorola, Inc. | Decode circuitry for bipolar random access memory |
| JPS528739A (en) * | 1975-07-10 | 1977-01-22 | Fujitsu Ltd | Electronic circuit |
| JPS5631137A (en) * | 1979-08-22 | 1981-03-28 | Fujitsu Ltd | Decoder circuit |
| JPS56112122A (en) * | 1980-02-08 | 1981-09-04 | Fujitsu Ltd | Decoder circuit |
| JPS5841597B2 (ja) * | 1980-12-24 | 1983-09-13 | 富士通株式会社 | 半導体メモリディスチャ−ジ回路 |
-
1982
- 1982-12-29 JP JP57233906A patent/JPS59124092A/ja active Granted
-
1983
- 1983-12-22 EP EP83307901A patent/EP0115187B1/en not_active Expired - Lifetime
- 1983-12-22 DE DE8383307901T patent/DE3382163D1/de not_active Expired - Lifetime
- 1983-12-28 US US06/566,323 patent/US4617653A/en not_active Expired - Fee Related
- 1983-12-29 IE IE3081/83A patent/IE56715B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| IE56715B1 (en) | 1991-11-20 |
| US4617653A (en) | 1986-10-14 |
| DE3382163D1 (de) | 1991-03-28 |
| EP0115187B1 (en) | 1991-02-20 |
| JPS59124092A (ja) | 1984-07-18 |
| IE833081L (en) | 1984-06-29 |
| EP0115187A2 (en) | 1984-08-08 |
| EP0115187A3 (en) | 1986-12-30 |
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