JPH0256692B2 - - Google Patents

Info

Publication number
JPH0256692B2
JPH0256692B2 JP56119699A JP11969981A JPH0256692B2 JP H0256692 B2 JPH0256692 B2 JP H0256692B2 JP 56119699 A JP56119699 A JP 56119699A JP 11969981 A JP11969981 A JP 11969981A JP H0256692 B2 JPH0256692 B2 JP H0256692B2
Authority
JP
Japan
Prior art keywords
common bus
address
data
main memory
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP56119699A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5819969A (ja
Inventor
Masaaki Kobayashi
Takumi Kishino
Shigeru Hashimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56119699A priority Critical patent/JPS5819969A/ja
Publication of JPS5819969A publication Critical patent/JPS5819969A/ja
Publication of JPH0256692B2 publication Critical patent/JPH0256692B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP56119699A 1981-07-30 1981-07-30 メモリアクセス制御方式 Granted JPS5819969A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56119699A JPS5819969A (ja) 1981-07-30 1981-07-30 メモリアクセス制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56119699A JPS5819969A (ja) 1981-07-30 1981-07-30 メモリアクセス制御方式

Publications (2)

Publication Number Publication Date
JPS5819969A JPS5819969A (ja) 1983-02-05
JPH0256692B2 true JPH0256692B2 (cs) 1990-11-30

Family

ID=14767877

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56119699A Granted JPS5819969A (ja) 1981-07-30 1981-07-30 メモリアクセス制御方式

Country Status (1)

Country Link
JP (1) JPS5819969A (cs)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5319574A (en) * 1988-12-27 1994-06-07 Fujitsu Limited Status change monitoring apparatus

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55153024A (en) * 1979-05-15 1980-11-28 Toshiba Corp Bus control system
JPS5671129A (en) * 1979-11-15 1981-06-13 Fujitsu Ltd Data processing system

Also Published As

Publication number Publication date
JPS5819969A (ja) 1983-02-05

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