JPH02307225A - 樹脂封止型半導体装置 - Google Patents

樹脂封止型半導体装置

Info

Publication number
JPH02307225A
JPH02307225A JP1129165A JP12916589A JPH02307225A JP H02307225 A JPH02307225 A JP H02307225A JP 1129165 A JP1129165 A JP 1129165A JP 12916589 A JP12916589 A JP 12916589A JP H02307225 A JPH02307225 A JP H02307225A
Authority
JP
Japan
Prior art keywords
pads
island
semiconductor device
bump
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1129165A
Other languages
English (en)
Other versions
JP2819614B2 (ja
Inventor
Yoshihiro Kitamura
北村　義裕
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1129165A priority Critical patent/JP2819614B2/ja
Publication of JPH02307225A publication Critical patent/JPH02307225A/ja
Application granted granted Critical
Publication of JP2819614B2 publication Critical patent/JP2819614B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は樹脂封止型半導体装置に関する。
〔従来の技術〕
樹脂封止型半導体装置は、種々のパッケージに組立てる
ことかできるように半導体チップに設けた外部回路接続
用の電極パッドのすべてのパッケージに対応できるよう
に配置しである。
第２図は従来の樹脂封止型半導体装置の一例を示す部分
平面図である。
第２図に示すように、アイランド６の上に搭載した半導
体チップ４の内部配線５に接続して設けた電極パッド３
ｅ、３ｆと、アイランド６の周囲に設けた内部リード７
ｃ、７ｄと電極パッド３ｆと内部リード７ｄとの間を電
気的に接続する金属細線２とを含んで構成されている。
ここで、電極パッド３ｅはいずれの内部リードとも接続
されず空パッドとなっている。
〔発明が解決しようとする課題〕
上述した従来の樹脂封止型半導体装置は、内部配線に接
続された電極パッドのうちの一部にいずれの内部リード
とも接続されない空パッドを有しているので、耐湿性に
おいて樹脂内部へ侵入する水分や不純分によって、アル
ミニウム層が露出している空きパッドの腐蝕が発生し、
断線してしまうという欠点があった。
〔課題を解決するための手段〕
本発明の樹脂封止型半導体装置は、アイランド上に搭載
した半導体チップに設けた電極パッドと、前記アイラン
ドの周囲に設けて前記電極パッドと電気的に接続した内
部リードとを有する樹脂封止型半導体装置において、前
記内部リードのいずれとも接続されていない空きパッド
の表面に設けて腐蝕を防止するホール状バンプを有する
。
〔実施例〕
次に、本発明について図面を参照して説明する。
第１図は本発明の一実施例の部分斜視図である。
アイランド６に搭載された半導体チップ４に設けた電極
パッド３ａ、３ｂ、３ｃ、３ｄの内の電極３ａ、３ｃを
アイランド６の周囲に設けた内部リード７ａ、７ｂにそ
れぞれ金属細線２により接続する。次に、空きパッドと
なっている電極パッド３ｂ、３ｄにポールホンディング
法によるバンプ１を圧着して形成する。このように、半
導体チップ４の空きパッド全てにバンプ１を形成して水
分、不純分の侵入によるアルミ腐蝕を抑えることかでき
る。
〔発明の効果〕
以上説明したように本発明は、全ての空きパッドにホー
ル状バンプを圧着することにより空きバットに発生ずる
アルミニウム層の腐蝕を防ぎ、耐湿性を向上できるとい
う効果がある。
図面の簡単な説明 第１図は本発明の一実施例の部分斜視図、第２図は従来
の樹脂封止型半導体装置の一例を示す部分平面図である
。
１・・・バンプブ、２・・・金ｚ達・出線、３ａ、３ｂ
、３ｃ、３ｄ、３ｅ、３ｆ・・・電極パッド、４・・・
半導体チップ、５・・・内部配線、６・・・アイランド
、７ａ。
７ｂ、７ｃ、７ｄ・・内部リード。

Claims (1)

    【特許請求の範囲】
  1. アイランド上に搭載した半導体チップに設けた電極パッ
    ドと、前記アイランドの周囲に設けて前記電極パッドと
    電気的に接続した内部リードとを有する樹脂封止型半導
    体装置において、前記内部リードのいずれとも接続され
    ていない空きパッドの表面に設けて腐蝕を防止するボー
    ル状バンプを有することを特徴とする樹脂封止型半導体
    装置。
JP1129165A 1989-05-22 1989-05-22 樹脂封止型半導体装置 Expired - Lifetime JP2819614B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1129165A JP2819614B2 (ja) 1989-05-22 1989-05-22 樹脂封止型半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1129165A JP2819614B2 (ja) 1989-05-22 1989-05-22 樹脂封止型半導体装置

Publications (2)

Publication Number Publication Date
JPH02307225A true JPH02307225A (ja) 1990-12-20
JP2819614B2 JP2819614B2 (ja) 1998-10-30

Family

ID=15002751

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1129165A Expired - Lifetime JP2819614B2 (ja) 1989-05-22 1989-05-22 樹脂封止型半導体装置

Country Status (1)

Country Link
JP (1) JP2819614B2 (ja)

Also Published As

Publication number Publication date
JP2819614B2 (ja) 1998-10-30

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