JPH03153048A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPH03153048A
JPH03153048A JP1292605A JP29260589A JPH03153048A JP H03153048 A JPH03153048 A JP H03153048A JP 1292605 A JP1292605 A JP 1292605A JP 29260589 A JP29260589 A JP 29260589A JP H03153048 A JPH03153048 A JP H03153048A
Authority
JP
Japan
Prior art keywords
pad
crack
produced
resin
outside
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1292605A
Other languages
English (en)
Inventor
Kenji Yokoyama
横山　謙二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP1292605A priority Critical patent/JPH03153048A/ja
Publication of JPH03153048A publication Critical patent/JPH03153048A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05555—Shape in top view being circular or elliptic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0504—14th Group
    • H01L2924/05042—Si3N4

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し、特に外部との接続用パッド
の形状に関するものである。
〔従来の技術〕
従来の半導体装置の外部との接続用パッドの形状は、第
２図に示すように４角形である。
〔発明が解決しようとする課題〕
しかし、前述技術では、ＩＣを樹脂により封止した場合
に、外部との接続用パッドの角の部分に樹脂のストレス
が集中し、パッシベーション膜にクラックが生じ、信頼
性上の問題が生しる。
本発明は、このような従来の欠点を回避し、外部との接
続用パッドの角の部分にはクラックが発生しない信頼性
の高い半導体装置を提供する。
〔課題を解決するための手段〕
本発明の半導体装置は、外部との接続用パッドを有し、
前記パッドの形状が８角形以上の多角形あるいは、丸形
であることを特徴とする。
〔実　施　例〕
以下本発明について、実施例に基づき詳細に説明する。
第１図は本発明の一実施例を示す図であり、（ａ）は、
外部との接続用パッドの平面図、（ｂ）は断面図を示す
。
従来、外部との接続用パッドは第２図に示すように４角
形であり、ＩＣを樹脂により封止した場合、パッドの角
の部分に樹脂のストレスが集中し、第３図に示すように
、シリコン酸化物やシリコン窒化物等を用いた、単層あ
るいは、多層のバッシベーション８３０３にクラック３
０４が発生するという問題がある。このようなりラック
３０４が発生すると、耐湿性が悪くなり、Ａ１合金等を
使用しているパッド電極３０２が腐食してしまう。
しかし、第１図に示すようにパッド部を８角形とするこ
とで樹脂のストレスを分散させ、１つの角に加わる力を
小さくすることで、パッシベーション１漠のクラックを
防止することができる。
さらに、外部との接続のためにボンディングを行なった
場合、第４図のようになり、従来技術、本発明、共に断
面図は（ａ）図であるが、平面図に見ると、従来技術で
は、（ｂ）図のように通常Ａｕを使うボンディングボー
ル４０４が、パッド用電極４０２を覆わない部分が広く
なり、非効率的であり、パッド用７ｔＪｔ４０２にＡ、
９合金を用いた場合、ボンディング・ボール４０４が覆
わない部分は、腐食してしまう。（ｃ）図は本発明のパ
ッド部の平面図であるが、効率的であり、ボンディング
・ボール４０４が、パッド電極４０２を覆わない部分は
ほとんどない。
実施例として、８角形のパッドを例として挙げたが、第
５図に示すように１８角形（（ａ）図）あるいは、丸形
（（ｂ）図）とすることで、さらに信頼性の高いものと
なる。
〔発明の効果〕
以上説明したように本発明によれば、パッド部のパッシ
ベーション膜にクラックが発生することがなく、パッド
用電極が腐食することがない、信頼性の高い半導体装置
を提供することができる。
【図面の簡単な説明】
第１図（ａ）、（ｂ）は本発明の一実施例を示し、（ａ
）は平面図、（ｂ）は断面図である。第２図（ａ）、（
ｂ）は従来の技術によるものであり、（ａ）は平面図、
（ｂ）は断面図である。第３図は、パッシベーション膜
にクラックが発生した場合の断面図である。第４図（ａ
）〜（ｃ）は、ボンディングを行なった場合を示し、（
ａ）は断面図、（ｂ）は従来の技術による平面図、（Ｃ
）は本発明の一実施例を示す平面図である。第５図（ａ
）、（ｂ）はそれぞれ本発明の他の実施例を示す平面図
である。 １０１．２０１．３０１．４０１ ・・・・・・半導体基板 １０２．２０２．３０２．４０２．５０１・・・・・・
パッド用電極 １０３．２０３．３０３．４０３．５０２・・・・・・
パッシベーション膜 ４０４・・・・ボンデインク・ボール 以上

Claims (1)

    【特許請求の範囲】
  1. 外部との接続用パッドを有する半導体装置において、前
    記パッドの形状が８角形以上の多角形あるいは丸形であ
    ることを特徴とする半導体装置。
JP1292605A 1989-11-10 1989-11-10 半導体装置 Pending JPH03153048A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1292605A JPH03153048A (ja) 1989-11-10 1989-11-10 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1292605A JPH03153048A (ja) 1989-11-10 1989-11-10 半導体装置

Publications (1)

Publication Number Publication Date
JPH03153048A true JPH03153048A (ja) 1991-07-01

Family

ID=17783958

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1292605A Pending JPH03153048A (ja) 1989-11-10 1989-11-10 半導体装置

Country Status (1)

Country Link
JP (1) JPH03153048A (ja)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001351920A (ja) * 2000-06-07 2001-12-21 Mitsubishi Electric Corp 半導体装置およびその製造方法
DE10106564A1 (de) * 2001-02-13 2002-08-22 Promos Technologies Inc Bondierungsanschlussflächenanordnung
DE10231647A1 (de) * 2002-07-12 2003-10-23 Infineon Technologies Ag Anschlusspads für integrierte Schaltung
JP2007258596A (ja) * 2006-03-24 2007-10-04 Fujifilm Corp 半導体素子の製造方法及び半導体素子
JP2011238951A (ja) * 2011-07-08 2011-11-24 Renesas Electronics Corp 半導体装置およびその製造方法
US8791568B2 (en) 2011-05-31 2014-07-29 Mitsubishi Electric Corporation Semiconductor device
CN107845622A (zh) * 2017-12-04 2018-03-27 睿力集成电路有限公司 具有硅穿孔的芯片堆叠体及其制造方法

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001351920A (ja) * 2000-06-07 2001-12-21 Mitsubishi Electric Corp 半導体装置およびその製造方法
DE10059773B4 (de) * 2000-06-07 2004-04-29 Mitsubishi Denki K.K. Halbleitervorrichtung
CN1331223C (zh) * 2000-06-07 2007-08-08 三菱电机株式会社 半导体装置及其制造方法
DE10106564A1 (de) * 2001-02-13 2002-08-22 Promos Technologies Inc Bondierungsanschlussflächenanordnung
DE10106564B4 (de) * 2001-02-13 2006-04-20 Promos Technologies, Inc. Bondierungsanschlussflächenanordnung
DE10231647A1 (de) * 2002-07-12 2003-10-23 Infineon Technologies Ag Anschlusspads für integrierte Schaltung
JP2007258596A (ja) * 2006-03-24 2007-10-04 Fujifilm Corp 半導体素子の製造方法及び半導体素子
US8791568B2 (en) 2011-05-31 2014-07-29 Mitsubishi Electric Corporation Semiconductor device
DE102012208246B4 (de) * 2011-05-31 2017-04-06 Mitsubishi Electric Corp. Halbleitervorrichtung
JP2011238951A (ja) * 2011-07-08 2011-11-24 Renesas Electronics Corp 半導体装置およびその製造方法
CN107845622A (zh) * 2017-12-04 2018-03-27 睿力集成电路有限公司 具有硅穿孔的芯片堆叠体及其制造方法

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