JP2007258596A - 半導体素子の製造方法及び半導体素子 - Google Patents
半導体素子の製造方法及び半導体素子 Download PDFInfo
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- JP2007258596A JP2007258596A JP2006083918A JP2006083918A JP2007258596A JP 2007258596 A JP2007258596 A JP 2007258596A JP 2006083918 A JP2006083918 A JP 2006083918A JP 2006083918 A JP2006083918 A JP 2006083918A JP 2007258596 A JP2007258596 A JP 2007258596A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L24/03—Manufacturing methods
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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Abstract
【解決手段】電極パッドを有する半導体素子の製造方法であって、シリコン基板1上方に第1の電極パッド3及び第2の電極パッド5を形成する工程と、第2の電極パッド5表面を覆うパッシベーション膜6を形成する工程と、パッシベーション膜6に開口を形成して第2の電極パッド5を露出させる電極パッド露出工程とを含み、電極パッド露出工程では、平面形状が多角形の角を丸めた形状のマスクを用いて前記開口を形成する。
【選択図】図1
Description
本発明の実施形態を説明するための半導体素子は、次のようにして製造する。
シリコン基板1上にフィールド酸化膜2を形成した後、ポリシリコン等の電極材料をスパッタ法等によって成膜し、成膜した電極材料をフォトリソグラフィ法等によってパターニングして第1の電極パッド3を形成する(図1(a))。
2 フィールド酸化膜
3 第1の電極パッド
4 層間絶縁膜
5 第2の電極パッド
6 パッシベーション膜
K 開口
Claims (4)
- 電極パッドを有する半導体素子の製造方法であって、
基板上方に前記電極パッドを形成する電極パッド形成工程と、
前記電極パッド表面を覆うパッシベーション膜を形成するパッシベーション膜形成工程と、
前記パッシベーション膜に開口を形成して前記電極パッドを露出させる電極パッド露出工程とを含み、
前記電極パッド露出工程では、平面形状が多角形の角を丸めた形状のマスクを用いて前記開口を形成する半導体素子の製造方法。 - 請求項1記載の半導体素子の製造方法であって、
前記電極パッドが、層間絶縁膜を介して複数の電極パッドを積層した複数層構造であり、最上層の電極パッドが前記基板に対して傾斜する傾斜面を有し、
前記電極パッド露出工程では、平面視において、前記傾斜面と前記開口の周縁とが重なるように、前記開口を形成する半導体素子の製造方法。 - 請求項1又は2記載の半導体素子の製造方法であって、
前記半導体素子が固体撮像素子を含む半導体素子の製造方法。 - 請求項1〜3のいずれか記載の製造方法によって形成された半導体素子。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006083918A JP2007258596A (ja) | 2006-03-24 | 2006-03-24 | 半導体素子の製造方法及び半導体素子 |
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JP2006083918A JP2007258596A (ja) | 2006-03-24 | 2006-03-24 | 半導体素子の製造方法及び半導体素子 |
Publications (1)
Publication Number | Publication Date |
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JP2007258596A true JP2007258596A (ja) | 2007-10-04 |
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JP2006083918A Abandoned JP2007258596A (ja) | 2006-03-24 | 2006-03-24 | 半導体素子の製造方法及び半導体素子 |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102012208246B4 (de) * | 2011-05-31 | 2017-04-06 | Mitsubishi Electric Corp. | Halbleitervorrichtung |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58194345A (ja) * | 1982-05-07 | 1983-11-12 | Hitachi Ltd | 半導体装置 |
JPS60183439U (ja) * | 1984-05-16 | 1985-12-05 | 日本電気株式会社 | 集積回路 |
JPH03153048A (ja) * | 1989-11-10 | 1991-07-01 | Seiko Epson Corp | 半導体装置 |
JPH09181113A (ja) * | 1995-12-22 | 1997-07-11 | Sony Corp | 半導体装置の製造方法 |
JP2004079774A (ja) * | 2002-08-19 | 2004-03-11 | Denso Corp | 半導体装置 |
-
2006
- 2006-03-24 JP JP2006083918A patent/JP2007258596A/ja not_active Abandoned
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58194345A (ja) * | 1982-05-07 | 1983-11-12 | Hitachi Ltd | 半導体装置 |
JPS60183439U (ja) * | 1984-05-16 | 1985-12-05 | 日本電気株式会社 | 集積回路 |
JPH03153048A (ja) * | 1989-11-10 | 1991-07-01 | Seiko Epson Corp | 半導体装置 |
JPH09181113A (ja) * | 1995-12-22 | 1997-07-11 | Sony Corp | 半導体装置の製造方法 |
JP2004079774A (ja) * | 2002-08-19 | 2004-03-11 | Denso Corp | 半導体装置 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102012208246B4 (de) * | 2011-05-31 | 2017-04-06 | Mitsubishi Electric Corp. | Halbleitervorrichtung |
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