JPH02247089A - リードフレーム - Google Patents

リードフレーム

Info

Publication number
JPH02247089A
JPH02247089A JP1261933A JP26193389A JPH02247089A JP H02247089 A JPH02247089 A JP H02247089A JP 1261933 A JP1261933 A JP 1261933A JP 26193389 A JP26193389 A JP 26193389A JP H02247089 A JPH02247089 A JP H02247089A
Authority
JP
Japan
Prior art keywords
conductor
bonding
lead frame
width
bonding pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1261933A
Other languages
English (en)
Japanese (ja)
Inventor
Hugo Westerkamp
フーゴ・ベスターカンプ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
LSI Logic Products GmbH
Original Assignee
LSI Logic Products GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by LSI Logic Products GmbH filed Critical LSI Logic Products GmbH
Publication of JPH02247089A publication Critical patent/JPH02247089A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0102—Calcium [Ca]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01088—Radium [Ra]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Laser Beam Processing (AREA)
  • Wire Bonding (AREA)
  • Lasers (AREA)
JP1261933A 1988-10-10 1989-10-06 リードフレーム Pending JPH02247089A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE3834361.4 1988-10-10
DE3834361A DE3834361A1 (de) 1988-10-10 1988-10-10 Anschlussrahmen fuer eine vielzahl von anschluessen

Publications (1)

Publication Number Publication Date
JPH02247089A true JPH02247089A (ja) 1990-10-02

Family

ID=6364724

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1261933A Pending JPH02247089A (ja) 1988-10-10 1989-10-06 リードフレーム

Country Status (4)

Country Link
EP (1) EP0363679A3 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPH02247089A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
CA (1) CA2000338A1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE3834361A1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994013015A1 (en) * 1992-11-24 1994-06-09 Hitachi Construction Machinery Co., Ltd. Lead frame manufacturing method
US5580466A (en) * 1993-04-14 1996-12-03 Hitachi Construction Machinery Co., Ltd. Metal plate processing method, lead frame processing method, lead frame, semiconductor device manufacturing method, and semiconductor device
US5632083A (en) * 1993-08-05 1997-05-27 Hitachi Construction Machinery Co., Ltd. Lead frame fabricating method and lead frame fabricating apparatus

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4101790C1 (en) * 1991-01-18 1992-07-09 Technisch-Wissenschaftliche-Gesellschaft Thiede Und Partner Mbh, O-1530 Teltow, De Chip-support arrangement prodn. - in tape form, in dual-in-line format by film-bond technology
JPH05114685A (ja) * 1991-10-23 1993-05-07 Mitsubishi Electric Corp 半導体装置
EP0644585A3 (en) * 1993-09-20 1995-10-11 Sumitomo Electric Industries Lead frame and manufacturing process.
DE102023202636A1 (de) 2023-03-23 2024-09-26 Robert Bosch Gesellschaft mit beschränkter Haftung Verfahren zur Herstellung eines strukturierten Leistungsmodul-Schaltungsträgers

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6080260A (ja) * 1983-10-07 1985-05-08 Hitachi Micro Comput Eng Ltd 半導体装置用リ−ドフレ−ムとその製造方法
JPS61216354A (ja) * 1985-03-20 1986-09-26 Shinko Electric Ind Co Ltd リ−ドフレ−ムの製造方法
JPH0284757A (ja) * 1988-09-21 1990-03-26 Nec Corp リードフレームの製造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3110235A1 (de) * 1981-03-17 1982-10-21 Trumpf GmbH & Co, 7257 Ditzingen "verfahren und vorrichtung zum brennschneiden mittels eines laserstrahls"
JPS58169940A (ja) * 1982-03-30 1983-10-06 Fujitsu Ltd 半導体装置の製造方法
US4529958A (en) * 1983-05-02 1985-07-16 Dale Electronics, Inc. Electrical resistor
GB2178894B (en) * 1985-08-06 1988-07-27 Gen Electric Co Plc Preparation of fragile devices
DE3608410A1 (de) * 1986-03-13 1987-09-17 Siemens Ag Herstellung von feinstrukturen fuer die halbleiterkontaktierung
US4774635A (en) * 1986-05-27 1988-09-27 American Telephone And Telegraph Company At&T Bell Laboratories Semiconductor package with high density I/O lead connection
FR2624652B1 (fr) * 1987-12-14 1990-08-31 Sgs Thomson Microelectronics Procede de mise en place sur un support, d'un composant electronique, muni de ses contacts

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6080260A (ja) * 1983-10-07 1985-05-08 Hitachi Micro Comput Eng Ltd 半導体装置用リ−ドフレ−ムとその製造方法
JPS61216354A (ja) * 1985-03-20 1986-09-26 Shinko Electric Ind Co Ltd リ−ドフレ−ムの製造方法
JPH0284757A (ja) * 1988-09-21 1990-03-26 Nec Corp リードフレームの製造方法

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994013015A1 (en) * 1992-11-24 1994-06-09 Hitachi Construction Machinery Co., Ltd. Lead frame manufacturing method
US5548890A (en) * 1992-11-24 1996-08-27 Hitachi Construction Machinery Co., Ltd. Lead frame processing method
US5580466A (en) * 1993-04-14 1996-12-03 Hitachi Construction Machinery Co., Ltd. Metal plate processing method, lead frame processing method, lead frame, semiconductor device manufacturing method, and semiconductor device
US5632083A (en) * 1993-08-05 1997-05-27 Hitachi Construction Machinery Co., Ltd. Lead frame fabricating method and lead frame fabricating apparatus
WO2004085108A1 (ja) * 1993-08-05 2004-10-07 Nobuhiko Tada リードフレーム加工方法及びリードフレーム加工装置

Also Published As

Publication number Publication date
DE3834361A1 (de) 1990-04-12
DE3834361C2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1990-08-16
CA2000338A1 (en) 1990-04-10
EP0363679A3 (de) 1990-07-18
EP0363679A2 (de) 1990-04-18

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