JPH0210575B2 - - Google Patents

Info

Publication number
JPH0210575B2
JPH0210575B2 JP55063573A JP6357380A JPH0210575B2 JP H0210575 B2 JPH0210575 B2 JP H0210575B2 JP 55063573 A JP55063573 A JP 55063573A JP 6357380 A JP6357380 A JP 6357380A JP H0210575 B2 JPH0210575 B2 JP H0210575B2
Authority
JP
Japan
Prior art keywords
groove
film
trench
phosphosilicate glass
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP55063573A
Other languages
English (en)
Japanese (ja)
Other versions
JPS56160050A (en
Inventor
Junji Sakurai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=13233122&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=JPH0210575(B2) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP6357380A priority Critical patent/JPS56160050A/ja
Priority to DE8181302078T priority patent/DE3174383D1/de
Priority to IE1040/81A priority patent/IE51992B1/en
Priority to EP81302078A priority patent/EP0041776B2/en
Priority to US06/263,280 priority patent/US4404735A/en
Publication of JPS56160050A publication Critical patent/JPS56160050A/ja
Publication of JPH0210575B2 publication Critical patent/JPH0210575B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)
JP6357380A 1980-05-14 1980-05-14 Semiconductor device and manufacture thereof Granted JPS56160050A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP6357380A JPS56160050A (en) 1980-05-14 1980-05-14 Semiconductor device and manufacture thereof
DE8181302078T DE3174383D1 (en) 1980-05-14 1981-05-11 Method of manufacturing a semiconductor device comprising an isolation structure
IE1040/81A IE51992B1 (en) 1980-05-14 1981-05-11 Method for manufacturing a semiconductor device
EP81302078A EP0041776B2 (en) 1980-05-14 1981-05-11 Method of manufacturing a semiconductor device comprising an isolation structure
US06/263,280 US4404735A (en) 1980-05-14 1981-05-13 Method for manufacturing a field isolation structure for a semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6357380A JPS56160050A (en) 1980-05-14 1980-05-14 Semiconductor device and manufacture thereof

Publications (2)

Publication Number Publication Date
JPS56160050A JPS56160050A (en) 1981-12-09
JPH0210575B2 true JPH0210575B2 (OSRAM) 1990-03-08

Family

ID=13233122

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6357380A Granted JPS56160050A (en) 1980-05-14 1980-05-14 Semiconductor device and manufacture thereof

Country Status (5)

Country Link
US (1) US4404735A (OSRAM)
EP (1) EP0041776B2 (OSRAM)
JP (1) JPS56160050A (OSRAM)
DE (1) DE3174383D1 (OSRAM)
IE (1) IE51992B1 (OSRAM)

Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4506435A (en) * 1981-07-27 1985-03-26 International Business Machines Corporation Method for forming recessed isolated regions
US4544576A (en) * 1981-07-27 1985-10-01 International Business Machines Corporation Deep dielectric isolation by fused glass
US4492717A (en) * 1981-07-27 1985-01-08 International Business Machines Corporation Method for forming a planarized integrated circuit
US4532701A (en) * 1981-08-21 1985-08-06 Tokyo Shibaura Denki Kabushiki Kaisha Method of manufacturing semiconductor device
FR2513016A1 (fr) * 1981-09-14 1983-03-18 Radiotechnique Compelec Transistor v mos haute tension, et son procede de fabrication
JPS58115832A (ja) * 1981-12-28 1983-07-09 Fujitsu Ltd 半導体装置の製造方法
JPS58210634A (ja) * 1982-05-31 1983-12-07 Toshiba Corp 半導体装置の製造方法
JPS59106133A (ja) * 1982-12-09 1984-06-19 Nec Corp 集積回路装置
JPS59119848A (ja) * 1982-12-27 1984-07-11 Fujitsu Ltd 半導体装置の製造方法
US4494303A (en) * 1983-03-31 1985-01-22 At&T Bell Laboratories Method of making dielectrically isolated silicon devices
JPS6042855A (ja) * 1983-08-19 1985-03-07 Hitachi Ltd 半導体装置
JPH073858B2 (ja) * 1984-04-11 1995-01-18 株式会社日立製作所 半導体装置の製造方法
JPS618945A (ja) * 1984-06-25 1986-01-16 Nec Corp 半導体集積回路装置
US4583282A (en) * 1984-09-14 1986-04-22 Motorola, Inc. Process for self-aligned buried layer, field guard, and isolation
US4574469A (en) * 1984-09-14 1986-03-11 Motorola, Inc. Process for self-aligned buried layer, channel-stop, and isolation
US4656497A (en) * 1984-11-01 1987-04-07 Ncr Corporation Trench isolation structures
US4571819A (en) * 1984-11-01 1986-02-25 Ncr Corporation Method for forming trench isolation structures
US4665010A (en) * 1985-04-29 1987-05-12 International Business Machines Corporation Method of fabricating photopolymer isolation trenches in the surface of a semiconductor wafer
US4681795A (en) * 1985-06-24 1987-07-21 The United States Of America As Represented By The Department Of Energy Planarization of metal films for multilevel interconnects
US4665007A (en) * 1985-08-19 1987-05-12 International Business Machines Corporation Planarization process for organic filling of deep trenches
JP2584754B2 (ja) * 1986-12-01 1997-02-26 キヤノン株式会社 通信装置
JPH0834242B2 (ja) * 1988-12-08 1996-03-29 日本電気株式会社 半導体装置およびその製造方法
DE69125886T2 (de) * 1990-05-29 1997-11-20 Semiconductor Energy Lab Dünnfilmtransistoren
JPH05129296A (ja) * 1991-11-05 1993-05-25 Fujitsu Ltd 導電膜の平坦化方法
US5646450A (en) * 1994-06-01 1997-07-08 Raytheon Company Semiconductor structures and method of manufacturing
US5773309A (en) * 1994-10-14 1998-06-30 The Regents Of The University Of California Method for producing silicon thin-film transistors with enhanced forward current drive
JP3180599B2 (ja) * 1995-01-24 2001-06-25 日本電気株式会社 半導体装置およびその製造方法
US6114741A (en) * 1996-12-13 2000-09-05 Texas Instruments Incorporated Trench isolation of a CMOS structure
TW347576B (en) * 1996-12-18 1998-12-11 Siemens Ag Method to produce an integrated circuit arrangement
US6535535B1 (en) * 1999-02-12 2003-03-18 Semiconductor Energy Laboratory Co., Ltd. Laser irradiation method, laser irradiation apparatus, and semiconductor device
US7374974B1 (en) * 2001-03-22 2008-05-20 T-Ram Semiconductor, Inc. Thyristor-based device with trench dielectric material
JP3559971B2 (ja) * 2001-12-11 2004-09-02 日産自動車株式会社 炭化珪素半導体装置およびその製造方法
US7615393B1 (en) 2008-10-29 2009-11-10 Innovalight, Inc. Methods of forming multi-doped junctions on a substrate
EP2826072B1 (en) * 2012-03-14 2019-07-17 IMEC vzw Method for fabricating photovoltaic cells with plated contacts
JP2014130922A (ja) * 2012-12-28 2014-07-10 Toshiba Corp 半導体装置及びその製造方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1461943A (en) * 1973-02-21 1977-01-19 Raytheon Co Semi-conductor devices
JPS50118672A (OSRAM) * 1974-03-01 1975-09-17
US3998673A (en) * 1974-08-16 1976-12-21 Pel Chow Method for forming electrically-isolated regions in integrated circuits utilizing selective epitaxial growth
JPS51146192A (en) * 1975-06-11 1976-12-15 Fujitsu Ltd Diode device fabrication method
JPS5255877A (en) * 1975-11-01 1977-05-07 Fujitsu Ltd Semiconductor device
JPS5422168A (en) * 1977-07-20 1979-02-19 Toshiba Corp Glass coating method for semiconductor element
JPS54147789A (en) * 1978-05-11 1979-11-19 Matsushita Electric Ind Co Ltd Semiconductor divice and its manufacture
GB2023926B (en) * 1978-06-22 1983-03-16 Western Electric Co Conductors for semiconductor devices
JPS5534442A (en) * 1978-08-31 1980-03-11 Fujitsu Ltd Preparation of semiconductor device
JPS5572052A (en) * 1978-11-27 1980-05-30 Fujitsu Ltd Preparation of semiconductor device
US4269636A (en) * 1978-12-29 1981-05-26 Harris Corporation Method of fabricating self-aligned bipolar transistor process and device utilizing etching and self-aligned masking
CA1174285A (en) * 1980-04-28 1984-09-11 Michelangelo Delfino Laser induced flow of integrated circuit structure materials
US4284659A (en) * 1980-05-12 1981-08-18 Bell Telephone Laboratories Insulation layer reflow

Also Published As

Publication number Publication date
EP0041776A2 (en) 1981-12-16
US4404735A (en) 1983-09-20
IE51992B1 (en) 1987-05-13
EP0041776B2 (en) 1990-03-14
EP0041776A3 (en) 1983-12-21
JPS56160050A (en) 1981-12-09
IE811040L (en) 1981-11-14
DE3174383D1 (en) 1986-05-22
EP0041776B1 (en) 1986-04-16

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