JPH01208012A - フリップフロップ回路 - Google Patents

フリップフロップ回路

Info

Publication number
JPH01208012A
JPH01208012A JP63033338A JP3333888A JPH01208012A JP H01208012 A JPH01208012 A JP H01208012A JP 63033338 A JP63033338 A JP 63033338A JP 3333888 A JP3333888 A JP 3333888A JP H01208012 A JPH01208012 A JP H01208012A
Authority
JP
Japan
Prior art keywords
circuit
input
flip
flop
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63033338A
Other languages
English (en)
Japanese (ja)
Inventor
Akira Aso
麻生　明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63033338A priority Critical patent/JPH01208012A/ja
Priority to US07/310,443 priority patent/US4933575A/en
Publication of JPH01208012A publication Critical patent/JPH01208012A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Tests Of Electronic Circuits (AREA)
JP63033338A 1988-02-15 1988-02-15 フリップフロップ回路 Pending JPH01208012A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP63033338A JPH01208012A (ja) 1988-02-15 1988-02-15 フリップフロップ回路
US07/310,443 US4933575A (en) 1988-02-15 1989-02-14 Electric circuit interchangeable between sequential and combination circuits

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63033338A JPH01208012A (ja) 1988-02-15 1988-02-15 フリップフロップ回路

Publications (1)

Publication Number Publication Date
JPH01208012A true JPH01208012A (ja) 1989-08-22

Family

ID=12383781

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63033338A Pending JPH01208012A (ja) 1988-02-15 1988-02-15 フリップフロップ回路

Country Status (2)

Country Link
US (1) US4933575A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPH01208012A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5394404A (en) * 1992-05-19 1995-02-28 Mitsubishi Denki Kabushiki Kaisha Flip-flop circuit having diagnostic function

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5268598A (en) * 1991-04-25 1993-12-07 Altera Corporation High-density erasable programmable logic device architecture using multiplexer interconnections
US5241224A (en) * 1991-04-25 1993-08-31 Altera Corporation High-density erasable programmable logic device architecture using multiplexer interconnections
US5384499A (en) * 1991-04-25 1995-01-24 Altera Corporation High-density erasable programmable logic device architecture using multiplexer interconnections
US5221865A (en) * 1991-06-21 1993-06-22 Crosspoint Solutions, Inc. Programmable input/output buffer circuit with test capability
US5856792A (en) * 1992-02-24 1999-01-05 Sony Corporation Of America Interrupt driven method of remote control
US5331226A (en) * 1992-07-23 1994-07-19 Xilinx, Inc. Logic cell for field programmable gate array having optional input inverters
US5646547A (en) * 1994-04-28 1997-07-08 Xilinx, Inc. Logic cell which can be configured as a latch without static one's problem
US5365125A (en) * 1992-07-23 1994-11-15 Xilinx, Inc. Logic cell for field programmable gate array having optional internal feedback and optional cascade
US5291079A (en) * 1992-07-23 1994-03-01 Xilinx, Inc. Configuration control unit for programming a field programmable gate array and reading array status
US5386154A (en) * 1992-07-23 1995-01-31 Xilinx, Inc. Compact logic cell for field programmable gate array chip
US5319254A (en) * 1992-07-23 1994-06-07 Xilinx, Inc. Logic cell which can be configured as a latch without static one's problem
US5414380A (en) * 1993-04-19 1995-05-09 Motorola, Inc. Integrated circuit with an active-level configurable and method therefor
US5486775A (en) * 1993-11-22 1996-01-23 Altera Corporation Multiplexer structures for use in making controllable interconnections in integrated circuits.
US5684422A (en) * 1995-01-25 1997-11-04 Advanced Micro Devices, Inc. Pipelined microprocessor including a high speed single-clock latch circuit
WO1996027945A1 (en) * 1995-03-08 1996-09-12 Advanced Micro Devices, Inc. Conditional latching mechanism and pipelined microprocessor employing the same
US5970255A (en) 1995-10-16 1999-10-19 Altera Corporation System for coupling programmable logic device to external circuitry which selects a logic standard and uses buffers to modify output and input signals accordingly
JPH11118883A (ja) * 1997-10-20 1999-04-30 Kawasaki Steel Corp 半導体集積回路およびそのテスト方法
US7962681B2 (en) * 2008-01-09 2011-06-14 Qualcomm Incorporated System and method of conditional control of latch circuit devices

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4742252A (en) * 1985-03-29 1988-05-03 Advanced Micro Devices, Inc. Multiple array customizable logic device
US4745573A (en) * 1986-04-11 1988-05-17 Symbolics Inc. Programmable clock generator
US4786829A (en) * 1987-02-24 1988-11-22 Letcher John H Latched fedback memory finite-state-engine
US4783606A (en) * 1987-04-14 1988-11-08 Erich Goetting Programming circuit for programmable logic array I/O cell

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5394404A (en) * 1992-05-19 1995-02-28 Mitsubishi Denki Kabushiki Kaisha Flip-flop circuit having diagnostic function

Also Published As

Publication number Publication date
US4933575B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1992-07-21
US4933575A (en) 1990-06-12

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