JP7442504B2 - 接合メモリ装置およびその製作方法 - Google Patents

接合メモリ装置およびその製作方法 Download PDF

Info

Publication number
JP7442504B2
JP7442504B2 JP2021509877A JP2021509877A JP7442504B2 JP 7442504 B2 JP7442504 B2 JP 7442504B2 JP 2021509877 A JP2021509877 A JP 2021509877A JP 2021509877 A JP2021509877 A JP 2021509877A JP 7442504 B2 JP7442504 B2 JP 7442504B2
Authority
JP
Japan
Prior art keywords
forming
layer
wafer
insulating
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2021509877A
Other languages
English (en)
Japanese (ja)
Other versions
JP2021535597A (ja
Inventor
シェンウェイ・ヤン
ジョンイ・シア
クン・ハン
カン・リ
シャオグアン・ワン
ホンビン・ジュ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yangtze Memory Technologies Co Ltd
Original Assignee
Yangtze Memory Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yangtze Memory Technologies Co Ltd filed Critical Yangtze Memory Technologies Co Ltd
Publication of JP2021535597A publication Critical patent/JP2021535597A/ja
Priority to JP2023203903A priority Critical patent/JP7661454B2/ja
Application granted granted Critical
Publication of JP7442504B2 publication Critical patent/JP7442504B2/ja
Priority to JP2025060441A priority patent/JP2025096318A/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices
    • H10P10/12—Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices
    • H10P10/12—Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates
    • H10P10/128—Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates by direct semiconductor to semiconductor bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H10W80/301—Bonding techniques, e.g. hybrid bonding
    • H10W80/312—Bonding techniques, e.g. hybrid bonding characterised by the direct bonding of electrically conductive pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H10W80/301—Bonding techniques, e.g. hybrid bonding
    • H10W80/327—Bonding techniques, e.g. hybrid bonding characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips

Landscapes

  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
JP2021509877A 2018-11-30 2018-11-30 接合メモリ装置およびその製作方法 Active JP7442504B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2023203903A JP7661454B2 (ja) 2018-11-30 2023-12-01 接合メモリ装置およびその製作方法
JP2025060441A JP2025096318A (ja) 2018-11-30 2025-04-01 接合メモリ装置およびその製作方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2018/118705 WO2020107452A1 (en) 2018-11-30 2018-11-30 Bonded memory device and fabrication methods thereof

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2023203903A Division JP7661454B2 (ja) 2018-11-30 2023-12-01 接合メモリ装置およびその製作方法

Publications (2)

Publication Number Publication Date
JP2021535597A JP2021535597A (ja) 2021-12-16
JP7442504B2 true JP7442504B2 (ja) 2024-03-04

Family

ID=66060256

Family Applications (3)

Application Number Title Priority Date Filing Date
JP2021509877A Active JP7442504B2 (ja) 2018-11-30 2018-11-30 接合メモリ装置およびその製作方法
JP2023203903A Active JP7661454B2 (ja) 2018-11-30 2023-12-01 接合メモリ装置およびその製作方法
JP2025060441A Pending JP2025096318A (ja) 2018-11-30 2025-04-01 接合メモリ装置およびその製作方法

Family Applications After (2)

Application Number Title Priority Date Filing Date
JP2023203903A Active JP7661454B2 (ja) 2018-11-30 2023-12-01 接合メモリ装置およびその製作方法
JP2025060441A Pending JP2025096318A (ja) 2018-11-30 2025-04-01 接合メモリ装置およびその製作方法

Country Status (7)

Country Link
US (3) US11114453B2 (https=)
EP (2) EP4471855A3 (https=)
JP (3) JP7442504B2 (https=)
KR (1) KR102482697B1 (https=)
CN (2) CN111739792B (https=)
TW (1) TWI694596B (https=)
WO (1) WO2020107452A1 (https=)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11018133B2 (en) * 2009-10-12 2021-05-25 Monolithic 3D Inc. 3D integrated circuit
US10840205B2 (en) 2017-09-24 2020-11-17 Invensas Bonding Technologies, Inc. Chemical mechanical polishing for hybrid bonding
US11056348B2 (en) 2018-04-05 2021-07-06 Invensas Bonding Technologies, Inc. Bonding surfaces for microelectronics
US11393779B2 (en) 2018-06-13 2022-07-19 Invensas Bonding Technologies, Inc. Large metal pads over TSV
US11749645B2 (en) 2018-06-13 2023-09-05 Adeia Semiconductor Bonding Technologies Inc. TSV as pad
US11011494B2 (en) 2018-08-31 2021-05-18 Invensas Bonding Technologies, Inc. Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics
US11158573B2 (en) 2018-10-22 2021-10-26 Invensas Bonding Technologies, Inc. Interconnect structures
US11264357B1 (en) 2020-10-20 2022-03-01 Invensas Corporation Mixed exposure for large die
WO2022147429A1 (en) 2020-12-28 2022-07-07 Invensas Bonding Technologies, Inc. Structures with through-substrate vias and methods for forming the same
CN116762163A (zh) 2020-12-28 2023-09-15 美商艾德亚半导体接合科技有限公司 具有贯穿衬底过孔的结构及其形成方法
US11842979B2 (en) * 2021-03-11 2023-12-12 Nanya Technology Corporation Semiconductor device and method of manufacturing the same
EP4139954B1 (en) * 2021-03-30 2024-10-16 Yangtze Memory Technologies Co., Ltd. Method for fabricating three-dimensional semiconductor device using buried stop layer in substrate
US12288719B2 (en) * 2022-04-13 2025-04-29 SanDisk Technologies, Inc. Semiconductor device manufacturing process including forming a bonded assembly and substrate recycling
CN115776820B (zh) * 2022-11-04 2026-04-07 长江存储科技有限责任公司 半导体结构及其制造方法、存储器、存储器系统
KR20250091914A (ko) * 2023-12-14 2025-06-23 삼성전자주식회사 반도체 장치의 제조 방법
US20250285992A1 (en) * 2024-03-05 2025-09-11 Applied Materials, Inc. Methods and structures for reducing warpage

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000323714A (ja) 1999-05-10 2000-11-24 Toshiba Corp 多結晶シリコン素子およびその製造方法
JP2009524221A (ja) 2006-01-17 2009-06-25 インターナショナル・ビジネス・マシーンズ・コーポレーション Ｍｏｓｆｅｔゲート電極のランディング・パッドのための構造および方法
JP2012059966A (ja) 2010-09-09 2012-03-22 Toshiba Corp 半導体記憶装置及びその製造方法
WO2016060274A1 (ja) 2014-10-17 2016-04-21 ボンドテック株式会社 基板どうしの接合方法、基板接合装置
JP2016062901A (ja) 2014-09-12 2016-04-25 株式会社東芝 半導体記憶装置及びその製造方法
JP2017521853A (ja) 2014-05-19 2017-08-03 クアルコム，インコーポレイテッド ３次元（３ｄ）集積回路（ｉｃ）（３ｄｉｃ）および関連のシステムを構築するための方法
WO2017155002A1 (ja) 2016-03-11 2017-09-14 ボンドテック株式会社 基板接合方法
JP2018528622A (ja) 2015-08-25 2018-09-27 インヴェンサス ボンディング テクノロジーズ インコーポレイテッド 導電性バリアのダイレクトハイブリッドボンディング

Family Cites Families (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7052941B2 (en) 2003-06-24 2006-05-30 Sang-Yun Lee Method for making a three-dimensional integrated circuit structure
US5858831A (en) * 1998-02-27 1999-01-12 Vanguard International Semiconductor Corporation Process for fabricating a high performance logic and embedded dram devices on a single semiconductor chip
US7608927B2 (en) * 2002-08-29 2009-10-27 Micron Technology, Inc. Localized biasing for silicon on insulator structures
JP2005197602A (ja) * 2004-01-09 2005-07-21 Renesas Technology Corp 半導体装置およびその製造方法
KR100604871B1 (ko) * 2004-06-17 2006-07-31 삼성전자주식회사 상보형 불휘발성 메모리 소자와 그 동작 방법과 그 제조 방법과 그를 포함하는 논리소자 및 반도체 장치
US7166520B1 (en) * 2005-08-08 2007-01-23 Silicon Genesis Corporation Thin handle substrate method and structure for fabricating devices using one or more films provided by a layer transfer process
SG134187A1 (en) * 2006-01-13 2007-08-29 Tezzaron Semiconductor S Pte L Stacked wafer for 3d integration
EP1906441A1 (en) * 2006-09-29 2008-04-02 Schott Advanced Packaging Singapore Pte. Ldt. Wafer with semiconductor devices and method of manufacturing the same
US20080277778A1 (en) * 2007-05-10 2008-11-13 Furman Bruce K Layer Transfer Process and Functionally Enhanced Integrated Circuits Products Thereby
US7847374B1 (en) * 2007-07-06 2010-12-07 Chih-Hsin Wang Non-volatile memory cell array and logic
KR20100048610A (ko) * 2008-10-31 2010-05-11 삼성전자주식회사 반도체 패키지 및 그 형성 방법
JP2010123664A (ja) 2008-11-18 2010-06-03 Elpida Memory Inc 不揮発性メモリ装置
US7897477B2 (en) * 2009-01-21 2011-03-01 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming an isolation structure
US8058137B1 (en) * 2009-04-14 2011-11-15 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
JP2011003645A (ja) 2009-06-17 2011-01-06 Sharp Corp 半導体装置およびその製造方法
CN102263041B (zh) * 2010-05-27 2013-02-13 中国科学院上海微系统与信息技术研究所 多层堆叠电阻转换存储器的制造方法
CN101894771B (zh) * 2010-06-22 2012-02-22 中国科学院上海微系统与信息技术研究所 多层堆叠电阻转换存储器的制造方法
CN102034804B (zh) * 2010-10-19 2013-03-13 中国科学院上海微系统与信息技术研究所 多层堆叠的存储器及其制造方法
CN102468284B (zh) * 2010-11-10 2014-04-16 中国科学院微电子研究所 堆叠的半导体器件及其制造方法
US8557677B2 (en) * 2010-11-10 2013-10-15 Institute of Microelectronics, Chinese Academy of Sciences Stack-type semiconductor device and method for manufacturing the same
CN102122636B (zh) * 2010-12-08 2013-06-19 中国科学院上海微系统与信息技术研究所 三维电阻转换存储芯片制备方法
US20120168935A1 (en) * 2011-01-03 2012-07-05 Nanya Technology Corp. Integrated circuit device and method for preparing the same
CN102760726B (zh) * 2011-04-27 2015-04-01 中芯国际集成电路制造(上海)有限公司 半导体检测结构及其形成方法、检测方法
CN102214649B (zh) * 2011-05-25 2013-03-13 映瑞光电科技(上海)有限公司 一种led封装结构及其制备方法
KR20130060065A (ko) * 2011-11-29 2013-06-07 에스케이하이닉스 주식회사 비휘발성 메모리 장치 및 이의 제조 방법
US8772136B2 (en) * 2012-05-30 2014-07-08 United Microelectronics Corporation Method for fabricating semiconductor device
KR102046976B1 (ko) 2012-12-04 2019-12-02 삼성전자주식회사 반도체 메모리 장치 및 그 제조 방법
CN103904035B (zh) * 2014-03-05 2016-09-21 清华大学 Tcat结构及其形成方法
CN104241508A (zh) * 2014-09-22 2014-12-24 山东浪潮华光光电子股份有限公司 一种白光led芯片及制备方法
US9449987B1 (en) * 2015-08-21 2016-09-20 Sandisk Technologies Llc Three dimensional memory device with epitaxial semiconductor pedestal for peripheral transistors
US9543318B1 (en) * 2015-08-21 2017-01-10 Sandisk Technologies Llc Three dimensional memory device with epitaxial semiconductor pedestal for peripheral transistors
US10269620B2 (en) * 2016-02-16 2019-04-23 Sandisk Technologies Llc Multi-tier memory device with through-stack peripheral contact via structures and method of making thereof
JP2018064758A (ja) 2016-10-19 2018-04-26 ソニーセミコンダクタソリューションズ株式会社 半導体装置、製造方法、および電子機器
US9666573B1 (en) * 2016-10-26 2017-05-30 Micron Technology, Inc. Methods of forming integrated circuitry
JP2018152419A (ja) * 2017-03-10 2018-09-27 東芝メモリ株式会社 半導体記憶装置
JP2018163970A (ja) * 2017-03-24 2018-10-18 東芝メモリ株式会社 半導体装置及びその製造方法
CN107331679A (zh) * 2017-07-05 2017-11-07 广东工业大学 一种csp封装的高压led芯片结构及制作方法
CN107481997A (zh) * 2017-09-05 2017-12-15 中国电子科技集团公司第二十九研究所 一种双层堆叠气密封装结构及方法

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000323714A (ja) 1999-05-10 2000-11-24 Toshiba Corp 多結晶シリコン素子およびその製造方法
JP2009524221A (ja) 2006-01-17 2009-06-25 インターナショナル・ビジネス・マシーンズ・コーポレーション Ｍｏｓｆｅｔゲート電極のランディング・パッドのための構造および方法
JP2012059966A (ja) 2010-09-09 2012-03-22 Toshiba Corp 半導体記憶装置及びその製造方法
JP2017521853A (ja) 2014-05-19 2017-08-03 クアルコム，インコーポレイテッド ３次元（３ｄ）集積回路（ｉｃ）（３ｄｉｃ）および関連のシステムを構築するための方法
JP2016062901A (ja) 2014-09-12 2016-04-25 株式会社東芝 半導体記憶装置及びその製造方法
WO2016060274A1 (ja) 2014-10-17 2016-04-21 ボンドテック株式会社 基板どうしの接合方法、基板接合装置
JP2018528622A (ja) 2015-08-25 2018-09-27 インヴェンサス ボンディング テクノロジーズ インコーポレイテッド 導電性バリアのダイレクトハイブリッドボンディング
WO2017155002A1 (ja) 2016-03-11 2017-09-14 ボンドテック株式会社 基板接合方法

Also Published As

Publication number Publication date
CN109643643A (zh) 2019-04-16
JP2025096318A (ja) 2025-06-26
EP4471855A3 (en) 2025-03-19
US20200176466A1 (en) 2020-06-04
US20210104542A1 (en) 2021-04-08
JP7661454B2 (ja) 2025-04-14
CN109643643B (zh) 2020-08-25
JP2024019275A (ja) 2024-02-08
JP2021535597A (ja) 2021-12-16
CN111739792B (zh) 2021-06-08
EP3844810A4 (en) 2022-06-01
US12232316B2 (en) 2025-02-18
US11114453B2 (en) 2021-09-07
US20250089254A1 (en) 2025-03-13
TWI694596B (zh) 2020-05-21
CN111739792A (zh) 2020-10-02
KR102482697B1 (ko) 2022-12-28
TW202023027A (zh) 2020-06-16
KR20210028209A (ko) 2021-03-11
EP3844810A1 (en) 2021-07-07
EP4471855A2 (en) 2024-12-04
WO2020107452A1 (en) 2020-06-04

Similar Documents

Publication Publication Date Title
JP7661454B2 (ja) 接合メモリ装置およびその製作方法
US11410983B2 (en) Three-dimensional memory device and fabrication method thereof
US11901313B2 (en) Methods for forming three-dimensional memory devices with supporting structure for staircase region
TWI689047B (zh) 用於三維記憶體元件的貫穿陣列接觸
TWI685953B (zh) 使用梳狀繞線結構減少金屬線裝載的記憶元件
TWI693700B (zh) 記憶裝置
CN109314118B (zh) 具有贯穿阵列触点的三维存储器件及其形成方法
KR102748742B1 (ko) 3차원 메모리 소자의 상호연결 구조체
US11647632B2 (en) Three-dimensional memory devices with supporting structure for staircase region
US20250212407A1 (en) Three-dimensional memory devices with supporting structure for staircase region and spacer structure for contact structure and methods for forming the same
JP2022534537A (ja) ソース構造を伴う三次元メモリデバイス、およびその三次元メモリデバイスを形成するための方法
JP2022535024A (ja) 三次元メモリデバイス、および三次元メモリデバイスを形成するための方法
JP2022534430A (ja) 三次元メモリデバイス、および三次元メモリデバイスを形成するための方法
JP2022534943A (ja) ソース構造を伴う三次元メモリデバイス、およびその三次元メモリデバイスを形成するための方法
JP2022535517A (ja) 接着層によって連結されるソースコンタクトを伴う三次元メモリデバイス、およびそれを形成するための方法
TW202135301A (zh) 具有源極結構的三維記憶體元件及其形成方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20210219

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20210219

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20220509

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20220627

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20221017

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20221227

C60 Trial request (containing other claim documents, opposition documents)

Free format text: JAPANESE INTERMEDIATE CODE: C60

Effective date: 20221227

A911 Transfer to examiner for re-examination before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20230111

C21 Notice of transfer of a case for reconsideration by examiners before appeal proceedings

Free format text: JAPANESE INTERMEDIATE CODE: C21

Effective date: 20230116

A912 Re-examination (zenchi) completed and case transferred to appeal board

Free format text: JAPANESE INTERMEDIATE CODE: A912

Effective date: 20230217

C211 Notice of termination of reconsideration by examiners before appeal proceedings

Free format text: JAPANESE INTERMEDIATE CODE: C211

Effective date: 20230227

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20231201

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20240220

R150 Certificate of patent or registration of utility model

Ref document number: 7442504

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150