JP7406684B2 - 半導体デバイス内の凹状特徴部を低抵抗率金属で充填する方法 - Google Patents

半導体デバイス内の凹状特徴部を低抵抗率金属で充填する方法 Download PDF

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JP7406684B2
JP7406684B2 JP2021519654A JP2021519654A JP7406684B2 JP 7406684 B2 JP7406684 B2 JP 7406684B2 JP 2021519654 A JP2021519654 A JP 2021519654A JP 2021519654 A JP2021519654 A JP 2021519654A JP 7406684 B2 JP7406684 B2 JP 7406684B2
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metal
layer
recessed feature
recessed
deposition
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JP2022504574A5 (https=
JPWO2020077112A5 (https=
JP2022504574A (ja
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ユ，カイ－フン
オメアラ，デイヴィッド
ジョイ，ニコラス
パタナイク，ギャナランジャン
クラーク，ロバート
タピリー，カンダバラ
隆宏 袴田
ワイダ，コリー
ルーシンク，ゲリット
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Tokyo Electron Ltd
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    • H10P14/6682—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
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    • H10W20/44—Conductive materials thereof
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Plasma & Fusion (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Formation Of Insulating Films (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Chemical Vapour Deposition (AREA)
JP2021519654A 2018-10-10 2019-10-10 半導体デバイス内の凹状特徴部を低抵抗率金属で充填する方法 Active JP7406684B2 (ja)

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Application Number Priority Date Filing Date Title
US201862744038P 2018-10-10 2018-10-10
US62/744,038 2018-10-10
PCT/US2019/055676 WO2020077112A1 (en) 2018-10-10 2019-10-10 Method for filling recessed features in semiconductor devices with a low-resistivity metal

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JP2022504574A JP2022504574A (ja) 2022-01-13
JP2022504574A5 JP2022504574A5 (https=) 2022-10-19
JPWO2020077112A5 JPWO2020077112A5 (https=) 2022-10-19
JP7406684B2 true JP7406684B2 (ja) 2023-12-28

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US (2) US11024535B2 (https=)
JP (1) JP7406684B2 (https=)
KR (1) KR102759932B1 (https=)
CN (1) CN112805818B (https=)
TW (1) TWI835883B (https=)
WO (1) WO2020077112A1 (https=)

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US11823896B2 (en) * 2019-02-22 2023-11-21 Taiwan Semiconductor Manufacturing Co., Ltd. Conductive structure formed by cyclic chemical vapor deposition
US12507408B2 (en) 2020-03-12 2025-12-23 Tokyo Electron Limited Method and structures to reduce resistivity in three-dimensional structures for microelectronic workpieces using material deposited in recesses at edges of holes in a multilayer stack
US20220139776A1 (en) * 2020-11-03 2022-05-05 Tokyo Electron Limited Method for filling recessed features in semiconductor devices with a low-resistivity metal
US20220254683A1 (en) * 2021-02-05 2022-08-11 Tokyo Electron Limited Removal of stray ruthenium metal nuclei for selective ruthenium metal layer formation
US12237216B2 (en) * 2021-03-16 2025-02-25 Tokyo Electron Limited Method for filling recessed features in semiconductor devices with a low-resistivity metal
JP2024523510A (ja) * 2021-07-06 2024-06-28 東京エレクトロン株式会社 自己組織化単分子層を使用する選択的な膜形成
US12598977B2 (en) * 2021-12-21 2026-04-07 Intel Corporation Fill of vias in single and dual damascene structures using self-assembled monolayer
JP7803157B2 (ja) * 2022-02-14 2026-01-21 東京エレクトロン株式会社 凹部にルテニウムを埋め込む方法、及び装置
US12588435B2 (en) * 2022-02-28 2026-03-24 Tokyo Electron Limited Selective inhibition for selective metal deposition
US20240431025A1 (en) * 2023-06-26 2024-12-26 International Business Machines Corporation Corrosion resistant single damascene interconnects

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