CN112805818B - 用低电阻率金属填充半导体器件中的凹陷特征的方法 - Google Patents
用低电阻率金属填充半导体器件中的凹陷特征的方法 Download PDFInfo
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- CN112805818B CN112805818B CN201980066266.7A CN201980066266A CN112805818B CN 112805818 B CN112805818 B CN 112805818B CN 201980066266 A CN201980066266 A CN 201980066266A CN 112805818 B CN112805818 B CN 112805818B
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- H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H10W20/077—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers on sidewalls or on top surfaces of conductors
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- H10P14/42—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a gas or vapour
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- H10P14/668—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials
- H10P14/6681—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si
- H10P14/6682—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
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- H10W20/034—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics bottomless barrier, adhesion or liner layers
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- H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
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- H10W20/057—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches by selectively depositing, e.g. by using selective CVD or plating
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- H10W20/075—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers of multilayered thin functional dielectric layers
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- H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
- H10W20/089—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning
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- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
- H10W20/44—Conductive materials thereof
- H10W20/4403—Conductive materials thereof based on metals, e.g. alloys, metal silicides
- H10W20/4432—Conductive materials thereof based on metals, e.g. alloys, metal silicides the principal metal being a noble metal, e.g. gold
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Plasma & Fusion (AREA)
- Electrodes Of Semiconductors (AREA)
- Formation Of Insulating Films (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
- Chemical Vapour Deposition (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201862744038P | 2018-10-10 | 2018-10-10 | |
| US62/744,038 | 2018-10-10 | ||
| PCT/US2019/055676 WO2020077112A1 (en) | 2018-10-10 | 2019-10-10 | Method for filling recessed features in semiconductor devices with a low-resistivity metal |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112805818A CN112805818A (zh) | 2021-05-14 |
| CN112805818B true CN112805818B (zh) | 2024-10-18 |
Family
ID=70160709
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201980066266.7A Active CN112805818B (zh) | 2018-10-10 | 2019-10-10 | 用低电阻率金属填充半导体器件中的凹陷特征的方法 |
Country Status (6)
| Country | Link |
|---|---|
| US (2) | US11024535B2 (https=) |
| JP (1) | JP7406684B2 (https=) |
| KR (1) | KR102759932B1 (https=) |
| CN (1) | CN112805818B (https=) |
| TW (1) | TWI835883B (https=) |
| WO (1) | WO2020077112A1 (https=) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102759932B1 (ko) | 2018-10-10 | 2025-01-23 | 도쿄엘렉트론가부시키가이샤 | 반도체 소자의 함입형 형상부를 저-저항률 금속으로 충전하기 위한 방법 |
| US11823896B2 (en) * | 2019-02-22 | 2023-11-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Conductive structure formed by cyclic chemical vapor deposition |
| US12507408B2 (en) | 2020-03-12 | 2025-12-23 | Tokyo Electron Limited | Method and structures to reduce resistivity in three-dimensional structures for microelectronic workpieces using material deposited in recesses at edges of holes in a multilayer stack |
| US20220139776A1 (en) * | 2020-11-03 | 2022-05-05 | Tokyo Electron Limited | Method for filling recessed features in semiconductor devices with a low-resistivity metal |
| US20220254683A1 (en) * | 2021-02-05 | 2022-08-11 | Tokyo Electron Limited | Removal of stray ruthenium metal nuclei for selective ruthenium metal layer formation |
| US12237216B2 (en) * | 2021-03-16 | 2025-02-25 | Tokyo Electron Limited | Method for filling recessed features in semiconductor devices with a low-resistivity metal |
| JP2024523510A (ja) * | 2021-07-06 | 2024-06-28 | 東京エレクトロン株式会社 | 自己組織化単分子層を使用する選択的な膜形成 |
| US12598977B2 (en) * | 2021-12-21 | 2026-04-07 | Intel Corporation | Fill of vias in single and dual damascene structures using self-assembled monolayer |
| JP7803157B2 (ja) * | 2022-02-14 | 2026-01-21 | 東京エレクトロン株式会社 | 凹部にルテニウムを埋め込む方法、及び装置 |
| US12588435B2 (en) * | 2022-02-28 | 2026-03-24 | Tokyo Electron Limited | Selective inhibition for selective metal deposition |
| US20240431025A1 (en) * | 2023-06-26 | 2024-12-26 | International Business Machines Corporation | Corrosion resistant single damascene interconnects |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20060062926A (ko) * | 2004-12-06 | 2006-06-12 | 주식회사 하이닉스반도체 | 반도체 소자의 금속배선 형성방법 |
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| KR20060062926A (ko) * | 2004-12-06 | 2006-06-12 | 주식회사 하이닉스반도체 | 반도체 소자의 금속배선 형성방법 |
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| KR102759932B1 (ko) | 2025-01-23 |
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| US11024535B2 (en) | 2021-06-01 |
| WO2020077112A1 (en) | 2020-04-16 |
| JP2022504574A (ja) | 2022-01-13 |
| TW202029286A (zh) | 2020-08-01 |
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