JP7251865B2 - 柱状半導体素子を用いたメモリ装置と、その製造方法 - Google Patents

柱状半導体素子を用いたメモリ装置と、その製造方法 Download PDF

Info

Publication number
JP7251865B2
JP7251865B2 JP2022534323A JP2022534323A JP7251865B2 JP 7251865 B2 JP7251865 B2 JP 7251865B2 JP 2022534323 A JP2022534323 A JP 2022534323A JP 2022534323 A JP2022534323 A JP 2022534323A JP 7251865 B2 JP7251865 B2 JP 7251865B2
Authority
JP
Japan
Prior art keywords
layer
impurity region
layers
semiconductor
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2022534323A
Other languages
English (en)
Japanese (ja)
Other versions
JPWO2022097251A1 (https=
JPWO2022097251A5 (https=
Inventor
望 原田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Unisantis Electronics Singapore Pte Ltd
Original Assignee
Unisantis Electronics Singapore Pte Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Unisantis Electronics Singapore Pte Ltd filed Critical Unisantis Electronics Singapore Pte Ltd
Publication of JPWO2022097251A1 publication Critical patent/JPWO2022097251A1/ja
Publication of JPWO2022097251A5 publication Critical patent/JPWO2022097251A5/ja
Application granted granted Critical
Publication of JP7251865B2 publication Critical patent/JP7251865B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/20DRAM devices comprising floating-body transistors, e.g. floating-body cells
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/01Manufacture or treatment
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B61/00Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H10B61/20Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
    • H10B61/22Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B63/00Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/10Phase change RAM [PCRAM, PRAM] devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B63/00Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/30Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
    • H10B63/34Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors of the vertical channel field-effect transistor type
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/02Manufacture or treatment characterised by using material-based technologies
    • H10D84/03Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/837Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET] comprising vertical IGFETs

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP2022534323A 2020-11-06 2020-11-06 柱状半導体素子を用いたメモリ装置と、その製造方法 Active JP7251865B2 (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2020/041461 WO2022097251A1 (ja) 2020-11-06 2020-11-06 柱状半導体素子を用いたメモリ装置と、その製造方法

Publications (3)

Publication Number Publication Date
JPWO2022097251A1 JPWO2022097251A1 (https=) 2022-05-12
JPWO2022097251A5 JPWO2022097251A5 (https=) 2022-10-17
JP7251865B2 true JP7251865B2 (ja) 2023-04-04

Family

ID=81456983

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2022534323A Active JP7251865B2 (ja) 2020-11-06 2020-11-06 柱状半導体素子を用いたメモリ装置と、その製造方法

Country Status (4)

Country Link
US (1) US12520479B2 (https=)
JP (1) JP7251865B2 (https=)
TW (1) TWI800947B (https=)
WO (1) WO2022097251A1 (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117199052A (zh) * 2022-05-26 2023-12-08 长鑫存储技术有限公司 半导体结构及半导体存储器
CN117580358A (zh) 2022-08-04 2024-02-20 长鑫存储技术有限公司 一种半导体结构及其制备方法
EP4503129A4 (en) * 2022-08-19 2025-08-13 Changxin Memory Tech Inc SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SAME

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009096469A1 (ja) 2008-01-29 2009-08-06 Unisantis Electronics (Japan) Ltd. 半導体記憶装置
WO2009096468A1 (ja) 2008-01-29 2009-08-06 Unisantis Electronics (Japan) Ltd. 半導体記憶装置およびメモリ混載半導体装置、並びにそれらの製造方法
US20190206861A1 (en) 2017-12-29 2019-07-04 Micron Technology, Inc. Semiconductor devices including control logic structures, electronic systems, and related methods

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2703970B2 (ja) 1989-01-17 1998-01-26 株式会社東芝 Mos型半導体装置
JP2748072B2 (ja) * 1992-07-03 1998-05-06 三菱電機株式会社 半導体装置およびその製造方法
JPH1079482A (ja) * 1996-08-09 1998-03-24 Rai Hai 超高密度集積回路
KR100675297B1 (ko) * 2005-12-19 2007-01-29 삼성전자주식회사 캐패시터가 없는 동적 메모리 셀을 구비한 반도체 메모리장치 및 이 장치의 배치 방법
US8212298B2 (en) * 2008-01-29 2012-07-03 Unisantis Electronics Singapore Pte Ltd. Semiconductor storage device and methods of producing it
SG166752A1 (en) * 2009-05-22 2010-12-29 Unisantis Electronics Jp Ltd Semiconductor memory device and production method therefor
US9559216B2 (en) * 2011-06-06 2017-01-31 Micron Technology, Inc. Semiconductor memory device and method for biasing same
WO2015059789A1 (ja) * 2013-10-23 2015-04-30 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド 半導体装置
JP2015149413A (ja) * 2014-02-06 2015-08-20 株式会社東芝 半導体記憶装置及びその製造方法
US10014316B2 (en) * 2016-10-18 2018-07-03 Sandisk Technologies Llc Three-dimensional memory device with leakage reducing support pillar structures and method of making thereof
US10453798B2 (en) * 2017-09-27 2019-10-22 Sandisk Technologies Llc Three-dimensional memory device with gated contact via structures and method of making thereof
US20190312050A1 (en) * 2018-04-10 2019-10-10 Macronix International Co., Ltd. String select line gate oxide method for 3d vertical channel nand memory
US10763273B2 (en) * 2018-08-23 2020-09-01 Macronix International Co., Ltd. Vertical GAA flash memory including two-transistor memory cells
US11018151B2 (en) * 2018-09-26 2021-05-25 Sandisk Technologies Llc Three-dimensional flat NAND memory device including wavy word lines and method of making the same
JP2020150234A (ja) * 2019-03-15 2020-09-17 キオクシア株式会社 半導体記憶装置
US10854629B2 (en) * 2019-03-28 2020-12-01 Sandisk Technologies Llc Three-dimensional memory device containing asymmetric, different size support pillars and method for making the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009096469A1 (ja) 2008-01-29 2009-08-06 Unisantis Electronics (Japan) Ltd. 半導体記憶装置
WO2009096468A1 (ja) 2008-01-29 2009-08-06 Unisantis Electronics (Japan) Ltd. 半導体記憶装置およびメモリ混載半導体装置、並びにそれらの製造方法
US20190206861A1 (en) 2017-12-29 2019-07-04 Micron Technology, Inc. Semiconductor devices including control logic structures, electronic systems, and related methods

Also Published As

Publication number Publication date
TWI800947B (zh) 2023-05-01
JPWO2022097251A1 (https=) 2022-05-12
WO2022097251A1 (ja) 2022-05-12
TW202224157A (zh) 2022-06-16
US20230276612A1 (en) 2023-08-31
US12520479B2 (en) 2026-01-06

Similar Documents

Publication Publication Date Title
US10651181B2 (en) Method for producing pillar-shaped semiconductor device
US10658371B2 (en) Method for producing a pillar-shaped semiconductor memory device
US11862464B2 (en) Method for manufacturing three-dimensional semiconductor device
US12520479B2 (en) Memory device including pillar-shaped semiconductor element and method for manufacturing the same
US12183391B2 (en) Semiconductor memory device and manufacturing method of semiconductor memory device
US12029022B2 (en) Pillar-shaped semiconductor device and method for producing the same
US20220139928A1 (en) Pillar-shaped semiconductor device and method for producing the same
WO2015071983A1 (ja) 半導体装置、及び半導体装置の製造方法
JPWO2021005789A5 (https=)
US10229916B2 (en) Method for producing pillar-shaped semiconductor device
US10410932B2 (en) Method for producing pillar-shaped semiconductor device
US10304960B2 (en) Vertical transistor with multi-doping S/D regions
TWI811667B (zh) 半導體結構
WO2024127517A1 (ja) 半導体素子を用いたメモリ装置の製造方法
WO2023188379A1 (ja) 柱状半導体記憶装置と、その製造方法
JP7601424B2 (ja) 柱状半導体装置と、その製造方法
JP7056994B2 (ja) 柱状半導体装置の製造方法
TWI781747B (zh) 柱狀半導體裝置及其製造方法
JP6799872B2 (ja) 柱状半導体装置と、その製造方法。
WO2023188002A1 (ja) 半導体メモリ・デバイス
JP4757317B2 (ja) 半導体集積回路装置の製造方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20220606

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20220606

A871 Explanation of circumstances concerning accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A871

Effective date: 20220606

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20220815

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20221114

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20230213

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20230315

R150 Certificate of patent or registration of utility model

Ref document number: 7251865

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250