WO2022097251A1 - 柱状半導体素子を用いたメモリ装置と、その製造方法 - Google Patents

柱状半導体素子を用いたメモリ装置と、その製造方法 Download PDF

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Publication number
WO2022097251A1
WO2022097251A1 PCT/JP2020/041461 JP2020041461W WO2022097251A1 WO 2022097251 A1 WO2022097251 A1 WO 2022097251A1 JP 2020041461 W JP2020041461 W JP 2020041461W WO 2022097251 A1 WO2022097251 A1 WO 2022097251A1
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layer
semiconductor
impurity region
forming
layers
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French (fr)
Japanese (ja)
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望 原田
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Unisantis Electronics Singapore Pte Ltd
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Unisantis Electronics Singapore Pte Ltd
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Priority to JP2022534323A priority Critical patent/JP7251865B2/ja
Priority to PCT/JP2020/041461 priority patent/WO2022097251A1/ja
Priority to TW110138012A priority patent/TWI800947B/zh
Publication of WO2022097251A1 publication Critical patent/WO2022097251A1/ja
Priority to US18/311,701 priority patent/US12520479B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/20—DRAM devices comprising floating-body transistors, e.g. floating-body cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
    • H10B61/22—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/10—Phase change RAM [PCRAM, PRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
    • H10B63/34—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors of the vertical channel field-effect transistor type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/837—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET] comprising vertical IGFETs

Definitions

  • the present invention relates to a memory device using a columnar semiconductor element and a method for manufacturing the same.
  • the channel In a normal planar MOS transistor, the channel extends horizontally along the upper surface of the semiconductor substrate.
  • the SGT channel extends in a direction perpendicular to the upper surface of the semiconductor substrate (see, for example, Patent Document 1 and Non-Patent Document 1). Therefore, the SGT can increase the density of the semiconductor device as compared with the planar type MOS transistor.
  • DRAM Dynamic Random Access memory
  • PCM Phase change Memory
  • RRAM Resistive Random Access memory, for example, Non-Patent Document 4
  • MRAM Magnetic-resistive Random Access memory, for example, Non-Patent Document 5 that changes the direction of magnetic spin by current to change resistance. It is possible to achieve high integration such as).
  • FIG. 3 shows a schematic structural diagram of the N-channel SGT.
  • Si column the silicon semiconductor column
  • the silicon semiconductor column is referred to as "Si column” having a P-type or i-type (intrinsic type) conductive type, when one is the source, the other is the drain.
  • N + layers 101a and 101b semiconductor regions containing a high concentration of donor impurities are referred to as "N + layers" are formed.
  • the portion of the Si column 100 between the N + layers 101a and 101b serving as the source and drain becomes the channel region 102.
  • the gate insulating layer 103 is formed so as to surround the channel region 102.
  • the gate conductor layer 104 is formed so as to surround the gate insulating layer 103.
  • the N + layers 101a and 101b serving as sources and drains, the channel region 102, the gate insulating layer 103, and the gate conductor layer 104 are formed in a columnar shape as a whole. Then, a capacitor is connected to the N + layer 101b in DRAM, and a variable resistance element 105 is connected in PCM, RRAM, and MRAM.
  • the occupied area of the SGT corresponds to the occupied area of a single source or drain N + layer of the planar MOS transistor.
  • the circuit chip having the SGT can further reduce the chip size as compared with the circuit chip having the planar type MOS transistor.
  • a method for manufacturing a memory device using a columnar semiconductor device element according to the present invention which solves the above problems, is A substrate having a first impurity region at the bottom and a second impurity region at the top as a source or drain, and a region between the first impurity region and the second impurity region as a channel.
  • a columnar semiconductor device having a gate conductor layer surrounding the gate insulating layer.
  • a step of forming the first impurity region by extending it in a band shape in the first direction in a plan view.
  • a step of forming the semiconductor column that overlaps at least a part of the first impurity region In a plan view, a step of forming the semiconductor column that overlaps at least a part of the first impurity region, and In a plan view, a step of forming a semiconductor base including the semiconductor column and the first impurity region and extending in a band shape in the first direction by connecting to the bottom of the semiconductor column.
  • the step of forming the first insulating layer on the outer peripheral portion of the gate conductor layer and In a plan view, the contact hole that overlaps with the first impurity region on the semiconductor table and whose bottom is in contact with the first impurity region and extends in a band shape in the first direction is the first insulation.
  • a step of forming a first conductor layer extending in a band shape in the first direction in contact with the first impurity region at the bottom of the contact hole A step of forming a second insulating layer containing holes or made of a low dielectric constant material in the contact hole on the first conductor layer.
  • a step of forming the semiconductor column by using the first mask material layer as an etching mask and A step of forming a third insulating layer that surrounds the semiconductor column and whose upper surface position is at the bottom position of the first mask material layer or at the top position of the semiconductor column.
  • the third insulating layer, the first impurity layer, and the semiconductor substrate are used. Further has a step of forming the semiconductor table by etching. In a plan view, a part of the second mask material layer protrudes from the third mask material layer on the opposite side of the first conductor layer with the semiconductor column sandwiched in the second direction. Can be.
  • the width of the second conductor layer is within the distance between two points where the outer peripheral line of the gate conductor layer and the straight line extending in the first direction intersect. , Can be formed smaller than the longest line segment.
  • the upper end position of the first conductive layer can be formed lower than the lower end position of the gate conductor layer.
  • the upper end position of the hole can be formed lower than the upper end position of the gate conductor layer.
  • the polarity opposite to the first impurity region or the second impurity region is formed. It is possible to have a step of forming a third impurity region having.
  • the semiconductor column whose dimension in the first direction is longer than the dimension in the second direction can be formed.
  • the step of forming the first impurity layer which is the base of the first impurity region on the substrate, and the step of forming the first impurity layer.
  • a step of forming a second impurity layer on the first semiconductor layer, which becomes a part of the base body of the first semiconductor column and becomes at least a part of the second semiconductor region. can further have.
  • a fourth surface thereof is above the gate conductor layer and below the upper surface of the second impurity layer, and surrounds the outer periphery of the second impurity layer.
  • the memory device using the columnar semiconductor device element according to the present invention which solves the above problems, is A semiconductor pillar that stands perpendicular to the substrate, A first impurity region connected to the bottom of the semiconductor column, overlapping with the semiconductor column at least in part and extending in a band shape in the first direction in a plan view. A second impurity region at the top of the semiconductor column, A gate insulating layer surrounding the semiconductor column between the first impurity region and the second impurity region. The gate conductor layer surrounding the gate insulating layer and In a plan view, a semiconductor table connected to the bottom of the semiconductor column, containing the first impurity region, and extending in a band shape in the first direction.
  • the first insulating layer on the outer peripheral portion of the gate conductor layer and In a plan view in the first insulating layer, it overlaps with the first impurity region on the semiconductor table, and its bottom is in contact with the first impurity region, and is band-shaped in the first direction.
  • the first material layer has a first conductor layer extending in a band shape in the first direction in contact with the first impurity region at the bottom thereof. It is on the first conductor layer and the top surface position is composed of a second insulating layer containing pores lower than the upper end of the gate conductor layer or made of a low dielectric constant material. It has a second conductor layer that is on the second insulating layer, is in contact with the gate conductor layer, and extends in a strip shape in a second direction orthogonal to the first direction in a plan view. , Characterized by that.
  • a part of the semiconductor base surrounding the semiconductor column protrudes in the second direction, sandwiching the semiconductor column, on the side opposite to the first conductor layer.
  • the width of the second conductor layer in the first direction is the longest line segment among the distances between two points where the outer peripheral line of the gate conductor layer and the straight line extending in the first direction intersect. It is characterized by being smaller.
  • the upper end position of the first conductive layer is lower than the lower end position of the gate conductor layer.
  • the semiconductor column having a cross section extending in the first direction is formed in a plan view.
  • FIGS. 1A to 1J (First Embodiment)
  • a is a plan view
  • (b) is a cross-sectional structure diagram along the XX'line of (a)
  • (c) is a cross-sectional structure diagram along the YY'line.
  • N + layers 2a and 2b extending in a band shape in the YY'line direction in a plan view are placed on the upper part of the P layer substrate 1 (an example of the “substrate” in the claims).
  • the P layer 4 is formed by the epitaxial growth method. Then, on the P layer 4, a circular mask material layer 5a, 5b, 5c, 5d (an example of the "first mask material layer” in the claims) in a plan view is N + in a plan view. It is formed so as to partially overlap the layers 2a and 2b.
  • the mask material layers 5a to 5d are used as masks, and the P layer 4 and the upper layers of the P layer substrates 1, N + layers 2a and 2b are etched to form Si columns 7a and 7b. , 7c, 7d (an example of a "semiconductor column" in the claims).
  • the silicon nitriding (SiN) layer 9 (claimed “third”" is provided on the outer periphery of the Si columns 7a to 7d so that the upper surface position thereof is the top of the Si columns 7a to 7d. Is an example of “insulating layer”). Then, the tops of the Si columns 7a to 7d and the side surfaces of the mask material layers 5a to 5d are surrounded by the same width in a plan view, and the silicon oxidation (SiO 2 ) layers 10a, 10b, 10c, and 10d (claimed “" An example of a "second mask material layer”) is formed.
  • the SiO 2 layers 10a to 10d may be formed by covering the mask material layers 5a to 5d, covering the SiO 2 layers (not shown), and then etching by, for example, the RIE (Reactive Ion Etching) method. good.
  • the SiO 2 layers 10a to 10d are formed with the same width around the mask material layers 5a to 5d.
  • the SiO 2 layers 10a to 10d are self-aligned with the Si columns 7a to 7d. ..
  • the SiN layer 9 may be formed after forming a thin SiO 2 layer (not shown) on the side surfaces of the Si columns 7a to 7d.
  • the mask material layers 5a to 5d, the mask material layers 11a and 11b (which is an example of the "third mask material layer” in the patentable range), and the SiO 2 layers 10a to 10d are masked.
  • the SiN layer 9, N + layer 2a, 2b, and the P layer substrate 1 are etched, and the P layer base 12a, 12b composed of the N + layer 2aa, 2bb and the P layer substrate 1a (“semiconductor base” in the patent claim range. Is an example of).
  • 1E (d) shows a plan view of the formed P layer bases 12a and 12b.
  • the P layer bases 12a and 12b have N + layers 2aa and 2bb extending in a band shape in the YY'line direction and a part of the outer periphery of the Si columns 7a to 7d, as shown in FIG. 1E (d). Becomes a protruding shape. Since the P layer bases 12a and 12b of the portion where a part of the outer periphery of the Si columns 7a to 7d protrudes are formed by using the SiN layers 9a and 9b formed in self-alignment with the Si columns 7a to 7d as an etching mask. It is formed by self-alignment with Si columns 7a to 7d.
  • the mask material layers 11a and 11b, the SiO 2 layers 10a to 10d, and the SiN layers 9a and 9b are removed.
  • the SiO 2 layer 13 is formed so as to surround the P layer bases 12a and 12b so that the upper surface position thereof is above the upper surfaces of the P layer bases 12a and 12b.
  • a hafnium oxide (HfO 2 ) layer 14 (an example of the "gate insulating layer” in the claims) to be a gate insulating layer is formed by surrounding the Si columns 7a to 7d by the ALD (Atomic Layer Deposition) method. ..
  • a TiN layer (not shown) that covers the HfO 2 layer 14 and serves as a gate conductor layer and a SiO 2 layer (not shown) are formed.
  • the upper surface is polished to the upper surface of the mask material layers 5a to 5d by the CMP (Chemical Mechanical Polishing) method.
  • the SiO 2 layer and the TiN layer are etched by RIE to the upper part of the Si pillars 7a to 7d on the upper surface to form the TiN layer 15 and the SiO 2 layer 16.
  • the entire SiN layer (not shown) is covered.
  • the SiN layer is etched by the RIE method, and the side surfaces of the mask material layers 5a to 5d and the tops of the Si columns 7a to 7d are surrounded by the same width in a plan view, and the SiN layers 17a, 17b, 17c, Form 17d.
  • the SiO 2 layer 16 is removed.
  • the TiN layer 15 is etched by the RIE method to form the gate conductor layers TiN layers 15a, 15b, 15c, 15d (which is an example of the "gate conductor layer" in the claims. ) Is formed.
  • the SiN layers 17a to 17d which are etching masks, are formed by self-alignment with respect to the Si columns 7a to 7d, the TiN layers 15a to 15d are also self-aligned with respect to the Si columns 7a to 7d. Formed by.
  • a SiO 2 layer (not shown) is formed by covering the whole, and the upper surface is polished so that the upper surface position is the upper surface position of the mask material layers 5a to 5d by the CMP method.
  • Form two layers 20 is formed.
  • the contact holes 21a and 21b (claims "" An example of a "contact hole") is formed.
  • the upper surface is polished by CMP so that the upper surface becomes the upper surface of the mask material layers 5a to 5d.
  • the W layer in the contact holes 21a and 21b is etched by the RIE method, and the bottom of the contact holes 21a and 21b is in contact with the N + layers 2aa and 2bb to form the W layers 22a and 22b (claims "No. 1".
  • An example of "1 conductor layer” is formed.
  • the upper surface positions of the W layers 22a and 22b are formed so as to be lower than the lower end positions of the TiN layers 15a and 15b.
  • a buffer metal layer such as TaN may be formed to reduce the contact resistance between the W layers 22a and 22b and the N + layers 2aa and 2bb.
  • SiO 2 layers 24a and 24b having internal holes 25a and 25b in the contact holes 21a and 21b (an example of the "second insulating layer” in the claims).
  • the upper end positions of the holes 25a and 25b are formed lower than the upper end positions of the TiN layers 15a and 15b.
  • the SiO 2 layers 24a and 24b may be formed of a low dielectric constant material layer such as silicon carbide oxidation (SiOC). In this case, the holes 25a and 25b may or may not be formed.
  • the SiO 2 layers 20, 24a, and 24b are etched by the RIE method so that the upper surface position is lower than the upper end position of the TiN layers 15a, 15b, and the SiO 2 layer 20a (claimed).
  • a W layer (not shown) connected to the TiN layers 15a to 15d is formed on the outer peripheral portions of the TiN layers 15a and 15b.
  • the mask material layers 27a and 27b that overlap with a part of the TiN layers 26a and 26b and extend in a band shape in the XX'line direction are formed.
  • the W layer is etched using the mask material layers 27a and 27b as masks.
  • the W layers 26a and 26b (patented) connected to the TiN layers 15a and 15b and extended in the XX'line direction (an example of the "second direction" of the claims) in a plan view. It is an example of a "second conductor layer” in the claims).
  • the width L1 of the W layers 26a and 26b in the YY'line direction is formed to be smaller than the width L2 of the outer periphery of the gate TiN layers 15a and 15b in the YY'line direction.
  • L2 is the longest line segment among the distances between two points where the outer peripheral lines of the gate TiN layers 15a and 15b and the straight line extending in the YY'line direction intersect.
  • the SiO 2 layer 28 is formed on the outer peripheral portion of the top side surface of the Si columns 7a to 7d. Then, the tops of the Si columns 7a to 7d are covered to form N + layers 29a, 29b, 29c, 29d by, for example, a selective epitaxial method. Then, N + layers 30a, 30b, 30c (not shown) and 30d (not shown) are formed on the tops of the Si columns 7a to 7d by heat diffusion. This forms the selective SGT in the DRAM.
  • the W layers 22a and 22b are bit wire electrodes
  • the W layers 26a and 26b are word wire electrodes. Then, it is connected to the N + layers 29a to 29d, and the capacitor is connected. As a result, the DRAM device is formed on the P layer substrate 1a.
  • the N + layers 2aa and 2bb have been described as being formed on a part of the inside of the Si columns 7a to 7d in a plan view, but may be formed on the entire surface. Further, in RRAM, MRAM, PCM and the like, a variable resistance element whose resistance changes depending on the applied voltage is connected to each of the DRAM capacitors instead of the capacitors. In these elements, the N + layers 2aa and 2bb may be formed on the entire surface inside the Si columns 7a to 7d in a plan view.
  • the N + layers 2aa and 2bb may be formed on the entire surface of the Si columns 7a to 7d in a plan view.
  • the polarities of the impurity regions serving as the source or drain above and below the SGT may be different (see, for example, Non-Patent Document 7).
  • the W layers 22a and 22b are bit wire electrodes, but in RRAM, MRAM, PCM and the like, the W layers 22a and 22b are other than the source wire electrodes and ground wire electrodes. It may be used as an electrode of.
  • the N + layers 30a to 30d formed on the tops of the Si columns 7a to 7d are P, for example, after forming the P layer 4 in FIG. 1B and before forming the mask material layers 5a to 5d.
  • An N + layer formed on the layer 4 by the epitaxial crystal growth method may be used.
  • the step of performing the heat treatment shown in FIG. 1K to diffuse the donor impurities from the N + layers 29a to 29d to the tops of the Si columns 7a to 7d to form the N + layers 30a to 30d becomes unnecessary. ..
  • the gate TiN layers 15a to 15d and the gate are subjected to a long heat treatment at a high temperature so that the lower end of the N + layers 30a to 30d becomes the upper end of the gate TiN layers 15a to 15d in the vertical direction. Damage to the HfO 2 layer 14 which is an insulating layer becomes a problem.
  • FIG. 1B after the P layer 4 is formed, an N + layer is formed on the P layer 4, and the N + layers 30a to 30d are formed from these impurity layers to form the gate TiN as described above. Thermal damage to the layers 15a to 15d and the HfO 2 layer 14 which is the gate insulating layer can be avoided.
  • the N + layers 29a to 29d may or may not be formed.
  • a conductor layer such as a metal or an alloy may be used instead of the N + layers 29a to 29d.
  • the film thickness of the TiN layer 15, which is the gate conductor layer is made thicker than the SiN layers 17a, 17b, 17c, and 17d.
  • the film thickness of the TiN layer 15 is made thinner than the SiN layers 17a, 17b, 17c, and 17d, and a conductor layer such as TaN or an insulating layer such as a SiN layer is provided on the outside of the TiN layer 15 as a protective layer of the TiN layer 15. It may be provided as.
  • the protective layer is left around the side surfaces of the gate TiN layers 15a to 15d.
  • the protective layer on the top side surface of the gate TiN layers 15a to 15d is removed before forming the W layers 26a and 26b in FIG. 1I.
  • the etching rate is higher than that of the SiO 2 layer 20 in the formation of the contact holes 21a and 21b by RIE etching. It is preferable to use a small one, for example, a SiN layer. Instead of this SiN layer, a material layer serving as an etching stopper may be used. Further, after the contact holes 21a and 21b are formed, a thin insulating layer such as a SiN layer serving as an etching stopper is coated inside the contact holes 21a and 21b, and the SiN layer at the bottom of the contact holes 21a and 21b is removed by RIE.
  • W layers 22a and 22b may be formed.
  • the bottom cross-sectional shape of the contact holes 21a and 21b has a minimum area smaller than the upper area in a plan view. It is desirable to form as such.
  • the boron (B) impurities are contained in the N + layers 2a and 2b in a smaller amount than the phosphorus (P) impurities, and then the B impurities are diffused in the P layer substrate 1 by heat treatment to N +.
  • a P + layer may be formed on the outside of the layers 2a and 2b.
  • the P + layer may be formed by the epitaxial crystal growth method before the N + layers 2a and 2b are formed by the epitaxial crystal growth . Moreover, this P + layer may be formed by another method as long as it suits this purpose. Further, in the capacitorless DRAM, an impurity region having the polarity opposite to the polarity of the impurity region may be formed on the outside of one of the upper or lower impurity regions by the same method.
  • the present embodiment provides the following features. 1.
  • the TiN layers 15a to 15d which are gate electrodes
  • contact holes 21a and 21b are formed, and an N + layer is formed at the bottom of the contact holes 21a and 21b.
  • the bit wiring W layers 22a and 22b connected to 2aa and 2bb are formed.
  • SiO 2 layers 24a and 24b including pores 25a and 25b which are effectively low dielectric constant layers are formed.
  • the word wiring W layers 26a and 26b connected to the gate electrodes TiN layers 15a to 15d are formed on the SiO 2 layers 20a, 24aa and 24bb with the bit wiring W layers 22a and 22b in a plan view. Formed at right angles.
  • the SiO 2 layers 24aa and 24bb and the bit wire W layers 22a and 22b which are effectively low dielectric constant layers including the holes 25a and 25b, are formed in the contact holes 21a and 21b, the bit.
  • the wire W layers 22a and 22b and the SiO 2 layers 24aa and 24bb, which are low dielectric constant layers, are formed by self-alignment. As a result, the DRAM memory cell can be highly integrated.
  • FIG. 1J (a) in a plan view, SiO, which is an effective low dielectric constant layer, is formed in the overlapping region of the bit line W layers 22a and 22b and the word line W layers 26a and 26b.
  • the bit wire W layers 26a and 26b are connected only to the upper portions of the gate electrodes 15a to 15d in the height direction. As a result, for example, the height between the facing word line W layers 26a and 26b becomes smaller than the structure in which the word line W layers 26a and 26b are formed at the same height as the gate electrodes 15a and 15b. The capacity between word lines can be significantly reduced.
  • the capacity between the word wire W layers 26a and 26b is formed by forming the SiO 2 layers 25a and 25b including the pores 25a and 25b which are low dielectric constant layers between the word wire W layers 26a and 26b. Becomes smaller.
  • the P layer bases 12a and 12b have N + layers 2aa and 2bb on the opposite side, and the portions surrounding the Si columns 7a to 7b protrude. It is formed in a different shape.
  • This protruding portion is formed by self-alignment with the Si columns 7a to 7d.
  • the protruding P layer bases 12a and 12b can be formed with high accuracy and in a small area.
  • the P layer bases 12a and 12b on the side where the bit line W layers 22a and 22b are formed are formed by the mask material layers 11a and 11b.
  • the capacitance between the bit wire W layers 22a and 22b is the junction capacitance between the N + layers 2aa and 2bb, and the Si P layer bases 12a, 12b and SiO between the bit wire W layers 22a and 22b. It consists of two layers and a capacity of 13.
  • the relative permittivity of Si is 12, which is larger than that of SiO 2 of 3.9. Therefore, in order to reduce the capacitance between the bit wire W layers 22a and 22b, it is necessary to shorten the lengths of the P layer bases 12a and 12b between the bit wire W layers 22a and 22b.
  • FIG. 1K the capacitance between the bit wire W layers 22a and 22b is the junction capacitance between the N + layers 2aa and 2bb, and the Si P layer bases 12a, 12b and SiO between the bit wire W layers 22a and 22b.
  • the location of the P layer bases 12a and 12b closest to the bit line W layers 22a and 22b is a protruding portion surrounding the Si columns 7a to 7b.
  • the protruding portions of the P layer bases 12a and 12b are self-aligned with respect to the Si columns 7a to 7d.
  • the width of the P layer bases 12a and 12b surrounding the Si columns 7a to 7d can be reduced.
  • the distance between the P layer bases 12a and 12b and the bit line W layers 22a and 22b can be increased, and the bit line capacitance can be reduced.
  • the regions of the P layer bases 12a and 12b on the side where the bit wire W layers 22a and 22b are formed are defined by the mask material layers 11a and 11b.
  • the mask material layers 11a and 11b may overlap the SiN layers 10a to 10b in a plan view. If this condition is satisfied, the width of the mask material layers 11a and 11b in the XX'line direction can be made as small as possible. As a result, the Si capacity of the P layer bases 12a and 12b can be reduced.
  • the TiN layers 15a to 15d which are gate electrodes, are formed by self-alignment with respect to the Si columns 7a to 7d.
  • the word line W layers 26a and 26b are connected to a part of the outer periphery of the gate electrodes TiN layers 15a to 15d and are formed in a band shape in the XX'line direction. Then, in a plan view, the width of the W layers 26a and 26b in the YY'line direction is formed to be smaller than the width of the outer periphery of the TiN layers 15a to 15d in the YY'line direction.
  • the word wire W layers 26a and 26b are formed separately from the formation of the gate wire TiN layers 15a to 15d by using the mask material layers 27a and 27b as an etching mask.
  • the width of the word line W layers 26a and 26b in the YY'line direction can be manufactured by satisfying the condition that the word line W layers 26a and 26b and the gate line TiN layers 15a to 15d are connected. It can be as small as possible.
  • the distance in the YY'line direction between the word line W layers 26a and 26b can be increased.
  • the capacitance between the word line W layers 26a and 26b can be reduced.
  • the gate TiN layers 15a to 15d are self-aligned with respect to the Si columns 7a to 7d. This makes it possible to form a wide distance between the gate electrodes 15a and 15c and between the gate electrodes 15b and 15d in a plan view. This also makes it possible to reduce the capacitance between the word line W layers 26a and 26b.
  • FIG. (A) is a plan view
  • (b) is a cross-sectional structure diagram along the XX'line of (a)
  • (c) is a cross-sectional structure diagram along the YY'line.
  • rectangular Si columns 7A, 7B, 7C, and 7D are formed so that their long sides are parallel to the bit line W layers 22a and 22b in a plan view.
  • the gate insulating layer 14A is formed by surrounding the Si columns 7A to 7D.
  • the gate TiN layers 15A, 15B, 15C, and 15D are formed by surrounding the gate insulating layer 14A on the side surfaces of the Si columns 7A to 7D.
  • Other steps are the same as in the first embodiment.
  • the cross section of the Si columns 7a to 7d in a plan view is circular.
  • the cross section of the Si columns 7A to 7D in the present embodiment is a rectangular shape extending in the YY'line direction.
  • the channel cross section is larger than that of the SGT formed on the Si columns 7a to 7d in the first embodiment, and the effective SGT series resistance can be reduced.
  • the resistance between the bit line W layers 22a and 22b and the N + layers 2aa and 2bb can be reduced.
  • the Si columns 7a to 7d are formed, but the semiconductor columns may be made of other semiconductor materials. This also applies to the other embodiments according to the present invention.
  • the N + layer 2aa, 2bb, 29a, 29b in the first embodiment may be formed of Si containing a donor impurity or another semiconductor material layer. Further, the N + layers 2aa, 2bb, 29a and 29b may be formed from different semiconductor material layers. This also applies to the other embodiments according to the present invention.
  • the tops of the Si columns 7a to 7d and the N + layers 29a to 29d and 30a to 30d formed on the tops are, for example, the P layer after forming the P layer 4 in FIG. 1B.
  • An N + layer formed on the 4 by the epitaxial crystal growth method may be used. Further, the N + layer may be formed by another method. This also applies to the other embodiments according to the present invention.
  • the mask material layers 5a to 5d, 11a, 11b are other material layers including an organic material or an inorganic material composed of a single layer or a plurality of layers as long as they are materials suitable for the object of the present invention. You may use it.
  • the SiO 2 layers 9a and 9b and the SiN layers 10a to 10d used as the etching mask are also other material layers including an organic material or an inorganic material composed of a single layer or a plurality of layers as long as they are materials that also meet the object of the present invention. May be used. This also applies to the other embodiments according to the present invention.
  • the material of the W layers 22a and 22b in the first embodiment may be not only a metal but also a conductive material layer such as an alloy, an acceptor, or a semiconductor layer containing a large amount of donor impurities, and these may be used. It may be configured as a single layer or a combination of a plurality of layers. This also applies to the other embodiments according to the present invention.
  • TiN layers 15a to 15d were used as the gate conductor layer.
  • a material layer composed of a single layer or a plurality of layers can be used as long as it is a material that meets the object of the present invention.
  • the TiN layers 15a to 15d can be formed from a conductor layer such as a single layer or a plurality of metal layers having at least a desired work function.
  • another conductive layer such as a W layer may be formed.
  • a single layer or a plurality of metal layers may be used.
  • word line W layers 26a and 26b connected to the TiN layers 15a to 15d in the first embodiment may be laminated with another conductor layer or formed from another conductor layer. This also applies to the other embodiments according to the present invention.
  • HfO 2 layer 14 is used as the gate insulating layer, another material layer composed of a single layer or a plurality of layers may be used for each. This also applies to the other embodiments according to the present invention.
  • SiO 2 layers 24a and 24b having pores 25a and 25b were formed.
  • the upper portions of the contact holes 21a and 21b may be covered with a SiN layer by, for example, a CVD (Chemical Vapor Deposition) method to form holes 25a and 25b.
  • a CVD Chemical Vapor Deposition
  • an insulating layer made of an inorganic or organic layer having pores 25a and 25b may be formed by another method.
  • the shapes of the Si columns 7a to 7d in a plan view were circular.
  • the Si columns 7A to 7D have a rectangular shape in a plan view.
  • the shape of these Si columns in a plan view may be an ellipse or a character shape as well as a circular shape or a rectangular shape. Further, these shapes may be mixed and formed on the same P layer substrate 1a. This also applies to the other embodiments according to the present invention.
  • one memory cell is formed from one selection SGT
  • a plurality of SGTs are used in order to obtain a large drive current or to reduce the effective SGT series resistance. It may be connected in parallel. This also applies to the other embodiments according to the present invention.
  • an XY address type memory device such as DRAM, Capacitorless DRAM, RRAM, MRAM, and PCM.
  • the present invention can also be applied to other XY address type memory devices.
  • a plurality of SGTs may be used for one memory cell.
  • a plurality of RRAMs, MRAMs, and variable resistance elements for PCM may be connected to one SGT.
  • the SGT is formed on the P layer substrate 1, but an SOI (Silicon On Insulator) substrate may be used instead of the P layer substrate 1.
  • SOI Silicon On Insulator
  • another material substrate may be used as long as it serves as a substrate. This also applies to the other embodiments according to the present invention.
  • the SGT constituting the source and the drain by using the N + layers 2aa, 2bb, 29a to 29d, and 30a to 30d having the same polarity above and below the Si columns 7a to 7d has the same polarity.
  • the present invention can also be applied to a tunnel type SGT having sources and drains having different polarities. This also applies to the other embodiments according to the present invention.
  • one SGT is formed on one semiconductor column, but the present invention can also be applied to the formation of a circuit in which two or more SGTs are formed.
  • the present invention enables various embodiments and modifications without departing from the broad spirit and scope of the present invention.
  • the above-described embodiment is for explaining an embodiment of the present invention, and does not limit the scope of the present invention.
  • the above-mentioned embodiment and modification can be arbitrarily combined. Further, even if a part of the constituent requirements of the above embodiment is removed as necessary, it is within the scope of the technical idea of the present invention.
  • a memory device using a high-density and high-performance SGT can be obtained.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
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TW110138012A TWI800947B (zh) 2020-11-06 2021-10-13 使用柱狀半導體元件之記憶裝置及其製造方法
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