JPWO2022097251A5 - - Google Patents
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- Publication number
- JPWO2022097251A5 JPWO2022097251A5 JP2022534323A JP2022534323A JPWO2022097251A5 JP WO2022097251 A5 JPWO2022097251 A5 JP WO2022097251A5 JP 2022534323 A JP2022534323 A JP 2022534323A JP 2022534323 A JP2022534323 A JP 2022534323A JP WO2022097251 A5 JPWO2022097251 A5 JP WO2022097251A5
- Authority
- JP
- Japan
- Prior art keywords
- layer
- impurity region
- conductor layer
- semiconductor
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims 50
- 239000012535 impurity Substances 0.000 claims 37
- 239000004020 conductor Substances 0.000 claims 29
- 239000000463 material Substances 0.000 claims 14
- 238000004519 manufacturing process Methods 0.000 claims 10
- 239000000758 substrate Substances 0.000 claims 4
- 238000005530 etching Methods 0.000 claims 2
- 239000011159 matrix material Substances 0.000 claims 2
- 239000000956 alloy Substances 0.000 claims 1
- 229910045601 alloy Inorganic materials 0.000 claims 1
- 239000002184 metal Substances 0.000 claims 1
- 238000000034 method Methods 0.000 claims 1
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 claims 1
- 230000002093 peripheral effect Effects 0.000 claims 1
- 239000011148 porous material Substances 0.000 claims 1
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/JP2020/041461 WO2022097251A1 (ja) | 2020-11-06 | 2020-11-06 | 柱状半導体素子を用いたメモリ装置と、その製造方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JPWO2022097251A1 JPWO2022097251A1 (https=) | 2022-05-12 |
| JPWO2022097251A5 true JPWO2022097251A5 (https=) | 2022-10-17 |
| JP7251865B2 JP7251865B2 (ja) | 2023-04-04 |
Family
ID=81456983
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2022534323A Active JP7251865B2 (ja) | 2020-11-06 | 2020-11-06 | 柱状半導体素子を用いたメモリ装置と、その製造方法 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US12520479B2 (https=) |
| JP (1) | JP7251865B2 (https=) |
| TW (1) | TWI800947B (https=) |
| WO (1) | WO2022097251A1 (https=) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117199052A (zh) * | 2022-05-26 | 2023-12-08 | 长鑫存储技术有限公司 | 半导体结构及半导体存储器 |
| CN117580358A (zh) | 2022-08-04 | 2024-02-20 | 长鑫存储技术有限公司 | 一种半导体结构及其制备方法 |
| EP4503129A4 (en) * | 2022-08-19 | 2025-08-13 | Changxin Memory Tech Inc | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SAME |
Family Cites Families (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2703970B2 (ja) | 1989-01-17 | 1998-01-26 | 株式会社東芝 | Mos型半導体装置 |
| JP2748072B2 (ja) * | 1992-07-03 | 1998-05-06 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
| JPH1079482A (ja) * | 1996-08-09 | 1998-03-24 | Rai Hai | 超高密度集積回路 |
| KR100675297B1 (ko) * | 2005-12-19 | 2007-01-29 | 삼성전자주식회사 | 캐패시터가 없는 동적 메모리 셀을 구비한 반도체 메모리장치 및 이 장치의 배치 방법 |
| WO2009095996A1 (ja) | 2008-01-29 | 2009-08-06 | Unisantis Electronics (Japan) Ltd. | 半導体記憶装置 |
| WO2009096001A1 (ja) * | 2008-01-29 | 2009-08-06 | Unisantis Electronics (Japan) Ltd. | 半導体記憶装置およびメモリ混載半導体装置、並びにそれらの製造方法 |
| US8212298B2 (en) * | 2008-01-29 | 2012-07-03 | Unisantis Electronics Singapore Pte Ltd. | Semiconductor storage device and methods of producing it |
| SG166752A1 (en) * | 2009-05-22 | 2010-12-29 | Unisantis Electronics Jp Ltd | Semiconductor memory device and production method therefor |
| US9559216B2 (en) * | 2011-06-06 | 2017-01-31 | Micron Technology, Inc. | Semiconductor memory device and method for biasing same |
| WO2015059789A1 (ja) * | 2013-10-23 | 2015-04-30 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | 半導体装置 |
| JP2015149413A (ja) * | 2014-02-06 | 2015-08-20 | 株式会社東芝 | 半導体記憶装置及びその製造方法 |
| US10014316B2 (en) * | 2016-10-18 | 2018-07-03 | Sandisk Technologies Llc | Three-dimensional memory device with leakage reducing support pillar structures and method of making thereof |
| US10453798B2 (en) * | 2017-09-27 | 2019-10-22 | Sandisk Technologies Llc | Three-dimensional memory device with gated contact via structures and method of making thereof |
| US10366983B2 (en) * | 2017-12-29 | 2019-07-30 | Micron Technology, Inc. | Semiconductor devices including control logic structures, electronic systems, and related methods |
| US20190312050A1 (en) * | 2018-04-10 | 2019-10-10 | Macronix International Co., Ltd. | String select line gate oxide method for 3d vertical channel nand memory |
| US10763273B2 (en) * | 2018-08-23 | 2020-09-01 | Macronix International Co., Ltd. | Vertical GAA flash memory including two-transistor memory cells |
| US11018151B2 (en) * | 2018-09-26 | 2021-05-25 | Sandisk Technologies Llc | Three-dimensional flat NAND memory device including wavy word lines and method of making the same |
| JP2020150234A (ja) * | 2019-03-15 | 2020-09-17 | キオクシア株式会社 | 半導体記憶装置 |
| US10854629B2 (en) * | 2019-03-28 | 2020-12-01 | Sandisk Technologies Llc | Three-dimensional memory device containing asymmetric, different size support pillars and method for making the same |
-
2020
- 2020-11-06 WO PCT/JP2020/041461 patent/WO2022097251A1/ja not_active Ceased
- 2020-11-06 JP JP2022534323A patent/JP7251865B2/ja active Active
-
2021
- 2021-10-13 TW TW110138012A patent/TWI800947B/zh active
-
2023
- 2023-05-03 US US18/311,701 patent/US12520479B2/en active Active
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