JP7206465B2 - イオン注入ステップ中のドナー基板の縁部におけるゾーンのマスキング - Google Patents
イオン注入ステップ中のドナー基板の縁部におけるゾーンのマスキング Download PDFInfo
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- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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- H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
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Description
線81は、本発明の第1の実施例に係るドナー基板1内の注入プロファイルを表す。ヘリウムイオンは、ドナー基板1の面取りゾーン7に対応するドナー基板1の縁部5のゾーンをマスキングするために、図2dに示すようなマスク43を使用して、注入量c1(95keV及び2.5e16at/cm2)で注入される。
本発明に係る第2の実施例によれば、マスク43は、選択されることがあり、したがって、ドナー基板1の縁部5のゾーンが、ドナー基板1の面取りゾーン7より広く、ヘリウムイオンの注入量が、中央ゾーン9の注入量よりも少ない。従って、r2<r1である。
図3a及び3bを参照して説明されたような本発明の別の実施例によれば、第2の注入ステップは、第1の注入作業後にドナー基板に実行され、対応する注入プロファイルは、図3cの一点鎖線85で示される。
Claims (16)
- ドナー基板(1)の内側の所定の分離ゾーン(19)を形成するためのプロセスにおいて、
前記ドナー基板(1)の縁部(5)のゾーンの注入量(25)が前記ドナー基板(1)の中央ゾーン(9)の注入量(27)より少ないように実行される第1の原子及び/又はイオン注入ステップ(17)を含み、
前記ドナー基板(1)の前記縁部(5)の前記ゾーンが、前記ドナー基板(1)の前記縁部の面取りゾーン(7)に限定され、
前記第1の注入ステップより少ない注入量で前記ドナー基板(1)の面全体の上に実行される、第2の原子及び/又はイオン注入ステップ(17)を含む、ことを特徴とするプロセス。 - 前記第1の注入ステップ(17)が、前記注入(17)が前記ドナー基板(1)の前記中央ゾーン(9)に限定されるように実行される、請求項1に記載のプロセス。
- 前記基板(1)の前記縁部(5)の前記ゾーンの幅が、1mm~5mmで構成される、請求項1又は2に記載のプロセス。
- 前記第1の注入ステップの前記注入(17)が、マスク(43)を使用して、前記ドナー基板(1)の前記縁部(5)の前記ゾーンの上又は上方で実行される、請求項1~3のいずれか1項に記載のプロセス。
- 前記第1の注入ステップの前記注入(17)が、前記ドナー基板(1)の前記縁部(5)の前記ゾーンに向けた注入量が前記ドナー基板(1)の前記中央ゾーン(9)の注入量より少ないように、前記ドナー基板をイオンビームで走査することによって実行される、請求項1~4のいずれか1項に記載のプロセス。
- 前記第1の注入ステップの前記注入(17)が、ヘリウムイオン(He)の注入、又は、ヘリウムイオン及び水素イオン(He-H)の同時注入、を含む、ことを特徴とする請求項1~5のいずれか1項に記載のプロセス。
- 前記第1の注入ステップ(17)が、ヘリウムイオンの注入であり、前記第2の注入ステップ(17)が、水素イオンの注入である、請求項1に記載のプロセス。
- 前記ドナー基板の前記縁部(5)の前記ゾーンの前記注入量(25)が、1e16at/cm2より少ない、請求項1~7のいずれか1項に記載のプロセス。
- キャリア基板上に層を移転するプロセスのためのドナー基板であって、所定の分離ゾーン(19)を含み、前記ドナー基板の前記縁部(5)のゾーンの前記注入量(25)が、請求項1~8のいずれか1項に記載の前記プロセスによって生産される、前記ドナー基板の中央ゾーン(9)の注入量(27)より少ない、ドナー基板。
- キャリア基板上にドナー基板の層を移転するプロセスであって、
(a)請求項9に係るドナー基板(1)をキャリア基板(11)に取着するステップと、
(b)前記ドナー基板の残部(23)を前記キャリア基板(11)に移転された前記層(21)から脱離するために、所定の分離ゾーン(19)の部位で脱離作業を実行するステップと、を含む、プロセス。 - ステップ(b)が、熱アニールステップを含む、請求項10に記載のプロセス。
- 注入領域を請求項9に記載のドナー基板(1)、の前記縁部(5)のゾーンに限定するためのデバイスにおいて、前記デバイスが、前記ドナー基板(1)の前記縁部(5)のゾーンに向けた前記注入量(25)が前記ドナー基板(1)の中央ゾーン(9)の前記注入量(27)より少ないように、前記注入(17)を実行するのに適した手段を含む、ことを特徴とするデバイス。
- 前記注入領域を前記ドナー基板(1)の前記中央ゾーン(9)に限定するための前記手段が、マスク(43)を含むことがある、請求項12に記載のデバイス。
- 前記マスク(43)が、前記ドナー基板(1)の上又はその上方に位置決めされたリングである、請求項13に記載のデバイス。
- 前記マスク(43)が、ドナー基板(1)の前記縁部(5)の前記ゾーンを、1mm~5mmで構成される幅全体について、マスキングするように構成される、ことを特徴とする請求項13に記載のデバイス。
- 請求項12~15のいずれか1項に記載のデバイスを含む、ドナー基板(1)にイオンを注入するためのイオン注入装置。
Applications Claiming Priority (3)
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FR1751296 | 2017-02-17 | ||
FR1751296A FR3063176A1 (fr) | 2017-02-17 | 2017-02-17 | Masquage d'une zone au bord d'un substrat donneur lors d'une etape d'implantation ionique |
PCT/EP2018/053755 WO2018149906A1 (en) | 2017-02-17 | 2018-02-15 | Masking a zone at the edge of a donor substrate during an ion implantation step |
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JP2020507916A JP2020507916A (ja) | 2020-03-12 |
JP7206465B2 true JP7206465B2 (ja) | 2023-01-18 |
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EP (1) | EP3583620A1 (ja) |
JP (1) | JP7206465B2 (ja) |
KR (1) | KR102537290B1 (ja) |
CN (1) | CN110291626B (ja) |
FR (1) | FR3063176A1 (ja) |
TW (1) | TWI748057B (ja) |
WO (1) | WO2018149906A1 (ja) |
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FR3091620B1 (fr) | 2019-01-07 | 2021-01-29 | Commissariat Energie Atomique | Procédé de transfert de couche avec réduction localisée d’une capacité à initier une fracture |
EP3965186A4 (en) | 2019-09-24 | 2022-06-22 | LG Energy Solution, Ltd. | POSITIVE ELECTRODE FOR SECONDARY LITHIUM-SULFUR BATTERY WITH PATTERN, ASSOCIATED MANUFACTURING METHOD, AND SECONDARY LITHIUM-SULFUR BATTERY WITH SAID POSITIVE ELECTRODE |
FR3108440A1 (fr) | 2020-03-23 | 2021-09-24 | Soitec | Procédé de préparation d’une couche mince |
FR3121281B1 (fr) * | 2021-03-23 | 2023-11-24 | Soitec Silicon On Insulator | Procede de fabrication d’une structure composite comprenant une couche mince en semi-conducteur monocristallin sur un substrat support |
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JP2005079393A (ja) | 2003-09-01 | 2005-03-24 | Sumitomo Mitsubishi Silicon Corp | スマートカット法におけるイオン注入方法およびスマートカット法によるsoiウェーハ |
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JP2004535664A (ja) | 2001-04-13 | 2004-11-25 | コミサリヤ・ア・レネルジ・アトミク | 剥離可能な基板または剥離可能な構造、およびそれらの製造方法 |
JP2005079393A (ja) | 2003-09-01 | 2005-03-24 | Sumitomo Mitsubishi Silicon Corp | スマートカット法におけるイオン注入方法およびスマートカット法によるsoiウェーハ |
JP2009500839A (ja) | 2005-07-08 | 2009-01-08 | エス.オー.アイ.テック シリコン オン インシュレータ テクノロジーズ | 被膜の生成方法 |
JP2016072267A (ja) | 2014-09-26 | 2016-05-09 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法 |
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CN110291626B (zh) | 2023-05-05 |
CN110291626A (zh) | 2019-09-27 |
KR20190117573A (ko) | 2019-10-16 |
FR3063176A1 (fr) | 2018-08-24 |
WO2018149906A1 (en) | 2018-08-23 |
US11189519B2 (en) | 2021-11-30 |
TWI748057B (zh) | 2021-12-01 |
EP3583620A1 (en) | 2019-12-25 |
KR102537290B1 (ko) | 2023-05-30 |
JP2020507916A (ja) | 2020-03-12 |
US20210143052A1 (en) | 2021-05-13 |
TW201841302A (zh) | 2018-11-16 |
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