JP7189672B2 - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

Info

Publication number
JP7189672B2
JP7189672B2 JP2018079689A JP2018079689A JP7189672B2 JP 7189672 B2 JP7189672 B2 JP 7189672B2 JP 2018079689 A JP2018079689 A JP 2018079689A JP 2018079689 A JP2018079689 A JP 2018079689A JP 7189672 B2 JP7189672 B2 JP 7189672B2
Authority
JP
Japan
Prior art keywords
pads
semiconductor chip
bonding
circuit forming
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2018079689A
Other languages
English (en)
Japanese (ja)
Other versions
JP2019192667A5 (https=
JP2019192667A (ja
Inventor
聖二 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2018079689A priority Critical patent/JP7189672B2/ja
Priority to US16/380,166 priority patent/US10784177B2/en
Publication of JP2019192667A publication Critical patent/JP2019192667A/ja
Publication of JP2019192667A5 publication Critical patent/JP2019192667A5/ja
Application granted granted Critical
Publication of JP7189672B2 publication Critical patent/JP7189672B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/012—Manufacture or treatment of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/016—Manufacture or treatment using moulds
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07202—Connecting or disconnecting of bump connectors using auxiliary members
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07236—Soldering or alloying
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H10W72/07252—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting changes in structures or sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H10W72/07253—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting changes in shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221—Structures or relative sizes
    • H10W72/227—Multiple bumps having different sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/231—Shapes
    • H10W72/237—Multiple bump connectors having different shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/926—Multiple bond pads having different sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/014—Manufacture or treatment using batch processing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H10W80/701—Direct bonding of chips, wafers or substrates characterised by the pads after the direct bonding
    • H10W80/721—Direct bonding of chips, wafers or substrates characterised by the pads after the direct bonding having structure or size changed during the connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/791—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Wire Bonding (AREA)
JP2018079689A 2018-04-18 2018-04-18 半導体装置及びその製造方法 Active JP7189672B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2018079689A JP7189672B2 (ja) 2018-04-18 2018-04-18 半導体装置及びその製造方法
US16/380,166 US10784177B2 (en) 2018-04-18 2019-04-10 Semiconductor device with encapsulating resin

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2018079689A JP7189672B2 (ja) 2018-04-18 2018-04-18 半導体装置及びその製造方法

Publications (3)

Publication Number Publication Date
JP2019192667A JP2019192667A (ja) 2019-10-31
JP2019192667A5 JP2019192667A5 (https=) 2021-03-25
JP7189672B2 true JP7189672B2 (ja) 2022-12-14

Family

ID=68238233

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2018079689A Active JP7189672B2 (ja) 2018-04-18 2018-04-18 半導体装置及びその製造方法

Country Status (2)

Country Link
US (1) US10784177B2 (https=)
JP (1) JP7189672B2 (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11024608B2 (en) 2017-03-28 2021-06-01 X Display Company Technology Limited Structures and methods for electrical connection of micro-devices and substrates
US11101417B2 (en) * 2019-08-06 2021-08-24 X Display Company Technology Limited Structures and methods for electrically connecting printed components
US11316086B2 (en) 2020-07-10 2022-04-26 X Display Company Technology Limited Printed structures with electrical contact having reflowable polymer core

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003243818A (ja) 2002-02-15 2003-08-29 Denso Corp 半導体電子部品の実装方法
JP2010161425A (ja) 2010-04-26 2010-07-22 Panasonic Corp モジュールの製造方法と、その製造設備

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS538566A (en) * 1976-07-12 1978-01-26 Citizen Watch Co Ltd Mounting structure of semiconductor ic circuit
EP0248566A3 (en) * 1986-05-30 1990-01-31 AT&T Corp. Process for controlling solder joint geometry when surface mounting a leadless integrated circuit package on a substrate
KR100192766B1 (ko) * 1995-07-05 1999-06-15 황인길 솔더볼을 입출력 단자로 사용하는 볼그리드 어레이 반도체 패키지의 솔더볼 평탄화 방법 및 그 기판구조
TW434856B (en) * 2000-05-15 2001-05-16 Siliconware Precision Industries Co Ltd Manufacturing method for high coplanarity solder ball array of ball grid array integrated circuit package
JP3891838B2 (ja) * 2001-12-26 2007-03-14 株式会社ルネサステクノロジ 半導体装置およびその製造方法
JP2006196728A (ja) * 2005-01-14 2006-07-27 Seiko Epson Corp 電子部品、電気光学装置、及び電子機器
JP2009049499A (ja) * 2007-08-14 2009-03-05 Fujifilm Corp 半導体チップの実装方法及び半導体装置
JP2009117767A (ja) * 2007-11-09 2009-05-28 Shinko Electric Ind Co Ltd 半導体装置の製造方法及びそれにより製造した半導体装置
JP5375708B2 (ja) * 2010-03-29 2013-12-25 パナソニック株式会社 半導体装置の製造方法
JP2011243683A (ja) * 2010-05-17 2011-12-01 Fujitsu Ltd 電子部品の実装方法、電子部品の製造方法および電子部品、電子部品の製造装置
KR101712043B1 (ko) * 2010-10-14 2017-03-03 삼성전자주식회사 적층 반도체 패키지, 상기 적층 반도체 패키지를 포함하는 반도체 장치 및 상기 적층 반도체 패키지의 제조 방법
US8367475B2 (en) * 2011-03-25 2013-02-05 Broadcom Corporation Chip scale package assembly in reconstitution panel process format
KR101607790B1 (ko) * 2012-01-17 2016-03-30 파나소닉 아이피 매니지먼트 가부시키가이샤 반도체 장치 제조 방법 및 반도체 장치
US9343419B2 (en) * 2012-12-14 2016-05-17 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structures for semiconductor package
US9070644B2 (en) * 2013-03-15 2015-06-30 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging mechanisms for dies with different sizes of connectors
US8970051B2 (en) * 2013-06-28 2015-03-03 Intel Corporation Solution to deal with die warpage during 3D die-to-die stacking
JP6303373B2 (ja) 2013-10-02 2018-04-04 住友ベークライト株式会社 圧縮成形用モールドアンダーフィル材料、半導体パッケージ、構造体および半導体パッケージの製造方法
KR20160004065A (ko) * 2014-07-02 2016-01-12 삼성전자주식회사 반도체 패키지 및 이의 제조방법
JP2016063013A (ja) * 2014-09-17 2016-04-25 株式会社東芝 半導体装置
CN106206633A (zh) * 2015-05-28 2016-12-07 精材科技股份有限公司 影像感测装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003243818A (ja) 2002-02-15 2003-08-29 Denso Corp 半導体電子部品の実装方法
JP2010161425A (ja) 2010-04-26 2010-07-22 Panasonic Corp モジュールの製造方法と、その製造設備

Also Published As

Publication number Publication date
US20190326189A1 (en) 2019-10-24
US10784177B2 (en) 2020-09-22
JP2019192667A (ja) 2019-10-31

Similar Documents

Publication Publication Date Title
KR100652242B1 (ko) 플립칩형 반도체장치, 이의 제조를 위한 제조방법 및 이런 플립칩형 반도체장치를 사용하여 전자제품을 제조하기 위한 제조방법
CN100438025C (zh) 芯片层叠型半导体装置及其制造方法
CN103367176B (zh) 半导体器件的制造方法
CN100407422C (zh) 半导体装置及其制造方法
US20140295620A1 (en) Method of manufacturing semiconductor device having plural semiconductor chips stacked one another
TW200414471A (en) Semiconductor device and manufacturing method for the same
JP2012069903A (ja) 半導体装置及びその製造方法
JP7189672B2 (ja) 半導体装置及びその製造方法
WO2006035548A1 (ja) 配線基板および半導体装置
JP2012015142A (ja) 半導体パッケージおよびその製造方法
JP2013021058A (ja) 半導体装置の製造方法
CN1950939B (zh) 半导体装置
US8179686B2 (en) Mounted structural body and method of manufacturing the same
KR20180117238A (ko) 반도체 패키지 및 그 제조 방법
JP4324773B2 (ja) 半導体装置の製造方法
WO2018150809A1 (ja) 半導体装置、チップ状半導体素子、半導体装置を備えた電子機器、及び、半導体装置の製造方法
JP2004363289A (ja) 半導体装置の製造方法
KR20120032764A (ko) 플립칩 패키지용 기판 및 이를 이용한 플립칩 패키지의 제조 방법
JPH1098077A (ja) 半導体装置の製造方法
JP4561969B2 (ja) 半導体装置
TW201306197A (zh) 以金屬柱銲接為晶片連接之半導體封裝構造
JP4591715B2 (ja) 半導体装置の製造方法
TWI429041B (zh) 非陣列凸塊之覆晶接合方法與構造
JP2007294560A (ja) 半導体装置およびその製造方法
JPH11274235A (ja) 半導体装置およびその製造方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20210205

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20210205

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20211108

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20211221

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20220214

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20220712

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20220913

C60 Trial request (containing other claim documents, opposition documents)

Free format text: JAPANESE INTERMEDIATE CODE: C60

Effective date: 20220913

A911 Transfer to examiner for re-examination before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20220926

C21 Notice of transfer of a case for reconsideration by examiners before appeal proceedings

Free format text: JAPANESE INTERMEDIATE CODE: C21

Effective date: 20221004

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20221108

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20221202

R150 Certificate of patent or registration of utility model

Ref document number: 7189672

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150