JP7111457B2 - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

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Publication number
JP7111457B2
JP7111457B2 JP2017208586A JP2017208586A JP7111457B2 JP 7111457 B2 JP7111457 B2 JP 7111457B2 JP 2017208586 A JP2017208586 A JP 2017208586A JP 2017208586 A JP2017208586 A JP 2017208586A JP 7111457 B2 JP7111457 B2 JP 7111457B2
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layer
opening
wiring
conductive paste
barrier layer
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Japanese (ja)
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JP2019083234A (ja
JP2019083234A5 (https=
Inventor
圭吾 佐藤
浩志 種子田
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Priority to JP2017208586A priority Critical patent/JP7111457B2/ja
Priority to US16/138,252 priority patent/US10593621B2/en
Publication of JP2019083234A publication Critical patent/JP2019083234A/ja
Publication of JP2019083234A5 publication Critical patent/JP2019083234A5/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44—Conductive materials thereof
    • H10W20/4403—Conductive materials thereof based on metals, e.g. alloys, metal silicides
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    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44—Conductive materials thereof
    • H10W20/4473—Conductive organic materials, e.g. conductive adhesives or conductive inks
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/098—Applying pastes or inks, e.g. screen printing
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/40—Encapsulations, e.g. protective coatings characterised by their materials
    • H10W74/47—Encapsulations, e.g. protective coatings characterised by their materials comprising organic materials, e.g. plastics or resins
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
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    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07232—Compression bonding, e.g. thermocompression bonding
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    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07237—Techniques using a polymer adhesive, e.g. an adhesive based on silicone or epoxy
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H10W72/07252—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting changes in structures or sizes
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    • H10W72/073—Connecting or disconnecting of die-attach connectors
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    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07331—Connecting techniques
    • H10W72/07332—Compression bonding, e.g. thermocompression bonding
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    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07331—Connecting techniques
    • H10W72/07337—Connecting techniques using a polymer adhesive, e.g. an adhesive based on silicone or epoxy
    • H10W72/07338—Connecting techniques using a polymer adhesive, e.g. an adhesive based on silicone or epoxy hardening the adhesive by curing, e.g. thermosetting
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221—Structures or relative sizes
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221—Structures or relative sizes
    • H10W72/222—Multilayered bumps, e.g. a coating on top and side surfaces of a bump core
    • H10W72/223—Multilayered bumps, e.g. a coating on top and side surfaces of a bump core characterised by the structure of the outermost layers, e.g. multilayered coatings
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    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221—Structures or relative sizes
    • H10W72/225—Bumps having a filler embedded in a matrix
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/231—Shapes
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    • H10W72/00—Interconnections or connectors in packages
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    • H10W72/241—Dispositions, e.g. layouts
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    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/245—Dispositions, e.g. layouts of outermost layers of multilayered bumps, e.g. bump coating being only on a part of a bump core
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    • H10W72/00—Interconnections or connectors in packages
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    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
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    • H10W72/00—Interconnections or connectors in packages
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    • H10W72/251—Materials
    • H10W72/253—Materials not comprising solid metals or solid metalloids, e.g. polymers or ceramics
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    • H10W72/255—Materials of outermost layers of multilayered bumps, e.g. material of a coating
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    • H10W72/351—Materials of die-attach connectors
    • H10W72/353—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics
    • H10W72/354—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics comprising polymers
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    • H10W74/00—Encapsulations, e.g. protective coatings
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    • H10W74/012—Manufacture or treatment of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills
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    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
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    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
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    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Wire Bonding (AREA)
JP2017208586A 2017-10-27 2017-10-27 半導体装置及びその製造方法 Active JP7111457B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2017208586A JP7111457B2 (ja) 2017-10-27 2017-10-27 半導体装置及びその製造方法
US16/138,252 US10593621B2 (en) 2017-10-27 2018-09-21 Semiconductor device with barrier layer

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Application Number Priority Date Filing Date Title
JP2017208586A JP7111457B2 (ja) 2017-10-27 2017-10-27 半導体装置及びその製造方法

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JP2019083234A JP2019083234A (ja) 2019-05-30
JP2019083234A5 JP2019083234A5 (https=) 2020-09-10
JP7111457B2 true JP7111457B2 (ja) 2022-08-02

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Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018172098A1 (en) * 2017-03-23 2018-09-27 Imec Vzw Methods for forming metal electrodes concurrently on silicon regions of opposite polarity
CN111146170A (zh) * 2019-12-30 2020-05-12 颀中科技（苏州）有限公司 封装结构及其成型方法
JP7548743B2 (ja) * 2020-07-21 2024-09-10 新光電気工業株式会社 半導体装置
JP7516230B2 (ja) * 2020-12-03 2024-07-16 新光電気工業株式会社 半導体装置及び半導体装置の製造方法
CN115881655A (zh) * 2023-02-16 2023-03-31 成都频岢微电子有限公司 一种射频前端模组封装工艺结构

Citations (4)

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Publication number Priority date Publication date Assignee Title
JP2004288959A (ja) 2003-03-24 2004-10-14 Matsushita Electric Ind Co Ltd 電子回路装置およびその製造方法
JP2014143305A (ja) 2013-01-24 2014-08-07 Nippon Telegr & Teleph Corp <Ntt> 半導体装置の実装構造および半導体装置の製造方法
JP2016042536A (ja) 2014-08-18 2016-03-31 富士通株式会社 半導体装置及び半導体装置の製造方法
WO2016139794A1 (ja) 2015-03-05 2016-09-09 オリンパス株式会社 半導体装置および半導体装置の製造方法

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JPH07226421A (ja) * 1994-02-09 1995-08-22 Toshiba Corp Ｉｃ素子実装回路装置およびｉｃ素子の実装方法
JP3876953B2 (ja) * 1998-03-27 2007-02-07 セイコーエプソン株式会社 半導体装置及びその製造方法、回路基板並びに電子機器
WO2010003732A2 (de) * 2008-07-09 2010-01-14 Robert Bosch Gmbh Magnetischer positionssensor
US8884159B2 (en) * 2011-09-14 2014-11-11 International Business Machines Corporation Photovoltaic devices with metal semiconductor alloy metallization
JP6555907B2 (ja) * 2015-03-16 2019-08-07 アルパッド株式会社 半導体発光装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004288959A (ja) 2003-03-24 2004-10-14 Matsushita Electric Ind Co Ltd 電子回路装置およびその製造方法
JP2014143305A (ja) 2013-01-24 2014-08-07 Nippon Telegr & Teleph Corp <Ntt> 半導体装置の実装構造および半導体装置の製造方法
JP2016042536A (ja) 2014-08-18 2016-03-31 富士通株式会社 半導体装置及び半導体装置の製造方法
WO2016139794A1 (ja) 2015-03-05 2016-09-09 オリンパス株式会社 半導体装置および半導体装置の製造方法

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JP2019083234A (ja) 2019-05-30
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