JP6985431B2 - 抵抗変化型記憶装置 - Google Patents
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- 230000008859 change Effects 0.000 title claims description 36
- 239000010410 layer Substances 0.000 claims description 56
- 239000004065 semiconductor Substances 0.000 claims description 38
- 239000000758 substrate Substances 0.000 claims description 28
- 238000004519 manufacturing process Methods 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 15
- 229920005591 polysilicon Polymers 0.000 claims description 15
- 230000002093 peripheral effect Effects 0.000 claims description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 12
- 239000011229 interlayer Substances 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 5
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- 238000005530 etching Methods 0.000 description 12
- 238000010586 diagram Methods 0.000 description 6
- 230000006870 function Effects 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000000295 complement effect Effects 0.000 description 4
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 238000013528 artificial neural network Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
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- 230000000149 penetrating effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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Description
110:メモリセルアレイ
120:行選択/駆動回路
130:列選択回路
140:センス回路
150:書込み/読出しバイアス回
160:制御回路
170:内部バス
200:ピラー
210:ビット線
220:メモリセル
222:ゲート絶縁膜
224:半導体層
226:可変抵抗素子
300:シリコン基板
310:メモリセルアレイ
320:周辺回路
Claims (15)
- 基板の主面に対して垂直方向に延在し、第1の導電型の半導体材料から構成される複数の垂直部材と、
前記基板の主面に対して水平方向に延在し、導電性材料から構成される複数の水平部材と、
前記複数の垂直部材と前記複数の水平部材とのそれぞれの交差部に形成されたメモリセルとを含み、
前記メモリセルは、前記垂直部材の外周に形成されたゲート絶縁膜と、前記ゲート絶縁膜の外周に形成された第2の導電型の半導体材料から構成される半導体膜と、前記半導体膜の外周に形成され可変抵抗膜とを含み、前記可変抵抗膜は、内側の電極領域と外側の電極領域との間に形成されたスイッチング領域を含み、前記外側の電極領域の対向する第1および第2の電極領域が水平方向において隣接する一対の水平部材にそれぞれ電気的に接続され、前記垂直部材に電圧が印加されたとき、前記半導体膜にチャンネルが形成され、前記一対の水平部材の一方の水平部材から他方の水平部材との間に前記第1および第2の電極領域を含む電流経路が形成され、
抵抗変化型記憶装置はさらに、行アドレス信号に基づき垂直部材を選択する行選択手段と、列アドレス信号に基づき水平部材を選択する列選択手段と、前記行選択手段および前記列選択手段により選択されたメモリセルの読出しまたは書込みを制御する制御手段とを有し、前記制御手段は、選択メモリセルに接続された前記一対の水平部材の一方に読出し電圧または書込み電圧を印加し、他方に基準電圧またはGNDを印加し、前記行選択手段および前記列選択手段によりメモリセルの選択が可能である、抵抗変化型記憶装置。 - 前記メモリセルは、前記一対の水平部材との間に1つのアクセス用トランジスタと当該アクセス用トランジスタの両側に2つの可変抵抗とを含む、請求項1に記載の抵抗変化型記憶装置。
- 前記複数の垂直部材、前記複数の水平部材および前記半導体膜は、ポリシリコン材料から構成される、請求項1または2に記載の抵抗変化型記憶装置。
- 前記複数の垂直部材は2次元的に配置され、前記複数の水平部材は、垂直方向に配置され、複数のメモリセルが3次元に配置される、請求項1ないし3いずれか1つに記載の抵抗変化型記憶装置。
- 前記複数の垂直部材が対応するワード線に接続され、前記複数の水平部材が対応するビット線に接続され、
前記行選択手段がワード線を選択し、前記列選択手段がビット線を選択することでメモリセルが選択される、請求項1に記載の抵抗変化型記憶装置。 - 行方向の奇数番目の垂直部材の一方の端部が、水平方向に延在する第1のワード線に電気的に接続され、行方向の偶数番目の垂直部材の前記一方の端部と対向する他方の端部が、水平方向に延在する第2のワード線に電気的に接続される、請求項5に記載の抵抗変化型記憶装置。
- 行方向のメモリセルがビット線を共有し、同一行の複数のメモリセルが第1組のメモリセルと第2組のメモリセルとを含み、第1組のメモリセルと第2組のメモリセルが交互に位置し、
第1組のメモリセルが第1のワード線に電気的に接続され、第2組のメモリセルが第2のワード線に接続され、
第1組のメモリセルが選択されたとき第2組のメモリセルが非選択であり、第2組のメモリセルが選択されたとき第1組のメモリセルが非選択である、請求項5に記載の抵抗変化型記憶装置。 - 前記制御手段は、選択された第1組のメモリセルまたは選択された第2組のメモリセルに接続された選択ビット線対に読出しまたは書込みのためのバイアス電圧を印加する、請求項7に記載の抵抗変化型記憶装置。
- 抵抗変化型記憶装置はさらに、基板と、当該基板の表面または基板内に形成された周辺回路とを含み、
前記周辺回路上には、前記複数の垂直部材および前記複数の水平部材が形成され、
前記複数の垂直部材および前記複数の水平部材は、多層配線構造を介して前記周辺回路に電気的に接続される、請求項1に記載の抵抗変化型記憶装置。 - 前記多層配線構造は、複数の導電層と複数の絶縁層との積層を含み、選択された導電層が選択された垂直部材または水平部材に接続される、請求項9に記載の抵抗変化型記憶装置。
- 前記周辺回路は、行アドレス信号に基づき垂直部材を選択する行選択回路および列アドレス信号に基づき水平部材を選択する列選択回路を含む、請求項9に記載の抵抗変化型記憶装置。
- 請求項1ないし11いずれか1つに記載の抵抗変化型記憶装置の製造方法であって、
前記複数の水平部材と前記複数の水平部材のそれぞれを電気的に絶縁する層間絶縁膜とが形成された基板を用意し、
前記水平部材および前記層間絶縁膜を貫通する開口を形成し、前記開口の側壁の一方の側が前記一対の水平部材の一方を露出させ、前記開口の側壁の前記一方の側と対向する他方の側が前記一対の水平部材の他方を露出させ、
前記開口の側壁の全周に前記可変抵抗膜を形成し、前記可変抵抗膜を前記一対の水平部材に接続させ、
前記可変抵抗膜の開口の側壁の全周に前記半導体膜を形成し、
前記半導体膜の開口内に前記垂直部材を形成する工程を含む、製造方法。 - 前記基板は、シリコン基板と絶縁層を含み、前記シリコン基板表面には、行アドレス信号に基づき前記垂直部材を選択する行選択手段、列アドレス信号に基づき前記水平部材を選択する列選択手段および前記行選択手段および前記列選択手段により選択されたメモリセルの読出しまたは書込みを制御する制御手段の周辺回路が形成され、前記絶縁層上に前記複数の水平部材、前記垂直部材および前記可変抵抗膜を含むメモリセルアレイが形成される、請求項12に記載の製造方法。
- 前記絶縁層と前記メモリセルアレイとの間に導電層が形成され、前記導電層は、前記メモリセルアレイの電源ラインを提供する、請求項13に記載の製造方法。
- 前記電源ラインは、前記メモリセルアレイの共通のソース線である、請求項14に記載の製造方法。
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