JP6910907B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP6910907B2 JP6910907B2 JP2017184123A JP2017184123A JP6910907B2 JP 6910907 B2 JP6910907 B2 JP 6910907B2 JP 2017184123 A JP2017184123 A JP 2017184123A JP 2017184123 A JP2017184123 A JP 2017184123A JP 6910907 B2 JP6910907 B2 JP 6910907B2
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Description
まず、抵抗性フィールドプレート部を有する半導体装置の一般的な構造例について簡単に説明する。図28は抵抗性フィールドプレート部を有する半導体装置を構成する半導体チップの平面図である。
<半導体装置の構成例>
図1は本実施の形態1の半導体装置を構成する半導体チップの平面図である。
次に、本実施の形態1の半導体装置の製造方法の一例を図12〜図19を参照して説明する。図12〜図19は図1の半導体装置の製造工程中の基板の素子領域(左)と周辺領域(右)の要部断面図である。
図20は実施の形態1の変形例1の半導体装置における図4のII−II線に相当する箇所の断面図、図21は図20の破線で囲んだ領域の拡大断面図である。
図22は実施の形態1の変形例2の半導体装置を構成するチップの平面図、図23は図22のIII−III線の断面図、図24はチップの周辺領域の要部平面図である。なお、図22のII−II線の断面図は図5と同じである。
図25は実施の形態1の変形例3の半導体装置における図4のII−II線に相当する箇所の断面図、図26は図25のチップの要部拡大断面図である。
図27は実施の形態1の変形例4の半導体装置における図4のII−II線に相当する箇所の断面図である。
SB 半導体基板
DR 素子領域
PR 周辺領域
EE エミッタ電極
GEW ゲート電極配線
GE ゲート電極部
GW ゲート配線部
FCW 内側周回配線
JW 接続配線部
SCW 外側周回配線
BCF バリア導体膜
MCF 主導体膜
Tr 絶縁ゲートバイポーラトランジスタ
CR コレクタ領域
ER エミッタ領域
Ct 接続溝
DRR ドリフト領域
CHR チャネル形成領域
TG トレンチゲート電極
Gt ゲート溝
Gi ゲート絶縁膜
CE コレクタ電極
FPR 半導体領域
RSR リサーフ領域
CSR チャネルストッパ領域
FiF 厚い絶縁膜
TiF 薄い絶縁膜
FP 抵抗性フィールドプレート部
FCP,SCP,TCP 導体パターン
FCP1 主要部分
FCP2 引出部分
SCP1 主要部分
SCP2 引出部分
JH1〜JH4 接続孔
JHC1,JHC2 共有の接続孔
PF 表面保護膜
MB 封止体
Claims (9)
- 半導体チップを構成する半導体基板と、
前記半導体基板の第1面に配置された素子領域と、
前記素子領域に配置された素子と、
平面視で前記素子領域を取り囲むように前記第1面に設けられた第1導電型の第1半導体領域と、
平面視で前記第1半導体領域を取り囲むように前記第1面上に設けられた第1絶縁膜と、
平面視で前記第1絶縁膜より内側および外側の前記第1面上に設けられ、かつ、断面視で前記第1絶縁膜より薄い第2絶縁膜と、
平面視で前記素子領域を取り囲むように前記第1絶縁膜および前記第2絶縁膜上に設けられた導体プレート部と、
断面視で前記第1絶縁膜、前記第2絶縁膜および前記導体プレート部を覆うように前記第1面上に設けられた第3絶縁膜と、
平面視で前記導体プレート部より内側に前記素子領域を取り囲むように前記第3絶縁膜上に設けられ、かつ、前記素子の第1電極および前記第1半導体領域に電気的に接続された第1金属パターンと、
平面視で前記導体プレート部より外側に前記第1金属パターンを取り囲むように前記第3絶縁膜上に設けられ、かつ、前記素子の第2電極に電気的に接続された第2金属パターンと、
を備え、
前記導体プレート部は、
平面視で前記素子領域を取り囲むように配置された第1導体パターンと、
平面視で前記第1導体パターンを取り囲むように配置された第2導体パターンと、
平面視で前記第1導体パターンと前記第2導体パターンとの間に配置され、かつ、前記第1導体パターンと前記第2導体パターンとを電気的に接続する第3導体パターンと、
を備え、
前記第1導体パターンは、前記第1絶縁膜の内周端部より内側であって、断面視で前記第2絶縁膜と前記第3絶縁膜との間に延びる第1延在部を有し、
前記第2導体パターンは、前記第1絶縁膜の外周端部より外側であって、断面視で前記第2絶縁膜と前記第3絶縁膜との間に延びる第2延在部を有し、
前記第1金属パターンは、平面視で前記第1延在部の一部および前記第1半導体領域の一部を内包し、かつ、断面視で前記第2絶縁膜および前記第3絶縁膜に形成された第1の共有の接続孔を通じて、前記第1延在部および前記第1半導体領域の両方と電気的に接続され、
前記第2金属パターンは、平面視で前記第2延在部の一部および前記半導体基板に形成された第1導電型の第2半導体領域の一部を内包し、かつ、断面視で前記第2絶縁膜および前記第3絶縁膜に形成された第2の共有の接続孔を通じて、前記第2延在部および前記第2半導体領域の両方と電気的に接続され、
前記第1金属パターンの外周端部は、前記第1導体パターンの外周端部から前記素子領域に向かって離れている、半導体装置。 - 請求項1記載の半導体装置において、
前記第1金属パターンの外周端部が、前記第1絶縁膜の内周端部より内側に配置されている、半導体装置。 - 請求項2記載の半導体装置において、
前記第1金属パターンの外周端部が、前記第1半導体領域の外周端部より内側に配置されている、半導体装置。 - 請求項1記載の半導体装置において、
前記第1金属パターンの外周端部と前記第1導体パターンの外周端部との間隔が1μm以上である、半導体装置。 - 請求項1記載の半導体装置において、
前記第2金属パターンの内周端部は、前記第2導体パターンの内周端部から前記半導体チップの外周に向かって離れている、半導体装置。 - 請求項5記載の半導体装置において、
前記第2金属パターンの内周端部が、前記第1絶縁膜の外周端部より外側に配置されている、半導体装置。 - 請求項5記載の半導体装置において、
前記第2金属パターンの内周端部と前記第2導体パターンの内周端部との間隔が1μm以上である、半導体装置。 - 請求項1記載の半導体装置において、
前記第1の共有の接続孔は、平面視で前記第1金属パターンの角部には配置されておらず、前記第1金属パターンの角部と角部との間に延在した状態で配置されている、半導体装置。 - 請求項1記載の半導体装置において、
前記第2の共有の接続孔は、平面視で前記第2金属パターンの角部には配置されておらず、前記第2金属パターンの角部と角部との間に延在した状態で配置されている、半導体装置。
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