JP6810059B2 - 先進的なパターニングプロセスにおけるスペーサ堆積および選択的除去のための装置および方法 - Google Patents
先進的なパターニングプロセスにおけるスペーサ堆積および選択的除去のための装置および方法 Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
Description
Claims (15)
- マルチパターニングプロセス中にスペーサ層を堆積しパターニングする方法であって、
基板上に配置されたパターニングされた構造であって、その間に画定された開口部の第1の群を有するパターニングされた構造の外面上にスペーサ層を共形的に形成することと、
前記基板上に形成された前記スペーサ層の第1の部分を、前記スペーサ層の第2の部分を処理することなく、選択的に処理することと、
前記スペーサ層の処理された前記第1の部分を選択的に除去することと
を含む方法。 - 前記パターニングされた構造が、アモルファスカーボン材料、窒化ケイ素、二酸化ケイ素または炭化ケイ素を含む、請求項1に記載の方法。
- 前記スペーサ層が、ポリシリコンまたはアモルファスシリコンを含む、請求項1または2に記載の方法。
- 前記基板上にスペーサ層を共形的に形成する前に前記基板を前処理することをさらに含む、請求項1から3のいずれか一項に記載の方法。
- 前記基板を前処理することが、
不活性ガスを含む前処理混合ガスを前記基板に供給することと、
前記基板の温度をセ氏約200度からセ氏約400度の間に維持することと
をさらに含む、請求項4に記載の方法。 - 約2000ワットの上部誘導結合ソース電力および約4000ワットの側部誘導結合ソース電力を印加することをさらに含む、請求項5に記載の方法。
- 前記スペーサ層を共形的に形成することが、シリコン系ガスとN2ガスとを含む堆積混合ガスを供給することをさらに含む、請求項1から6のいずれか一項に記載の方法。
- 前記堆積混合ガスを供給することが、
前記堆積混合ガスに6500ワット未満の誘導結合ソース電力を印加することと、
前記堆積混合ガスに100ワットから約500ワットの間のRFバイアス電力を印加することと
をさらに含む、請求項7に記載の方法。 - 前記スペーサ層の前記第1の部分を選択的に処理することが、不活性ガスを含む堆積後処理混合ガスを前記基板に供給することをさらに含む、請求項1から8のいずれか一項に記載の方法。
- 前記堆積後処理混合ガスを供給することが、RFソース電力なしで250ワットから約1500ワットの間のRFバイアス電力を前記堆積後処理混合ガスに印加することをさらに含む、請求項9に記載の方法。
- 前記スペーサ層の前記第1の部分を選択的に処理することが、前記スペーサ層の側壁およびコーナー部を処理することなく前記スペーサ層の上面および底面を選択的に処理することをさらに含む、請求項1から8のいずれか一項に記載の方法。
- 前記スペーサ層の処理された前記第1の部分を選択的に除去することが、
アンモニア(NH3)ガスと三フッ化窒素(NF3)ガスとを含む選択的除去混合ガスを供給することと、
遠隔プラズマ源を前記選択的除去混合ガスに印加することと
をさらに含む、請求項1から11のいずれか一項に記載の方法。 - 前記スペーサ層の処理された前記第1の部分を選択的に除去することが、前記スペーサ層の側壁およびコーナー部を含む前記第2の部分を実質的に攻撃することなく、前記スペーサ層の上面および底面を含む前記スペーサ層の前記第1の部分を優勢にエッチングすることをさらに含む、請求項1から11のいずれか一項に記載の方法。
- 前記基板から前記パターニングされた構造を除去することと、
前記開口部の第1の群の寸法よりも小さい寸法を有する開口部の第2の群を、エッチングされた前記スペーサ層に形成することと
をさらに含む、請求項1から13のいずれか一項に記載の方法。 - 前記スペーサ層を共形的に形成することと、前記スペーサ層の前記第1の部分を選択的に処理することと、前記スペーサ層の処理された前記第1の部分を選択的に除去することとが、全て単一の処理チャンバ内で行なわれる、請求項1から14のいずれか一項に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/729,932 | 2015-06-03 | ||
US14/729,932 US9484202B1 (en) | 2015-06-03 | 2015-06-03 | Apparatus and methods for spacer deposition and selective removal in an advanced patterning process |
PCT/US2016/033882 WO2016196073A1 (en) | 2015-06-03 | 2016-05-24 | Apparatus and methods for spacer deposition and selective removal in an advanced patterning process |
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