JP6773501B2 - Semiconductor device - Google Patents

Description

One aspect of the present invention relates to a semiconductor device.

One aspect of the present invention is not limited to the above technical fields. The technical field of one aspect of the invention disclosed in this specification and the like relates to a product, a method, or a manufacturing method. Alternatively, one aspect of the invention relates to a process, machine, manufacture, or composition (composition of matter). Therefore, more specifically, the technical fields of one aspect of the present invention disclosed in the present specification include semiconductor devices, display devices, liquid crystal display devices, light emitting devices, lighting devices, power storage devices, storage devices, imaging devices, and the like. The operation method or the manufacturing method thereof can be given as an example.

In the present specification and the like, the semiconductor device refers to all devices that can function by utilizing the semiconductor characteristics. Transistors and semiconductor circuits are one aspect of semiconductor devices. Further, the storage device, the display device, the image pickup device, and the electronic device may have a semiconductor device.

In recent years, IT technology has developed rapidly, and many high-performance semiconductor devices have been developed. For example, as an imaging device, an ultra-high speed image sensor, an ultra-sensitive image sensor, an ultra-high resolution image sensor, and the like have been developed.

In addition, oxide semiconductors are attracting attention as semiconductor materials applicable to transistors. For example, a technique for manufacturing a transistor using zinc oxide or an In-Ga-Zn-based oxide semiconductor as an oxide semiconductor is disclosed (see Patent Document 1 and Patent Document 2).

Japanese Unexamined Patent Publication No. 2007-123861 JP-A-2007-96055

While the amount of data and power consumption handled by semiconductor devices are increasing, there is a demand for smaller and thinner semiconductor devices and lower power consumption.

Therefore, in one aspect of the present invention, one of the problems is to provide a semiconductor device with reduced power consumption. Alternatively, one of the issues is to provide a small semiconductor device. Alternatively, one of the problems is to provide a semiconductor device suitable for high-speed operation. Alternatively, one of the problems is to provide a semiconductor device suitable for low voltage operation. Alternatively, one of the problems is to provide a semiconductor device having a transistor having a small off-current. Alternatively, one of the problems is to provide a semiconductor device that can be used in a wide temperature range. Alternatively, one of the issues is to provide a highly reliable semiconductor device.

Alternatively, one aspect of the present invention is to provide a new semiconductor device, a method of operating a new semiconductor device, a new electronic device, and the like.

The problems of one aspect of the present invention are not limited to the problems listed above. The issues listed above do not preclude the existence of other issues. Other issues are issues not mentioned in this item, which are described below. Issues not mentioned in this item can be derived from descriptions in the description or drawings by those skilled in the art, and can be appropriately extracted from these descriptions. In addition, one aspect of the present invention solves at least one of the above-listed problems and / or other problems.

One aspect of the present invention includes a first circuit, a first wiring, a second wiring, a third wiring, a fourth wiring, a fifth wiring, and a sixth wiring. It is a semiconductor device to have. The first circuit operates in the first mode or the second mode, and the first circuit includes a second circuit, a third circuit, a fourth circuit, and a fifth circuit. The fifth circuit has n (n is an integer of 2 or more) sixth circuit. Further, the second circuit, the third circuit, the fourth circuit, and the fifth circuit are electrically connected by the fifth wiring and the sixth wiring. The second circuit transfers the data of the first wiring to the fifth wiring and the data of the second wiring to the sixth wiring when the first circuit operates in the first mode. When it has a function and the first circuit operates in the second mode, the signal corresponding to the data of the fifth wiring is output to the third wiring, and the signal corresponding to the data of the sixth wiring is output. Has a function of outputting to the fourth wiring. The third circuit has a function of storing 1-bit imaging data. Further, the third circuit has a function of writing the complementary data stored in the third circuit to the sixth circuit when the first circuit operates in the first mode, and the first circuit also has a function of writing the complementary data stored in the third circuit to the sixth circuit. When operating in the second mode, it has a function of amplifying the complementary data transferred from the sixth circuit. Further, the fourth circuit has a function of precharging the fifth wiring and the sixth wiring. Further, the sixth circuit has a function of holding 1-bit complementary data written from the third circuit.

Further, the second circuit may include a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor. .. One of the source or drain of the first transistor is electrically connected to the first wire, the other of the source or drain of the first transistor is electrically connected to the fifth wire, and the first transistor One of the source or drain of the second transistor is electrically connected to the gate of the third transistor, and one of the source or drain of the second transistor is electrically connected to the third wiring and the source of the second transistor. Or the other of the drains is electrically connected to one of the sources or drains of the third transistor and the other of the sources or drains of the third transistor is electrically connected to one of the sources or drains of the sixth transistor. One of the source or drain of the fourth transistor is electrically connected to the second wire, and the other of the source or drain of the fourth transistor is electrically connected to the sixth wire. The other of the source or drain of the transistor is electrically connected to the gate of the sixth transistor, and one of the source or drain of the fifth transistor is electrically connected to the fourth wiring, and the fifth transistor. The other of the source or drain of the sixth transistor is electrically connected to the other of the source or drain of the sixth transistor.

Further, the third circuit may have a latch circuit.

Further, the sixth circuit may include a seventh transistor, an eighth transistor, a first capacitive element, and a second capacitive element. One of the source or drain of the seventh transistor is electrically connected to the fifth wiring, and the other of the source or drain of the seventh transistor is electrically connected to one terminal of the first capacitive element. , One of the source or drain of the eighth transistor is electrically connected to the sixth wiring, and the other of the source or drain of the eighth transistor is electrically connected to one terminal of the second capacitive element. The other terminal of the first capacitive element is electrically connected to the other terminal of the second capacitive element.

Further, the seventh transistor and the eighth transistor may have an oxide semiconductor in the active layer. Further, the oxide semiconductor may have In, Zn, and M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd or Hf).

Further, the fifth circuit may have a region overlapping with each of the second circuit, the third circuit, and the fourth circuit.

An electronic device having a semiconductor device according to an aspect of the present invention and a display device is also an aspect of the present invention.

In one aspect of the present invention, it is possible to provide a semiconductor device with reduced power consumption. Alternatively, a small semiconductor device can be provided. Alternatively, a semiconductor device suitable for high-speed operation can be provided. Alternatively, a semiconductor device suitable for low voltage operation can be provided. Alternatively, a semiconductor device having a transistor having a small off-current can be provided. Alternatively, a semiconductor device that can be used in a wide temperature range can be provided. Alternatively, a highly reliable semiconductor device can be provided.

Alternatively, in one aspect of the present invention, a new semiconductor device, a new operating method of the semiconductor device, a new electronic device, and the like can be provided.

The effects of one aspect of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. The other effects are the effects not mentioned in this item, which are described below. Effects not mentioned in this item can be derived from those described in the description or drawings by those skilled in the art, and can be appropriately extracted from these descriptions. In addition, one aspect of the present invention has at least one of the above-listed effects and / or other effects. Therefore, one aspect of the present invention may not have the effects listed above in some cases.

A block diagram illustrating an imaging device and a timing chart illustrating the operation of a line buffer. A circuit diagram illustrating a line buffer. A circuit diagram illustrating a line buffer. A circuit diagram schematically showing a device structure of a line buffer. A timing chart that describes the operation of the line buffer. A timing chart that describes the operation of the line buffer. A circuit diagram and a timing chart illustrating a potential generation circuit. A circuit diagram illustrating a line buffer. A circuit diagram illustrating a line buffer. A circuit diagram illustrating a line buffer. A circuit diagram illustrating a line buffer. A circuit diagram illustrating a line buffer. A block diagram illustrating a line buffer. A timing chart that describes the operation of the line buffer. A timing chart that describes the operation of the line buffer. Top view and sectional view explaining the transistor. Top view and sectional view explaining the transistor. The figure explaining the cross section in the channel width direction of a transistor. Top view and sectional view explaining the semiconductor layer. Top view and sectional view explaining the transistor. Top view and sectional view explaining the transistor. The figure explaining the cross section in the channel width direction of a transistor. The figure explaining the cross section in the channel length direction of a transistor. The figure explaining the cross section in the channel length direction of a transistor. Top view and sectional view explaining the transistor. Top view illustrating a transistor. The figure explaining the range of the atomic number ratio of the oxide which concerns on this invention. The figure explaining the crystal of InMZnO ₄ . Band diagram in a laminated structure of oxides. The figure explaining the structural analysis of CAAC-OS and a single crystal oxide semiconductor by XRD, and the figure which shows the selected area electron diffraction pattern of CAAC-OS. A cross-sectional TEM image of the CAAC-OS, a plane TEM image, and an image analysis image thereof. The figure which shows the electron diffraction pattern of nc-OS, and the cross-sectional TEM image of nc-OS. Cross-sectional TEM image of a-like OS. The figure which shows the change of the crystal part by electron irradiation of In-Ga-Zn oxide. A perspective view and a sectional view of a package containing an imaging device. A perspective view and a sectional view of a package containing an imaging device. The figure explaining the electronic device.

The embodiment will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that the form and details of the present invention can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention is not construed as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same reference numerals may be used in common between different drawings for the same parts or parts having similar functions, and the repeated description thereof may be omitted. The hatching of the same elements constituting the drawings may be omitted or changed as appropriate between different drawings.

The ordinal numbers attached as the first and second numbers are used for convenience and do not indicate the process order or the stacking order. Therefore, for example, the "first" can be appropriately replaced with the "second" or "third" for explanation. In addition, the ordinal numbers described in the present specification and the like may not match the ordinal numbers used to specify one aspect of the present invention.

Also, in the drawings, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. The drawings schematically show ideal examples, and are not limited to the shapes or values shown in the drawings. For example, it is possible to include variations in signal, voltage, or current due to noise, or variations in signal, voltage, or current due to timing lag.

Further, in the present specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. Then, a channel region is provided between the drain (drain terminal, drain region or drain electrode) and the source (source terminal, source region or source electrode), and a current flows through the drain, the channel region and the source. Can be done.

Here, since the source and drain change depending on the structure or operating conditions of the transistor, it is difficult to limit which is the source or drain. Therefore, the terms "source" and "drain" can be interchanged in some cases or in some circumstances.

Further, in the present specification and the like, when it is explicitly stated that X and Y are connected, the case where X and Y are electrically connected and the case where X and Y function. It is assumed that the case where X and Y are directly connected and the case where X and Y are directly connected are disclosed in the present specification and the like. Therefore, it is not limited to a predetermined connection relationship, for example, a connection relationship shown in a figure or a sentence, and a connection relationship other than the connection relationship shown in the figure or the sentence shall be described in the figure or the sentence.

Here, X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

As an example of the case where X and Y are directly connected, an element (for example, a switch, a transistor, a capacitive element, an inductor, a resistance element, a diode, a display) that enables an electrical connection between X and Y is used. Elements (eg, switches, transistors, capacitive elements, inductors) that allow an electrical connection between X and Y when the element, light emitting element, load, etc. are not connected between X and Y. , A resistance element, a diode, a display element, a light emitting element, a load, etc.), and X and Y are connected to each other.

As an example of the case where X and Y are electrically connected, an element (for example, a switch, a transistor, a capacitance element, an inductor, a resistance element, a diode, a display) that enables an electrical connection between X and Y is used. One or more elements, light emitting elements, loads, etc.) can be connected between X and Y. The switch has a function of controlling on / off. That is, the switch is in a conductive state (on state) or a non-conducting state (off state), and has a function of controlling whether or not a current flows. Alternatively, the switch has a function of selecting and switching the path through which the current flows. It should be noted that the case where X and Y are electrically connected includes the case where X and Y are directly connected.

As an example of the case where X and Y are functionally connected, a circuit that enables functional connection between X and Y (for example, a logic circuit (inverter, NAND circuit, NOR circuit, etc.), signal conversion, etc.) Circuits (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (boost circuit, step-down circuit, etc.), level shifter circuit that changes the signal potential level, etc.), voltage source, current source, switching Circuits, amplification circuits (circuits that can increase signal amplitude or current amount, operational amplifiers, differential amplification circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, storage circuits, control circuits, etc.) are X and Y. It is possible to connect one or more in between. As an example, even if another circuit is sandwiched between X and Y, if the signal output from X is transmitted to Y, it is assumed that X and Y are functionally connected. To do. When X and Y are functionally connected, it includes a case where X and Y are directly connected and a case where X and Y are electrically connected.

When it is explicitly stated that X and Y are electrically connected, it is different when X and Y are electrically connected (that is, between X and Y). When X and Y are functionally connected (that is, when they are connected by sandwiching another circuit between X and Y) and when they are functionally connected by sandwiching another circuit between X and Y. (That is, when X and Y are directly connected (that is, when another element or another circuit is not sandwiched between X and Y)). It shall be disclosed in the book. That is, when it is explicitly stated that it is electrically connected, the same contents as when it is explicitly stated that it is simply connected are disclosed in the present specification and the like. It is assumed that it has been done.

Note that, for example, the source of the transistor (or the first terminal, etc.) is electrically connected to X via (or not) Z1, and the drain of the transistor (or the second terminal, etc.) connects to Z2. Through (or not) being electrically connected to Y, or the source of the transistor (or the first terminal, etc.) is directly connected to one part of Z1 and another part of Z1. Is directly connected to X, the drain of the transistor (or the second terminal, etc.) is directly connected to one part of Z2, and another part of Z2 is directly connected to Y. Then, it can be expressed as follows.

For example, "X and Y, the source of the transistor (or the first terminal, etc.) and the drain (or the second terminal, etc.) are electrically connected to each other, and the X, the source of the transistor (or the first terminal, etc.) (Terminals, etc.), transistor drains (or second terminals, etc.), and Y are electrically connected in this order. " Alternatively, "the source of the transistor (or the first terminal, etc.) is electrically connected to X, the drain of the transistor (or the second terminal, etc.) is electrically connected to Y, and the X, the source of the transistor (such as the second terminal). Or the first terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y are electrically connected in this order. " Alternatively, "X is electrically connected to Y via the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor, and X, the source (or first terminal, etc.) of the transistor. The terminals, etc.), the drain of the transistor (or the second terminal, etc.), and Y are provided in this connection order. " By defining the order of connections in the circuit configuration using the same representation as these examples, the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor can be separated. Separately, the technical scope can be determined.

Alternatively, as another expression, for example, "the source of the transistor (or the first terminal, etc.) is electrically connected to X via at least the first connection path, and the first connection path is. It does not have a second connection path, the second connection path between the source of the transistor (or the first terminal, etc.) and the drain of the transistor (or the second terminal, etc.) via the transistor. The first connection path is a path via Z1, and the drain of the transistor (or the second terminal, etc.) is electrically connected to Y via at least a third connection path. It is connected, and the third connection path does not have the second connection path, and the third connection path is a path via Z2. " Alternatively, "the source of the transistor (or the first terminal, etc.) is electrically connected to X via Z1 by at least the first connection path, and the first connection path is the second connection path. The second connection path has a connection path via a transistor, and the drain of the transistor (or a second terminal, etc.) is via Z2 by at least a third connection path. , Y is electrically connected, and the third connection path does not have the second connection path. " Alternatively, "the source of the transistor (or the first terminal, etc.) is electrically connected to X via Z1 by at least the first electrical path, the first electrical path being the second. It does not have an electrical path, the second electrical path is an electrical path from the source of the transistor (or the first terminal, etc.) to the drain of the transistor (or the second terminal, etc.). The drain (or second terminal, etc.) of the transistor is electrically connected to Y via Z2 by at least a third electrical path, the third electrical path being a fourth electrical path. The fourth electrical path is an electrical path from the drain of the transistor (or the second terminal, etc.) to the source of the transistor (or the first terminal, etc.). " can do. By defining the connection path in the circuit configuration using the same representation as these examples, the source (or first terminal, etc.) of the transistor and the drain (or second terminal, etc.) can be distinguished. , The technical scope can be determined.

It should be noted that these expression methods are examples and are not limited to these expression methods. Here, it is assumed that X, Y, Z1 and Z2 are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

Even if the circuit diagram shows that the independent components are electrically connected to each other, the case where one component has the functions of a plurality of components together. There is also. For example, when a part of the wiring has a function as an electrode, one conductive film has both a function of the wiring and a function of a component of the function of the electrode. Therefore, the electrical connection in the present specification also includes the case where one conductive film has the functions of a plurality of components in combination.

The term "membrane" and the term "layer" can be interchanged with each other in some cases or in some circumstances. For example, it may be possible to change the term "conductive layer" to the term "conductive layer". Alternatively, for example, it may be possible to change the term "insulating layer" to the term "insulating film".

In general, the potential (voltage) is relative, and the magnitude is determined by the relative magnitude from the reference potential. Therefore, even if it is described as "ground", "GND", "ground", etc., the potential is not necessarily 0 volt. For example, "ground" or "GND" may be defined with reference to the lowest potential in the circuit. Alternatively, the circuit may define "ground" or "GND" with reference to an intermediate potential. In that case, the positive potential and the negative potential are defined with the potential as a reference.

In this specification, terms such as "above" and "below" are used for convenience in order to explain the positional relationship between the configurations with reference to the drawings. Further, the positional relationship between the configurations changes appropriately depending on the direction in which each configuration is depicted. Therefore, it is not limited to the words and phrases explained in the specification, and can be appropriately paraphrased according to the situation.

(Embodiment 1)
In the present embodiment, an imaging device will be described as an example of the semiconductor device.

One aspect of the present invention relates to a line buffer having a plurality of long-term storage memories per working memory. The line buffer has a function of holding the image pickup data output from the pixels of the image pickup apparatus and outputting the held image pickup data to, for example, a frame memory of a signal processing LSI. The working memory has a latch circuit and has a higher write speed and read speed than a DRAM or a non-volatile memory. Further, the long-term memory memory is a memory having a capacitive element and a transistor having an extremely small off-current such as a transistor having an active layer or an active region formed of an oxide semiconductor. A memory having a transistor having an extremely small off-current occupies a smaller area per bit than a memory having a latch circuit. That is, the storage capacity per unit area is large. As described above, the line buffer having a plurality of long-term storage memories per working memory according to one aspect of the present invention can realize high-speed write operation and read operation even if it is small.

<Imaging device>
FIG. 1A is a block diagram showing a configuration of an image pickup apparatus 10 according to an aspect of the present invention. The image pickup apparatus 10 includes a pixel 11, a circuit 13, a circuit 14, a circuit 15, a circuit 16, and a circuit 17. Further, the pixels 11 are arranged in a matrix to form a pixel array 12 having p rows and q columns (p and q are natural numbers). Further, the circuits 16 are arranged in a matrix, and the circuits 17 are arranged for each circuit 16 in each row.

The circuit 16 has a circuit 16A and a circuit 16B, and the circuit 17 has a circuit 17A and a circuit 17B. Further, the circuit 17A is electrically connected to the circuit 16A, and the circuit 17B is electrically connected to the circuit 16B.

The arrangement of each circuit block in the drawing specifies the positional relationship for explanation, and even if it is shown that different circuit blocks realize different functions, the actual circuit blocks are different in the same circuit block. In some cases, it is provided so as to realize the functions of. Further, the function of each circuit block in the drawing is for specifying the function for explanation, and even if it is shown as one circuit block, in the actual circuit block, the processing performed by one circuit block is performed by a plurality of circuit blocks. In some cases, it is provided to do so.

The circuit 13 has a function as a row driver that selects a row of the pixel array 12. The circuit 14 has a function as a column driver that selects a column of the pixel array 12. The circuit 13 selects the pixel 11 in the first row, then selects the pixel 11 in the second row, and selects the pixel 11 in the p-th row in order. That is, the circuit 13 has a function of scanning the pixel 11 in the horizontal direction.

Various circuits such as a decoder and a shift register are used in the circuit 13 and the circuit 14.

The circuit 15 has a function as an A / D conversion circuit. The analog imaging data output from the pixel 11 is converted into digital data.

In the present specification, the term "imaging data" may represent a signal output from a pixel depending on the illuminance of the light applied to the pixel. Further, when simply described as "imaging data", it may represent imaging data before A / D conversion, or may represent imaging data after A / D conversion.

The circuit 16A and the circuit 16B have a function as a line buffer for holding digital data. The digital data output from the circuit 15 is written to the circuit 16A or the circuit 16B, held, and then read, and output to, for example, a frame memory of a signal processing LSI. The digital data output from the circuit 15 is not directly output to the frame memory of the signal processing LSI, but is held in the circuit 16A or the circuit 16B and then output, for example, the circuit 15 and the frame of the signal processing LSI. Digital data can be output from the circuit 15 to the frame memory of the signal processing LSI even when the drive speed and access timing are different from those of the memory.

The circuit 17A has a function as a control circuit that controls the overall operation of the circuit 16A. Further, the circuit 17B has a function as a control circuit that controls the overall operation of the circuit 16B. The details of the functions of the circuit 17A and the circuit 17B will be described later in the third embodiment.

FIG. 1B is a timing chart showing the operations of the circuit 13, the circuit 15, the circuit 16A and the circuit 16B. In the period T1, while the circuit 13 is selecting the pixel 11 in the Nth row (N is a natural number of p or less), the imaging data output from the pixel 11 in the Nth row is A / D converted by the circuit 15. Will be done. Further, the imaging data output from the pixel 11 on the N-1th line and A / D converted is written in the circuit 16A. Further, the imaging data output from the pixel 11 on the N-2th line is held in the circuit 16B, and the imaging data is read out from the circuit 16B.

Next, in the period T2, while the circuit 13 is selecting the pixel 11 in the N + 1 line, the imaging data output from the pixel 11 in the N + 1 line is A / D converted by the circuit 15, and in the period T1. The imaging data on the N-1th line written in the circuit 16A is read out. Then, the imaging data output from the pixel 11 on the Nth row in the period T1 and A / D converted is written in the circuit 16B. Further, in the period T3, while the circuit 13 is selecting the pixel 11 in the N + 2nd row, the imaging data output from the pixel 11 in the N + 2nd row is A / D converted by the circuit 15. Then, the imaging data output from the pixel 11 on the N + 1th row in the period T2 and A / D converted is written in the circuit 16A, and the imaging data in the Nth row written in the circuit 16B in the period T2 is read out.

By providing a plurality of line buffers (circuit 16A, circuit 16B) in this way, it is possible to write the imaging data to the line buffer and read the imaging data from the line buffer in parallel. This makes it possible to provide an imaging device 10 that operates at high speed.

<Line buffer>
FIG. 2 shows the circuit configurations of the circuit 16A and the circuit 16B. Circuit 16A includes circuit 20, circuit 30, circuit 40 and circuit 50. The configuration of the circuit 16B is the same as that of the circuit 16A.

The circuit 16A and the circuit 16B are electrically connected by wiring 61a (WBL), wiring 61b (WBLB), wiring 62a (RBL), and wiring 62b (RBLB). Further, the circuit 20, the circuit 30, the circuit 40, and the circuit 50 are electrically connected by the wiring 63a (LBL) and the wiring 63b (LBLB).

The circuit 20 has a function as a write / read selection switch. The circuit 30 has a function as a working memory that temporarily stores 1-bit imaging data. The circuit 40 has a function as a local precharge circuit that precharges the wiring 63a (LBL) and the wiring 63b (LBLB), which are local bit lines. The circuit 50 has a function as a long-term storage memory that holds n-bit (n is an integer of 2 or more) imaging data.

Note that n can take values such as 8, 16 and 32.

The wiring 61a (WBL), the wiring 61b (WBLB), the wiring 62a (RBL), and the wiring 62b (RBLB) have a function as a global bit line. Further, the wiring 63a (LBL) and the wiring 63b (LBLB) have a function as a local bit line. The imaging data written in the circuit 16A or the circuit 16B is input to the wiring 61a (WBL) and the wiring 61b (WBLB), and is read from the circuit 16A or the circuit 16B in the wiring 62a (RBL) and the wiring 62b (RBLB). The captured imaging data is output.

As described above, by separating the global bit line for writing the imaging data and the global bit line for reading the imaging data, as shown in FIG. 1B, the imaging data to the circuit 16A can be input. In parallel with the writing, the imaging data held in the circuit 16B can be read out. Further, the imaging data can be written to the circuit 16B in parallel with the reading of the imaging data held in the circuit 16A.

The wiring 61a (WBL) and the wiring 61b (WBLB) are bit line pairs for transmitting complementary data. The wiring 62a (RBL) and the wiring 62b (RBLB) are also bit line pairs for transmitting complementary data. That is, the wiring 61b (WBLB) is input with data in which the logic of the data input to the wiring 61a (WBL) is inverted, and the wiring 62b (RBLB) is input with the logic of the data output to the wiring 62a (RBL) inverted. The data is output.

<Write / read selection switch>
The circuit 20 includes a transistor 21, a transistor 22, a transistor 23, a transistor 24, a transistor 25, and a transistor 26. The transistors 21 to 26 are all n-channel transistors.

In the present specification, the n-channel transistor may be referred to as an n-ch transistor, and the p-channel transistor may be referred to as a p-ch transistor.

One of the source and drain of the transistor 21 is electrically connected to the wiring 61a (WBL). Further, the other side of the source or drain of the transistor 21 is electrically connected to the gate and the wiring 63a (LBL) of the transistor 23. Further, the gate of the transistor 21 is electrically connected to the wiring 27 (Wsw). Further, one of the source and drain of the transistor 22 is electrically connected to the wiring 62b (RBLB). Further, the other side of the source or drain of the transistor 22 is electrically connected to one of the source or drain of the transistor 23. Further, the gate of the transistor 22 is electrically connected to the wiring 28 (Rsw). Further, the other side of the source or drain of the transistor 23 is electrically connected to one of the source or drain of the transistor 26 and the wiring 29.

For example, an L level potential can be applied to the wiring 29.

In the present specification, H level indicates a high potential and L level indicates a low potential. Further, the L level can be, for example, a ground potential.

Further, one of the source and drain of the transistor 24 is electrically connected to the wiring 61b (WBLB). Also, the other side of the source or drain of the transistor 24 is electrically connected to the gate and wiring 63b (LBLB) of the transistor 26. Further, the gate of the transistor 24 is electrically connected to the wiring 27 (Wsw). Further, one of the source and drain of the transistor 25 is electrically connected to the wiring 62a (RBL). Further, the other side of the source or drain of the transistor 25 is electrically connected to the other side of the source or drain of the transistor 26. Further, the gate of the transistor 25 is electrically connected to the wiring 28 (Rsw).

When the circuit 16A performs a writing operation, the transistor 21 and the transistor 24 are turned on. As a result, the imaging data of the wiring 61a (WBL) is transferred to the wiring 63a (LBL), and the imaging data of the wiring 61b (WBLB) is transferred to the wiring 63b (LBLB).

When the circuit 16A performs a read operation, the transistor 22 and the transistor 25 are turned on. As a result, the inverted signal of the signal corresponding to the imaging data of the wiring 63a (LBL) is output to the wiring 62b (RBLB), and the inverted signal of the signal corresponding to the imaging data of the wiring 63b (LBLB) is output to the wiring 62a (RBL). It is output.

<Working memory>
The circuit 30 includes a transistor 31, a transistor 32, a transistor 33, and a transistor 34. The transistor 31 and the transistor 32 are n-ch type transistors, and the transistor 33 and the transistor 34 are p-ch type transistors.

One of the source or drain of the transistor 31, the gate of the transistor 32, one of the source or drain of the transistor 33, and the gate of the transistor 34 are electrically connected to the wiring 63a (LBL). Further, one of the gate of the transistor 31 and the source or drain of the transistor 32, and one of the gate of the transistor 33 and the source or drain of the transistor 34 are electrically connected to the wiring 63b (LBLB).

Further, the other side of the source or drain of the transistor 31 is electrically connected to the other side of the source or drain of the transistor 32 and the wiring 35 (VLL). Further, the other side of the source or drain of the transistor 33 is electrically connected to the other side of the source or drain of the transistor 34 and the wiring 36 (VHH).

As described above, the inverter is composed of the transistor 31 and the transistor 33, and the inverter is composed of the transistor 32 and the transistor 34. The input terminals of these two inverters are electrically connected to the other output terminal, respectively, to form a latch circuit. As a result, 1-bit imaging data can be temporarily stored. Further, the circuit 30 functions as a differential amplifier circuit, and can amplify and store the imaging data.

Since the circuit 30 has a latch circuit, it has a feature that the data writing speed to the circuit 30 and the data reading speed from the circuit 30 are faster than those of a DRAM, a non-volatile memory, or the like.

The transistor 31 and the transistor 32 have a function as a drive transistor (pull-down transistor). Further, the transistor 33 and the transistor 34 have a function as a load transistor (pull-up transistor).

Further, the wiring 35 (VLL) and the wiring 36 (VHH) have a function of supplying a power supply potential to the two inverters. As the power supply potential, for example, the L level potential can be supplied to the wiring 35 (VLL) and the H level potential can be supplied to the wiring 36 (VHH).

<Local precharge circuit>
The circuit 40 includes a transistor 41, a transistor 42, and a transistor 43. The transistors 41 to 43 are all n-ch type transistors.

One of the source or drain of the transistor 41 and one of the source or drain of the transistor 42 are electrically connected to the wiring 63a (LBL). Further, the other source or drain of the transistor 41 and one of the source or drain of the transistor 43 are electrically connected to the wiring 63b (LBLB).

Further, the gate of the transistor 41, the gate of the transistor 42, and the gate of the transistor 43 are electrically connected to the wiring 44 (PC). Further, the other side of the source or drain of the transistor 42 is electrically connected to the other side of the source or drain of the transistor 43 and the wiring 45 (VPC).

The transistor 41 has a function as an equalizer that equalizes the potentials of the wiring 63a (LBL) and the wiring 63b (LBLB). Further, the transistor 42 has a function of controlling the precharge operation of the wiring 63a (LBL). Further, the transistor 43 has a function of controlling the precharge operation of the wiring 63b (LBLB).

Further, the wiring 44 (PC) has a function as a signal line for supplying a signal for controlling the precharge operation of the wiring 63a (LBL) and the wiring 63b (LBLB). Further, the wiring 45 (VPC) has a function as a power supply line for supplying a precharge potential.

When precharging the wiring 63a (LBL) and the wiring 63b (LBLB), for example, the transistor 41, the transistor 42, and the transistor 43 are turned on by setting the potential of the wiring 44 (PC) to the H level. As a result, the potentials of the wiring 63a (LBL) and the wiring 63b (LBLB) can be set to the precharge potential which is the potential of the wiring 45 (VPC).

The precharge potential can be, for example, "VDD / 2". Here, assuming that the H level potential is "VHH" and the L level potential is "VLL", it is defined as "VDD = VHH + VLL". In particular, when the L level potential is the ground potential, "VDD" indicates the H level potential.

<Long-term memory>
The circuit 50 has n circuits 51. Further, one circuit 51 has one circuit 52a and one circuit 52b, respectively. The circuit 52a includes a transistor 53a and a capacitive element 54a. Further, the circuit 52b has a transistor 53b and a capacitance element 54b. Although the transistor 53a and the transistor 53b are n-ch type transistors in FIG. 2, they may be p-ch type.

That is, the circuit 50 has n circuits 51, a circuit 52a, a circuit 52b, a transistor 53a, a transistor 53b, a capacitance element 54a, and a capacitance element 54b, respectively.

One of the source or drain of one transistor 53a is electrically connected to one terminal of one capacitive element 54a. Further, the other of the source or drain of the n transistors 53a is electrically connected to one wiring 63a (LBL).

Further, one of the source and drain of one transistor 53b is electrically connected to the other terminal of one capacitive element 54b. Further, the other of the source or drain of the n transistors 53b is electrically connected to one wiring 63b (LBLB).

Further, the gate of one transistor 53a and the gate of one transistor 53b are electrically connected to one wiring 55 (WL). That is, n wires 55 (WL) are provided, and the gates of the n transistors 53a and the gates of the transistors 53b are electrically connected to n different wires 55 (WL).

Further, the other terminal of the n capacitance elements 54a and one terminal of the n capacitance elements 54b are electrically connected to one wiring 56. For example, an L level potential can be applied to the wiring 56.

It should be noted that n circuits 51, n circuits 52a, n circuits 52b, n transistors 53a, n transistors 53b, n capacitive elements 54a, n capacitive elements 54b and n wirings. 55 (WL) is distinguished by using a code such as [0], [1], [n-1].

Further, the circuit 52a has a function of holding the image pickup data transferred from the wiring 63a (LBL), and the circuit 52b has a function of holding the image pickup data transferred from the wiring 63b (LBLB). That is, the circuit 51 has a function of holding 1-bit complementary data.

Further, the wiring 55 (WL) has a function as a word line. That is, it has a function of selecting a circuit 51 that performs a write operation or a read operation.

Here, by reducing the off-currents of the transistors 53a and 53b, the holding time of the circuit 51 can be lengthened. The off-current here means the current that flows between the source and the drain when the transistor is in the off state. When the transistor is an n-channel type, for example, when the threshold voltage is about 0V to 2V, the current flowing between the source and the drain when the voltage between the gate and the source is a negative voltage is turned off. Can be called. Further, the extremely small off-current means, for example, that the off-current per 1 μm of the channel width is 100 zA (zeptoampere) or less. Since the smaller the off current is, the more preferable it is. Therefore, the standardized off current is preferably 10 zA / μm or less, or 1 zA / μm or less, and more preferably 10 yA (yoctoampere) / μm or less. 1zA is 1 × ^{10 -21} A, 1yA is 1 × ^{10 -24} A.

In order to make the off-current extremely small in this way, the channel formation region of the transistor may be formed of a semiconductor having a wide bandgap. Examples of such semiconductors include oxide semiconductors. Since the bandgap of the oxide semiconductor is 3.0 eV or more, the transistor in which the active layer or the active region is formed of the oxide semiconductor (hereinafter referred to as OS transistor) has a small leakage current due to thermal excitation and an off current. Extremely small. The channel forming region of the OS transistor is preferably an oxide semiconductor containing at least one of indium (In) and zinc (Zn). As such an oxide semiconductor, In—M—Zn oxide (element M is, for example, Al, Ga, Y or Sn) is typical. By reducing impurities such as water or hydrogen that serve as electron donors, and also reducing oxygen deficiency, oxide semiconductors can be made i-type (intrinsic semiconductors) or as close as possible to i-type. .. Here, such an oxide semiconductor can be referred to as a highly purified oxide semiconductor. By applying a highly purified oxide semiconductor, the off-current of the OS transistor standardized by the channel width can be reduced to about several yA / μm or more and several zA / μm or less.

By using the transistor 53a and the transistor 53b as an OS transistor, the holding time of the circuit 51 can be lengthened, so that the circuit 51 can be used as a non-volatile memory circuit. As a result, data can be retained in the circuit 51 for a long period of time even if the refresh operation or the like is not performed or the frequency of the refresh operation or the like is extremely low, and the power consumption can be reduced. Further, in the OS transistor, the temperature dependence of the off-current characteristic is small. Therefore, the normalized off current of the OS transistor can be set to 100 zA or less even at a high temperature (for example, 100 ° C. or higher). Therefore, by applying the OS transistor to the circuit 51, data can be retained without being lost even in a high temperature environment. Therefore, it is possible to obtain an image pickup apparatus 10 having high reliability even in a high temperature environment.

One circuit 51 having two transistors and two capacitive elements can hold one bit of complementary data. That is, the occupied area per bit is smaller than that of the circuit 30 having the latch circuit. That is, the storage capacity per unit area is large.

As described above, the circuit 16 which is the line buffer of one aspect of the present invention has the circuit 30 which is a memory whose writing speed and reading speed are faster than those of a DRAM or a non-volatile memory, and the storage capacity per unit area is larger than that of the circuit 30. It has a large circuit 51 and. From the above, the circuit 16 can be a small line buffer capable of high-speed writing and reading operations.

The memory that can be used in the circuit 50 is not limited to the memory that uses the OS transistor. For example, a non-volatile memory that does not use an OS transistor can be used for the circuit 50.

When the circuit 16 does not perform the write operation and the read operation at the same time, the wiring 61a (WBL) and the wiring 62b (RBLB) are made into one wiring as shown in FIG. 3, and the wiring 61b (WBLB) and the wiring 62a (RBL) are used. ) Can be one wiring. With such a configuration, the number of wires included in the image pickup apparatus 10 can be reduced, and the image pickup apparatus 10 can be miniaturized.

For example, the wiring 61a (WBL) and the wiring 62b (RBLB) may be one wiring, and the wiring 61b (WBLB) and the wiring 62a (RBL) may be separate wirings. Further, for example, the wiring 61b (WBLB) and the wiring 62a (RBL) may be used as one wiring, and the wiring 61a (WBL) and the wiring 62b (RBLB) may be used as separate wirings.

Further, wiring having a function as a global bit line may be further provided in addition to the wiring 61a (WBL), the wiring 61b (WBLB), the wiring 62a (RBL), and the wiring 62b (RBLB).

<Device structure>
In the image pickup apparatus 10, the transistor 53a and the transistor 53b included in the circuit 50 may be an OS transistor, and the other transistor may be, for example, a transistor having an active layer or an active region formed of silicon (hereinafter, referred to as a Si transistor). .. In this case, the circuit 50 can be formed on the region where the circuit 20, the circuit 30, and the circuit 40 are formed, as in the device configuration example of the circuit 16A shown in FIG. With such a laminated structure, the image pickup apparatus 10 can be miniaturized. Further, the capacity of the circuit 16A can be increased.

Further, the channel length and channel width of the transistor included in the circuit 30 can be increased. Thereby, the variation of the threshold voltage of the transistor included in the circuit 30 can be reduced. As a result, the SNM (Static Noise Margin) becomes large, and low-voltage operation can be performed.

In FIG. 4, the circuit 16A has a two-layer structure consisting of a layer having a Si transistor (hereinafter referred to as a Si layer) and a layer having an OS transistor (hereinafter referred to as an OS layer), but the present invention is not limited to this. .. For example, two OS layers may be formed, or three or more layers may be formed. By increasing the number of layers, the image pickup apparatus 10 can be further miniaturized and the capacity of the circuit 16A can be increased as compared with the case shown in FIG.

The circuit 16B can have the same device structure as the circuit 16A. Further, the Si layer of the circuit 16A and the Si layer of the circuit 16B can be provided in the same layer. Further, the OS layer of the circuit 16A and the OS layer of the circuit 16B can be provided on the same layer.

<Operation example>
Next, the writing operation and the reading operation of the circuit 16A will be described in detail using the timing charts shown in FIGS. 5 and 6. The timing chart shows wiring 27 (Wsw), wiring 28 (Rsw), wiring 35 (VLL), wiring 36 (VHH), wiring 44 (PC), wiring 55 (WL), wiring 61a (WBL), wiring 61b ( WBLB), wiring 63a (LBL) and wiring 63b (LBLB). The write operation and read operation of the circuit 16B are the same as the write operation and read operation of the circuit 16A.

FIG. 5 is a timing chart showing the writing operation of the circuit 16A. At time T00, the circuit 30 is activated by setting the potential of the wiring 35 (VLL) to the L level and the potential of the wiring 36 (VHH) to the H level. As a result, the circuit 16A can perform the writing operation.

At time T01, the A / D converted imaging data by the circuit 15 is transferred to the wiring 61a (WBL) and the wiring 61b (WBLB).

At time T02, the transistor 21 and the transistor 24 are turned on by setting the potential of the wiring 27 (Wsw) to the H level. As a result, the imaging data is transferred from the wiring 61a (WBL) to the wiring 63a (LBL) and from the wiring 61b (WBLB) to the wiring 63b (LBLB), and the imaging data is written in the circuit 30. Further, the transistor 53a [0] and the transistor 53b [0] are turned on by setting the potential of the wiring 55 [0] (WL [0]) to the H level. As a result, the imaging data written in the circuit 30 is written to the capacitive element 54a [0] via the transistor 53a [0] and to the capacitive element 54b [0] via the transistor 53b [0].

The data written in the capacitive element 54b [0] is data in which the logic of the imaging data written in the capacitive element 54a [0] is inverted. That is, 1-bit complementary data can be held by the capacitive element 54a [0] and the capacitive element 54b [0].

At time T03, the transistor 21 and the transistor 24 are turned off by setting the potential of the wiring 27 (Wsw) to the L level. As a result, the electrical connection between the wiring 61a (WBL) and the wiring 63a (LBL) is cut off, and the electrical connection between the wiring 61b (WBLB) and the wiring 63b (LBLB) is cut off. As a result, the imaging data written in the circuit 30 can be made independent of the wiring 61a (WBL) and the wiring 61b (WBLB).

At time T04, the transistor 53a [0] and the transistor 53b [0] are turned off by setting the wiring 55 [0] (WL [0]) to the L level. At time T02 to time T04 when the transistor 53a [0] and the transistor 53b [0] are turned on, the imaging data is continuously written from the circuit 30 to the capacitive element 54a [0] and the capacitive element 54b [0].

At time T11 to time T14, new imaging data is written to the capacitive element 54a [1] and the capacitive element 54b [1]. Transistor 53a [1] and transistor 53b [1] are turned on by setting the potential of wiring 55 [1] (WL [1]) to H level at time T12, and wiring 55 [1] (WL [1]) is turned on at time T14. ]), The transistor 53a [1] and the transistor 53b [1] are turned off by setting the potential to the L level. Other operations are the same as the operations at time T01 to time T04.

In this way, the imaging data is written in order from the capacitive element 54a [0] and the capacitive element 54b [0] to the capacitive element 54a [n-1] and the capacitive element 54b [n-1]. At time T21 to time T24, imaging data is written to the capacitive element 54a [n-1] and the capacitive element 54b [n-1]. Transistor 53a [n-1] and transistor 53b [n-1] are turned on by setting the potential of wiring 55 [n-1] (WL [n-1]) to H level at time T22, and wiring is performed at time T24. The transistor 53a [n-1] and the transistor 53b [n-1] are turned off by setting the potential of 55 [n-1] (WL [n-1]) to the L level. Other operations are the same as the operations at time T01 to time T04.

At time T30, the potentials of the wiring 35 (VLL) and the wiring 36 (VHH) are set to "VDD / 2". As a result, the circuit 30 becomes inactive and the writing operation ends. The potentials of the wiring 35 (VLL) and the wiring 36 (VHH) can be controlled in synchronization with the potential of the wiring 55 (WL).

FIG. 6 is a timing chart showing the read operation of the circuit 16A. By the writing operation shown in FIG. 5, the imaging data held in the capacitive element 54a [0] to the capacitive element 54a [n-1] and the capacitive element 54b [0] to the capacitive element 54b [n-1] are read out and output to the outside. To do.

At time T01, the circuit 30 is deactivated by setting the potentials of the wiring 35 (VLL) and the wiring 36 (VHH) to "VDD / 2". Further, by setting the potential of the wiring 45 (VPC) to "VDD / 2" and setting the potential of the wiring 44 (PC) to the H level and turning on the transistor 41, the transistor 42, and the transistor 43, the wiring 63a (LBL) and the wiring 63b (LBLB) is precharged to the potential "VDD / 2". As described above, the circuit 16A can perform the read operation. The potential of the wiring 45 (VPC) is not shown in FIG.

At time T02, the transistor 41, the transistor 42, and the transistor 43 are turned off by setting the potential of the wiring 44 (PC) to the L level. Further, the transistor 53a [0] and the transistor 53b [0] are turned on by setting the potential of the wiring 55 [0] (WL [0]) to the H level. As described above, the imaging data held in the capacitive element 54a [0] is transferred to the wiring 63a (LBL), the imaging data held in the capacitive element 54b [0] is transferred to the wiring 63b (LBLB), and each imaging data. Is transferred to circuit 30. That is, the 1-bit complementary data held in the capacitive element 54a [0] and the capacitive element 54b [0] is transferred to the circuit 30.

At time T03, the circuit 30 is activated by setting the potential of the wiring 35 (VLL) to the L level and the potential of the wiring 36 (VHH) to the H level. Since the imaging data transferred to the circuit 30 is complementary data, the circuit 30 functions as a differential amplifier circuit to amplify the imaging data. Therefore, even if the potential difference between the imaging data held in the capacitive element 54a [0] and the imaging data held in the capacitive element 54b [0] is small, highly reliable reading operation can be performed. In addition, the read operation can be performed at high speed.

At time T04, the transistor 22 and the transistor 25 are turned on by setting the potential of the wiring 28 (Rsw) to the H level. As a result, the inverted signal of the signal corresponding to the imaging data transferred to the circuit 30 is output to the wiring 62a (RBL) and the wiring 62b (RBLB), and the imaging data is read out to the outside.

At time T03 to time T05, the imaging data amplified by the circuit 30 is rewritten in the capacitive element 54a [0] and the capacitive element 54b [0]. As a result, the imaging data can be continuously held in the capacitance element 54a [0] and the capacitance element 54b [0] even after the imaging data is read out from the circuit 30.

At time T05, the transistor 22, the transistor 25, the transistor 53a [0], and the transistor 53b [0] are turned off by setting the potential of the wiring 28 (Rsw) and the wiring 55 [0] (WL [0]) to the L level. To do. Further, at time T06, the circuit 30 is deactivated by setting the potentials of the wiring 35 (VLL) and the wiring 36 (VHH) to "VDD / 2".

At time T11 to time T16, the imaging data held by the capacitive element 54a [1] and the capacitive element 54b [1] are read out. Transistor 53a [1] and transistor 53b [1] are turned on by setting the potential of wiring 55 [1] (WL [1]) to H level at time T12, and wiring 55 [1] (WL [1]) is turned on at time T15. ]), The transistor 53a [1] and the transistor 53b [1] are turned off by setting the potential to the L level. Other operations are the same as the operations at time T01 to time T06.

In this way, the imaging data is read out in order from the capacitive element 54a [0] and the capacitive element 54b [0] to the capacitive element 54a [n-1] and the capacitive element 54b [n-1]. At time T21 to time T26, the imaging data held in the capacitive element 54a [n-1] and the capacitive element 54b [n-1] are read out. Transistor 53a [n-1] and transistor 53b [n-1] are turned on by setting the potential of wiring 55 [n-1] (WL [n-1]) to H level at time T22, and wiring is performed at time T25. The transistor 53a [n-1] and the transistor 53b [n-1] are turned off by setting the potential of 55 [n-1] (WL [n-1]) to the L level. Other operations are the same as the operations at time T01 to time T06.

In the write operation shown in FIG. 5 and the read operation shown in FIG. 6, the capacitive element is while the transistors 53a [0] to 53a [n-1] and the transistors 53b [0] to 53b [n-1] are off. The imaging data written in the capacitance elements 54a [0] to the capacitance elements 54a [n-1] and the capacitance elements 54b [0] to the capacitance elements 54b [n-1] are held without consuming power. Therefore, it is possible to provide the image pickup device 10 with low power consumption.

<Potential generation circuit>
FIG. 7A shows a configuration example of the circuit 70 for generating the potential applied to the wiring 36 (VHH) and the potential applied to the wiring 35 (VLL). The circuit 70 includes a transistor 71, a transistor 72, a transistor 73, and a transistor 74. The transistor 71 and the transistor 72 are p-ch type transistors, and the transistor 73 and the transistor 74 are n-ch type transistors.

One of the source or drain of the transistor 71 is electrically connected to one of the source or drain of the transistor 72 and the wiring 36 (VHH). Further, the other side of the source or drain of the transistor 71 is electrically connected to the wiring 76 (H). Further, the other side of the source or drain of the transistor 72 is electrically connected to one of the source or drain of the transistor 73 and the wiring 78 (VDD / 2). Further, the other side of the source or drain of the transistor 73 is electrically connected to one of the source or drain of the transistor 74 and the wiring 35 (VLL). Further, the other side of the source or drain of the transistor 74 is electrically connected to the wiring 77 (L).

For example, an H level potential can be applied to the wiring 76 (H). Further, for example, an L level potential can be applied to the wiring 77 (L). Further, for example, the potential VDD / 2 can be applied to the wiring 78 (VDD / 2).

Further, the gates of the transistor 72 and the transistor 74 are electrically connected to the wiring 75a (SOa). Further, the gates of the transistor 71 and the transistor 73 are electrically connected to the wiring 75b (SOb).

When the H level potential is applied to the wiring 75a (SOa), the L level potential can be applied to the wiring 75b (SOb). In this case, the potential of the wiring 36 (VHH) becomes the potential of the wiring 76 (H) (for example, H level), and the potential of the wiring 35 (VLL) becomes the potential of the wiring 77 (L) (for example, L level). That is, the circuit 30 becomes active. Further, when the L level potential is applied to the wiring 75a (SOa), the H level potential can be applied to the wiring 75b (SOb). In this case, the potentials of the wiring 36 (VHH) and the wiring 35 (VLL) are the potentials of the wiring 78 (VDD / 2). That is, the circuit 30 becomes inactive.

In the read operation shown in FIG. 6, the potentials applied to the wiring 36 (VHH) and the wiring 35 (VLL) are changed in conjunction with the transfer of the imaging data between the circuit 30 and the circuit 50. It is preferable to change the potentials applied to the wiring 36 (VHH) and the wiring 35 (VLL) in conjunction with the timing when the potential of the selected wiring 55 (WL) becomes the H level and the timing when the potential becomes the L level. .. As a result, the circuit 30 can be inactive for as long as possible without slowing down the response speed of the imaging device 10. Therefore, it is possible to provide the image pickup device 10 with low power consumption.

Also in the writing operation shown in FIG. 5, the potentials applied to the wiring 36 (VHH) and the wiring 35 (VLL) can be changed in conjunction with the transfer of the imaging data between the circuit 30 and the circuit 50. .. As a result, the power consumption of the image pickup apparatus 10 can be further reduced.

FIG. 7B is a timing chart showing an operation example of the circuit 70. The timing chart shows the potentials of wiring 55 (WL), wiring 75a (SOa), wiring 75b (SOb), wiring 36 (VHH) and wiring 35 (VLL). Here, the potential of the wiring 55 (WL) is H level, which means that one of the wirings 55 [0] (WL [0]) to 55 [n-1] (WL [n-1]). It shows that the H level potential was applied to. Further, the potential of the wiring 55 (WL) is L level, and the L level potential is applied to all of the wiring 55 [0] (WL [0]) to the wiring 55 [n-1] (WL [n-1]). Indicates that it was done.

The timing when the potential of the wiring 75a (SOa) becomes the H level is delayed by T _d1 from the timing when the potential of the wiring 55 (WL) becomes the H level, and the timing when the potential of the wiring 75a (SOa) becomes the L level is , The time T _{d2 is} delayed from the timing when the potential of the wiring 55 (WL) reaches the L level. The time T _d1 may be the same as or different from the time T _d2 .

By operating the circuit 70 as described above, the circuit 30 can be immediately activated after any one of the n circuits 51 of the circuit 50 is in the selected state. Further, the circuit 30 can be immediately deactivated after deselecting all the n circuits 51 of the circuit 50.

This embodiment is not limited to the imaging device, and can be applied to other semiconductor devices. For example, the present embodiment can be applied to a storage device.

In the present embodiment, one aspect of the present invention has been described. Alternatively, in another embodiment, one aspect of the present invention will be described. However, one aspect of the present invention is not limited to these. That is, since various aspects of the invention are described in this embodiment and other embodiments, one aspect of the present invention is not limited to a specific aspect. For example, as one aspect of the present invention, an example is shown in which a transistor channel forming region, a source / drain region, and the like have an oxide semiconductor, but one aspect of the present invention is not limited to this. In some cases, or depending on the circumstances, the various transistors in one aspect of the invention, the transistor channel forming regions, the transistor source / drain regions, and the like may have different semiconductors. In some cases, or depending on the circumstances, the various transistors in one aspect of the invention, the channel formation region of the transistor, the source / drain region of the transistor, etc., are, for example, silicon, germanium, silicon germanium, silicon carbide, gallium arsenide. It may have at least one such as arsenide, aluminum gallium arsenide, indium phosphorus, gallium nitride, or an organic semiconductor. Or, for example, in some cases, or depending on the circumstances, the various transistors in one embodiment of the present invention, the channel formation region of the transistor, the source / drain region of the transistor, etc. may not have an oxide semiconductor. Good.

This embodiment can be implemented in combination with the configurations described in the other embodiments as appropriate.

(Embodiment 2)
In the present embodiment, modifications of the circuit 20, the circuit 40, and the circuit 50 shown in the first embodiment will be described with reference to the drawings.

<Write / read selection switch>
FIG. 8A shows a configuration in which the transistors 21 to 26 included in the circuit 20 shown in FIG. 2 are of the p-ch type. If necessary, the operation can be referred to with reference to FIGS. 5 and 6 by reversing the magnitude relation of the potentials applied to the wiring 27 (Wsw), the wiring 28 (Rsw), and the wiring 29. Of the transistors 21 to 26, some of the transistors may be replaced with the p-ch type.

FIG. 8B is a configuration in which the transistor 23 and the transistor 26 are removed from the circuit 20 shown in FIG. With such a configuration, the number of transistors included in the image pickup apparatus 10 can be reduced, so that the image pickup apparatus 10 can be miniaturized. On the other hand, the circuit 20 shown in FIG. 2 has a smaller load on the wiring 63a (LBL) and the wiring 63b (LBLB) during the reading operation than the circuit 20 shown in FIG. 8B, so that the reading speed is increased. be able to.

<Local precharge circuit>
FIG. 9A shows a configuration in which the transistors 41 to 43 included in the circuit 40 shown in FIG. 2 are of the p-ch type. If necessary, the operation can be referred to with reference to FIGS. 5 and 6 by reversing the magnitude relationship of the potentials applied to the wiring 44 (PC) and the wiring 45 (VPC). Of the transistors 41 to 43, some of the transistors may be replaced with the p-ch type.

FIG. 9B shows a configuration in which the transistor 42 and the transistor 43 are removed from the circuit 40 shown in FIG. That is, the circuit 40 can have a simple circuit equalizer configuration of a single transistor 41. The wiring 63a (LBL) and the wiring 63b (LBLB) are not precharged.

FIG. 9C shows a configuration in which the transistor 41 is removed from the circuit 40 shown in FIG. That is, the transistor 41 that functions as an equalizer may be omitted.

By configuring the circuit 40 as shown in FIG. 9B or FIG. 9C, the number of transistors included in the image pickup apparatus 10 can be reduced. As a result, the imaging device 10 can be miniaturized.

<Long-term memory>
In the circuit 50 shown in FIG. 2, the circuit 51 is composed of the circuit 52a and the circuit 52b, but as shown in FIG. 10, the circuit 51 has only one circuit having the configuration shown in the circuit 52a and the circuit 52b. May be good.

The circuit 51 includes a transistor 53 and a capacitive element 54. That is, when the circuit 50 has m circuits 51 (m is an integer of 2 or more), the circuit 50 has m transistors 53 and m capacitance elements 54, respectively. Although the transistor 53 is an n-ch type transistor in FIG. 10, it may be a p-ch type transistor.

One of the source or drain of one transistor 53 is electrically connected to one terminal of one capacitive element 54. Further, the other of the source or drain of the m transistors 53 is electrically connected to one wiring 63a (LBL) or wiring 63b (LBLB) having a function as a local bit line. Further, the other terminal of the m capacitance elements 54 is electrically connected to one wiring 56.

Further, the gate of one transistor 53 is electrically connected to one wiring 55 (WL). That is, m wires 55 (WL) are provided.

When the number of transistors and capacitive elements of the circuit 50 is equal, the circuit 50 having the configuration shown in FIG. 10 can hold imaging data having twice the capacitance of the circuit 50 having the configuration shown in FIG. As a result, the number of transistors included in the image pickup apparatus 10 can be reduced, so that the image pickup apparatus 10 can be miniaturized. On the other hand, since the circuit 50 having the configuration shown in FIG. 2 can hold complementary data as described above, the circuit 30 can amplify the imaging data when reading the imaging data. As a result, when the circuit 50 has the configuration shown in FIG. 2, the reading speed can be increased as compared with the case where the circuit 50 has the configuration shown in FIG.

11 (A) and 11 (B) show a configuration in which a back gate is provided in the transistor 53a and the transistor 53b included in the circuit 50 shown in FIG. FIG. 11A shows a configuration in which a constant potential is applied to the back gate, and the threshold voltage can be controlled. Further, FIG. 11B has a configuration in which the same potential as that of the front gate is applied to the back gate, and the on-current can be increased.

Further, a back gate may be provided in the transistors included in the circuit 20, the circuit 30, and the circuit 40. Further, a back gate may be provided in the transistor included in the circuit 70.

FIG. 12 shows a configuration in which the transistor 21, the transistor 22, the transistor 24, the transistor 25, the transistor 41, the transistor 42, the transistor 43, the transistor 53a, and the transistor 53b are replaced with switches in the circuit 16A having the configuration shown in FIG. The above-mentioned transistor is not limited to the transistor as long as it has a switching function, and any element can be used. A part of the transistor 21, the transistor 22, the transistor 24, the transistor 25, the transistor 41, the transistor 42, the transistor 43, the transistor 53a and the transistor 53b may be a transistor, and the rest may be another element having a switching function. Further, also in the circuit 16B, all or a part of the above transistors may be replaced with other elements having a switching function.

The configurations shown in FIGS. 2 and 8 to 12 can be arbitrarily combined.

Further, the present embodiment is not limited to the imaging device, and can be applied to other semiconductor devices. For example, the present embodiment can be applied to a storage device.

This embodiment can be implemented in combination with the configurations described in the other embodiments as appropriate.

(Embodiment 3)
In the present embodiment, a detailed system configuration example of the circuit 16 and the circuit 17 shown in FIG. 1 will be described with reference to the drawings.

As in the first embodiment, it is assumed that the circuit 50 included in one circuit 16A or circuit 16B has a function of holding n-bit imaging data.

FIG. 13 is a block diagram showing a system configuration example of the circuit 16A, the circuit 16B, the circuit 17A, and the circuit 17B shown in FIG. The image pickup apparatus 10 has a circuit 16A, a circuit 16B, a circuit 17A, and a circuit 17B for each j bank (j is a natural number).

Note that j can take values such as 4, 8 and 16.

The bank represents a set of a circuit 16A, a circuit 16B, a circuit 17A, and a circuit 17B as shown in the area 80.

Since one circuit 17A and one circuit 17B are provided for each bank, the image pickup apparatus 10 has j circuits 17A and one circuit 17B each. One circuit 17A is electrically connected to all the circuits 16A for one bank by n wirings 55 (WL). Further, one circuit 17B is electrically connected to all the circuits 16B for one bank by n wirings 55 (WL).

Further, the circuit 16A and the circuit 16B are electrically connected to each other by wiring 61a (WBL), wiring 61b (WBLB), wiring 62a (RBL) and wiring 62b (RBLB) for each row. Further, the j circuits 17A are electrically connected to each other by one wiring 81A (Wsw_enA) and one wiring 82A (Rsw_enA). Further, the j circuits 17B are electrically connected to each other by one wiring 81B (Wsw_enB) and one wiring 82B (Rsw_enB).

Further, one wiring 83 (BS), one wiring 84 (BS +), and n wirings 85 (BW) are electrically connected to one circuit 17A. Further, one wiring 83 (BS), one wiring 84 (BS +) and n wirings 85 (BW) are electrically connected to one circuit 17B.

The circuit 16A, the circuit 16B, the circuit 17A, the circuit 17B, the wiring 83 (BS) and the wiring 84 (BS +) for the j bank are distinguished by using a code such as _0, _1 or _j-1. Further, n wirings 85 (BW) are distinguished by using reference numerals such as [0], [1], and [n-1].

Since the circuit 16A and the circuit 17A for one bank are electrically connected by n wirings 55 (WL), a total of n × j wirings 55 (WL) are provided. These are distinguished by using symbols such as _0 [0], _0 [n-1], _j-1 [0], and _j-1 [n-1]. The wiring 55 (WL) that electrically connects the circuit 16B and the circuit 17B is also distinguished by using the same reference numerals.

The wiring 81A (Wsw_enA) has a function of controlling the operation of writing the imaging data to the circuit 30 of the circuit 16A, and the wiring 81B (Wsw_enB) has a function of controlling the operation of writing the imaging data to the circuit 30 of the circuit 16B. .. Further, the wiring 82A (Rsw_enA) controls the reading operation of the imaging data to the circuit 30 of the circuit 16A, and the wiring 82B (Rsw_enB) controls the reading operation of the imaging data to the circuit 30 of the circuit 16B. Has. For example, when the imaging data is written in the circuit 30 of the circuit 16A, the potential of the wiring 81A (Wsw_enA) is set to H level, and the potential of the wiring 82A (Rsw_enA) is set to L level. When reading the imaging data transferred to the circuit 30 of the circuit 16A, the potential of the wiring 81A (Wsw_enA) is set to the L level, and the potential of the wiring 82A (Rsw_enA) is set to the H level.

The wiring 81B (Wsw_enB) and the wiring 82B (Rsw_enB) also control the writing operation and the reading operation of the imaging data to the circuit 30 of the circuit 16B by the same logic as the wiring 81A (Wsw_enA) and the wiring 82A (Rsw_enA). Has the function of wiring.

The wiring 83 (BS) has a function of controlling the gate potential of the transistor of the circuit 20 included in the circuit 16A or the circuit 16B.

For example, by setting the potential of the wiring 83_0 (BS_0) to the H level and further setting the potential of the wiring 81A (Wsw_enA) to the H level, the potential of the wiring 27 (Wsw) included in the circuit 16A_0 becomes the H level. As a result, the transistor 21 and the transistor 24 included in the circuit 16A_0 are turned on, and the circuit 16A_0 can perform the writing operation. Further, for example, by setting the potential of the wiring 83_0 (BS_0) to the H level and further setting the potential of the wiring 82A (Rsw_enA) to the H level, the potential of the wiring 28 (Rsw) included in the circuit 16A_0 becomes the H level. As a result, the transistor 22 and the transistor 25 included in the circuit 16A_0 are turned on, and the circuit 16A_0 can perform the read operation.

Further, the wiring 84 (BS +) and the wiring 85 (BW) have a function of selecting the wiring 55 (WL). The wiring 84 (BS +) selects a bank, and the wiring 85 (BW) selects one of the wirings 55 (WL) in the bank selected by the wiring 84 (BS +).

For example, by setting the potentials of the wiring 84_0 (BS + _0) and the wiring 85 [0] (BW [0]) to the H level, the potential of the wiring 55_0 [0] (WL_0 [0]) becomes the H level. Further, for example, by setting the potential of the wiring 84_j-1 (BS + _j-1) and the wiring 85 [n-1] (BW [n-1]) to the H level, the wiring 55_j-1 [n-1] (WL_j-). The potential of 1 [n-1]) becomes the H level.

The logic of wiring 81A (Wsw_enA), wiring 81B (Wsw_enB), wiring 82A (Rsw_enA), wiring 82B (Rsw_enB), wiring 83 (BS), wiring 84 (BS +), and wiring 85 (BW) is required. Or can be reversed as appropriate.

<Operation example>
Next, the operation of the system shown in FIG. 13 will be described in detail using the timing charts shown in FIGS. 14 and 15.

In general, a circuit having a configuration like the circuit 51 has a slow write speed and a read speed, and a latch circuit like the circuit 30 has a high write speed and a read speed. Therefore, after the writing of the imaging data to the circuit 51 of the circuit 16A is completed, when the writing of the imaging data to the circuit 30 and the circuit 51 of the circuit 16A of the next bank is started, the writing speed of the circuit 51 becomes rate-determining. .. Further, when the reading of the imaging data from the circuit 30 of the circuit 16A is completed and the reading of the imaging data from the circuit 51 of the circuit 16A of the next bank is started, the reading speed of the circuit 51 becomes rate-determining. As described above, the entire system shown in FIG. 13 is written by writing the imaging data to the circuit 51 of the circuit 16A and writing the imaging data to the circuits 30 and 51 of the circuit 16A of the next bank in parallel. The writing speed as can be increased. Further, by reading the imaging data from the circuit 51 of the circuit 16A in parallel with reading the imaging data from the circuit 30 of the circuit 16A of the previous bank, the reading speed of the entire system shown in FIG. 13 Can be enhanced.

Regarding the timing charts shown in FIGS. 14 and 15, wiring 81A (Wsw_enA), wiring 82A (Rsw_enA), wiring 83_0 (BS_0), wiring 84_0 (BS + _0), wiring 83_1 (BS_1), wiring 84_1 (BS + _1), wiring 83_j- 1 (BS_j-1), wiring 84_j-1 (BS + _j-1), wiring 85 [0] (BW [0]), wiring 85 [n-1] (BW [n-1]), wiring 55_0 [0] (WL_0 [0]) and wiring 55_j-1 [n-1] (WL_j-1 [n-1]) potentials are shown.

The circuit 20, the circuit 30, the circuit 40, and the circuit 50 are provided one by one in one circuit 16A, and one by one in each circuit 16B. Further, one wiring 35 (VLL), one wiring 36 (VHH) and one wiring 44 (PC) are provided in the circuit 16A for one bank, and one each in the circuit 16B for one bank. There is. Further, one wiring 63a (LBL) and one wiring 63b (LBLB) are provided in one circuit 16A, and one wiring is provided in each circuit 16B. From the above, when the circuit 16A and the circuit 16B are provided for j banks, the circuit 20, the circuit 30, the circuit 40, the circuit 50, the wiring 35 (VLL), the wiring 36 (VHH), the wiring 44 (PC), and the wiring 63a ( LBL) and wiring 63b (LBLB) are also provided for j banks, respectively. Circuit 20, circuit 30, circuit 40, circuit 50, wiring 35 (VLL), wiring 36 (VHH), wiring 44 (PC), wiring 63a (LBL) and wiring 63b (LBLB) for j banks, circuit 16A and Similar to the circuit 16B, a code such as _0, _1, _j-1 is used for distinction.

FIG. 14 is a timing chart showing the potential of the wiring electrically connected to the circuit 17A when the circuit 16A shown in FIG. 13 performs a writing operation. In T01 to T06, the imaging data is written in the circuit 51_0 [0], the circuit 51_1 [0], and the circuit 51_2 [0].

The same number of wirings 55 (WL) and circuits 51 are provided. That is, when n × j wirings 55 (WL) are provided, n × j circuits 51 are also provided. The n × j circuits 51 are connected with reference numerals such as _0 [0], _0 [n-1], _j-1 [0], and _j-1 [n-1] as in the wiring 55 (WL). Distinguish.

At time T01, the potentials of wiring 84_0 (BS + _0) and wiring 85 [0] (BW [0]) are defined as H levels. As a result, the potential of the wiring 55_0 [0] (WL_0 [0]) becomes the H level. Further, although not shown in FIG. 14, the circuit 30_0 is activated by setting the potential of the wiring 35_0 (VLL_0) to the L level and the potential of the wiring 36_0 (VHH_0) to the H level.

Further, at time T01, the potential of wiring 83_0 (BS_0) is set to H level, and at time T02, the potential of wiring 81A (Wsw_enA) is set to H level. As a result, the transistor 21 and the transistor 24 included in the circuit 20_0 are turned on, the imaging data is written from the wiring 61a (WBL) and the wiring 61b (WBLB) to the circuit 30_0, and the imaging data is transferred to the circuit 51_0 [0]. Writing is started.

At time T03, the potentials of the wiring 81A (Wsw_enA) and the wiring 83_0 (BS_0) are set to the L level. Only when the potentials of the wiring 81A (Wsw_enA) and the wiring 83_0 (BS_0) are at H level, the transistor 21 and the transistor 24 of the circuit 20_0 are turned on, so that the transistor 21 and the transistor 24 of the circuit 20_0 are turned off. .. As a result, the writing of the imaging data from the wiring 61a (WBL) and the wiring 61b (WBLB) to the circuit 30_0 is completed.

At time T03, the potentials of the wiring 84_0 (BS + _0) and the wiring 85 [0] (BW [0]) remain at the H level. Therefore, the imaging data written in the circuit 30_0 at the time T02 to the time T03 is continuously written in the circuit 51_0 [0].

Further, at time T03, the potential of the wiring 84_1 (BS + _1) is set to the H level. Due to this operation and the potential of the wiring 85 [0] (BW [0]) being at the H level, the potential of the wiring 55_1 [0] (WL_1 [0]) is at the H level. The potential of the wiring 55_1 [0] (WL_1 [0]) is not shown in FIG.

Further, although not shown in FIG. 14, at time T03, the circuit 30_1 is activated by setting the potential of the wiring 35_1 (VLL_1) to the L level and the potential of the wiring 36_1 (VHH_1) to the H level.

Further, at time T03, the potential of the wiring 83_1 (BS_1) is set to the H level, and at time T04, the potential of the wiring 81A (Wsw_enA) is set to the H level. As a result, the transistor 21 and the transistor 24 included in the circuit 20_1 are turned on, the imaging data is written from the wiring 61a (WBL) and the wiring 61b (WBLB) to the circuit 30_1, and the imaging data is transferred to the circuit 51_1 [0]. Writing is started.

At time T05, the potentials of the wiring 81A (Wsw_enA) and the wiring 83_1 (BS_1) are set to the L level. Only when the potentials of the wiring 81A (Wsw_enA) and the wiring 83_1 (BS_1) are at H level, the transistor 21 and the transistor 24 of the circuit 20_1 are turned on, so that the transistor 21 and the transistor 24 of the circuit 20_1 are turned off. .. As a result, the writing of the imaging data from the wiring 61a (WBL) and the wiring 61b (WBLB) to the circuit 30_1 is completed.

Further, at time T05, the potential of the wiring 84_0 (BS + _0) is set to the L level. As a result, the potential of the wiring 55_0 [0] (WL_0 [0]) becomes the L level, and the writing of the imaging data to the circuit 51_0 [0] is completed. Further, after the potential of the wiring 55_0 [0] (WL_0 [0]) is set to the L level, the potential of the wiring 35_0 (VLL_0) and the wiring 36_0 (VHH_0) is set to "VDD / 2", so that the circuit 30_0 is not set. Since it becomes active, power consumption can be reduced.

At time T05, the potentials of the wiring 84_1 (BS + _1) and the wiring 85 [0] (BW [0]) remain at the H level. Therefore, the imaging data written in the circuit 30_1 at the time T04 to the time T05 is continuously written in the circuit 51-1 [0].

Further, at time T05, the potential of the wiring 84_2 (BS + __) is set to the H level. Due to this operation and the potential of the wiring 85 [0] (BW [0]) being at the H level, the potential of the wiring 55_2 [0] (WL_2 [0]) is at the H level. The potentials of the wiring 84_2 (BS + _2) and the wiring 55_2 [0] (WL_2 [0]) are not shown in FIG.

Further, although not shown in FIG. 14, at time T05, the circuit 30_2 is activated by setting the potential of the wiring 35_2 (VLL_2) to the L level and the potential of the wiring 36_2 (VHH_2) to the H level.

Further, at the time T05, the potential of the wiring 83_2 (BS_2) is set to the H level, and at the time T06, the potential of the wiring 81A (Wsw_enA) is set to the H level. As a result, the circuit 20_2 becomes active, the imaging data is written from the wiring 61a (WBL) and the wiring 61b (WBLB) to the circuit 30_2, and the writing of the imaging data to the circuit 51_2 [0] is started.

At time T11 to time T16, imaging data is written in circuit 51_j-2 [0], circuit 51_j-1 [0], and circuit 51_0 [1]. Further, at time T21 to time T25, the imaging data is written in the circuit 51_j-2 [n-1] and the circuit 51_j-1 [n-1]. As described above, in the operation shown in FIG. 14, the imaging data is written to the circuits 51_0 [0] to 51_j-1 [0], and then the circuits 51_0 [1] to 51_j-1 [1] are written. The imaging data is written to the circuit 51_0 [n-1] to the circuit 51_j-1 [n-1] in order. The above is the writing operation in the circuit 16A shown in FIG.

In FIG. 14, the imaging data is written from the circuit 30 to the circuit 51 even after the writing of the imaging data to the circuit 30 is completed. Further, at this time, the writing of the imaging data to the circuits 30 and 51 of the circuits 16A of the other banks is also performed in parallel. For example, at time T04 to time T05, the imaging data is not written to the circuit 30_0, but the imaging data is written from the circuit 30_0 to the circuit 51_0 [0], and is written to the circuit 30_1 and the circuit 51_1 in parallel. The imaging data of the above is also written. That is, the circuits 16A of the plurality of banks perform the writing operation in parallel.

Generally, a circuit having a configuration like the circuit 51 has a slow writing speed, and a latch circuit like the circuit 30 has a high writing speed. Therefore, after the writing of the imaging data to the circuit 51 of the circuit 16A is completed, when the writing of the imaging data to the circuit 30 and the circuit 51 of the circuit 16A of the next bank is started, the writing speed of the circuit 51 becomes rate-determining. .. Therefore, as shown in FIG. 14, the imaging data is written to the circuit 51 of the circuit 16A and the imaging data is written to the circuits 30 and 51 of the circuit 16A of the next bank in parallel. , The writing speed of the entire system shown in FIG. 13 can be increased.

In FIG. 14, the imaging data was written to the circuit 51 of the circuit 16A until the writing of the imaging data to the circuit 30 of the circuit 16A of the next bank was completed, but the circuit 16A of the same bank The imaging data can be written to the circuit 51 for an arbitrary time until the next imaging data is written to the circuit 30 having the circuit 30. For example, the writing of the imaging data to the circuit 51_0 [0] may be continued until, for example, the writing of the imaging data to the circuit 30_2 is completed, or the writing of the imaging data to the circuit 30_j-1 is completed. May be good. Further, for example, the writing of the imaging data to the circuit 51_1 [1] may be continued until the writing of the imaging data to the circuit 30_3 is completed, or may be continued until the writing of the imaging data to the circuit 30_1 is completed. Good.

For example, after the writing of the imaging data to the circuit 30_1 is completed and before the writing of the imaging data to the circuit 30_1 is started, the writing of the imaging data to the circuit 51_0 [0] may be completed. For example, the writing of the imaging data to the circuit 51_0 [0] may be completed at the same time as the writing of the imaging data to the circuit 30_0 is completed.

FIG. 15 is a timing chart showing the potential of the wiring electrically connected to the circuit 17A when the circuit 16A shown in FIG. 13 performs a read operation. In T01 to T06, the imaging data held in the circuit 51_0 [0] and the circuit 51_1 [0] are read out to the outside.

At time T01, the potentials of wiring 84_0 (BS + _0) and wiring 85 [0] (BW [0]) are defined as H levels. As a result, the potential of the wiring 55_0 [0] (WL_0 [0]) becomes the H level.

Although not shown in FIG. 15, before the potential of the wiring 84_0 (BS + _0) is set to the H level at time T01, the potential of the wiring 44_0 (PC_0) is set to the H level and then the potential of the wiring 44_0 (PC_0) is set to L. By setting the level, the wiring 63a_0 (LBL_0) and the wiring 63b_0 (LBLB_0) can be precharged. As a result, the imaging data held in the circuit 51_0 [0] can be correctly transferred to the circuit 30_0.

Further, after the potential of the wiring 55_0 [0] (WL_0 [0]) reaches the H level at time T01, although not shown in FIG. 15, the potential of the wiring 35_0 (VLL_0) is set to the L level and the potential of the wiring 36_0 (VHH_0). ) Is the H level. As a result, the circuit 30_0 becomes active, and the imaging data held in the circuit 51_0 [0] is transferred to the circuit 30_0. Then, the imaging data transferred to the circuit 30_0 is amplified. Further, since the potential of the wiring 55_0 [0] (WL_0 [0]) is H level, the amplified imaging data is rewritten in the circuit 51_0 [0].

At time T02, the potential of wiring 83_0 (BS_0) is defined as the H level. Further, at time T03, the potential of the wiring 82A (Rsw_enA) is set to the H level. As a result, the transistor 22 and the transistor 25 included in the circuit 20_0 are turned on, and the imaging data transferred from the circuit 51_0 [0] to the circuit 30_0 is read out via the circuit 20_0.

Further, at time T03, the potential of the wiring 84_1 (BS + _1) is set to the H level. Due to this operation and the potential of the wiring 85 [0] (BW [0]) being at the H level, the potential of the wiring 55_1 [0] (WL_1 [0]) is at the H level. The potential of the wiring 55_1 [0] (WL_1 [0]) is not shown in FIG.

Before the potential of the wiring 84_1 (BS + _1) is set to the H level at time T03, although not shown in FIG. 15, the potential of the wiring 44_1 (PC_1) is set to the H level and then the potential of the wiring 44_1 (PC_1) is set to L. By setting the level, the wiring 63a_1 (LBL_1) and the wiring 63b_1 (LBLB_1) can be precharged. As a result, the imaging data held in the circuit 51_1 [0] can be correctly transferred to the circuit 30_1.

Further, after the potential of the wiring 55_1 [0] (WL_1 [0]) reaches the H level at time T03, although not shown in FIG. 15, the potential of the wiring 35_1 (VLL_1) is set to the L level and the potential of the wiring 36_1 (VHH_1) is set to the L level. ) Is the H level. As a result, the circuit 30_1 becomes active, and the imaging data held in the circuit 51_1 [0] is transferred to the circuit 30_1. Then, the imaging data transferred to the circuit 30_1 is amplified. Further, since the potential of the wiring 55_1 [0] (WL_1 [0]) is at the H level, the amplified imaging data is rewritten in the circuit 51-1 [0].

At time T04, the potentials of the wiring 82A (Rsw_enA) and the wiring 83_0 (BS_0) are set to the L level. Since the circuit 20_0 is active only when the potentials of the wiring 82A (Rsw_enA) and the wiring 83_0 (BS_0) are both H level, the transistor 22 and the transistor 25 of the circuit 20_0 are turned off. As a result, the reading of the imaging data from the circuit 30_0 is completed.

Further, at time T04, by setting the potential of the wiring 84_0 (BS + _0) to the L level, the potential of the wiring 55_0 [0] (WL_0 [0]) becomes the L level. As a result, the rewriting from the circuit 30_0 to the circuit 51_0 [0] is completed.

After the potential of the wiring 55_0 [0] (WL_0 [0]) reaches the L level at time T04, the potential of the wiring 35_0 (VLL_0) and the potential of the wiring 36_0 (VHH_0) are set to "VDD / 2", respectively. .. As a result, the circuit 30_0 becomes inactive, so that power consumption can be reduced.

Further, at time T04, the potential of wiring 83_1 (BS_1) is set to H level, and at time T05, the potential of wiring 82A (Rsw_enA) is set to H level. As a result, the transistor 22 and the transistor 25 included in the circuit 20_1 are turned on, and the imaging data transferred from the circuit 51_1 [0] to the circuit 30_1 is read out via the circuit 20_1.

Further, at time T05, the potential of the wiring 84_2 (BS + __) is set to the H level. Due to this operation and the potential of the wiring 85 [0] (BW [0]) being at the H level, the potential of the wiring 55_2 [0] (WL_2 [0]) is at the H level. The potentials of the wiring 84_2 (BS + _2) and the wiring 55_2 [0] (WL_2 [0]) are not shown in FIG.

Although not shown in FIG. 15, before the potential of the wiring 84_2 (BS + _2) is set to the H level at time T05, the potential of the wiring 44_2 (PC_2) is set to the H level and then the potential of the wiring 44_2 (PC_2) is set to L. By setting the level, the wiring 63a_2 (LBL_2) and the wiring 63b_2 (LBLB_2) can be precharged. As a result, the imaging data held in the circuit 51-2 [0] can be correctly transferred to the circuit 30_2.

Further, after the potential of the wiring 55_2 [0] (WL_2 [0]) reaches the H level at time T05, although not shown in FIG. 15, the potential of the wiring 35_2 (VLL_2) is set to the L level and the potential of the wiring 36_2 (VHH_2). ) Is the H level. As a result, the circuit 30_2 becomes active, and the imaging data held in the circuit 51-2 [0] is transferred to the circuit 30_2. Then, the imaging data transferred to the circuit 30_2 is amplified. Further, since the potential of the wiring 55_2 [0] (WL_2 [0]) is H level, the amplified imaging data is rewritten in the circuit 51-2 [0].

At time T06, the potentials of the wiring 82A (Rsw_enA) and the wiring 83_1 (BS_1) are set to the L level. Since the circuit 20_1 is active only when the potentials of the wiring 82A (Rsw_enA) and the wiring 83_1 (BS_1) are both H level, the transistor 22 and the transistor 25 of the circuit 20_1 are turned off. As a result, the reading of the imaging data from the circuit 30_1 is completed.

Further, at time T06, by setting the potential of the wiring 84_1 (BS + _1) to the L level, the potential of the wiring 55_1 [0] (WL_1 [0]) becomes the L level. As a result, the rewriting from the circuit 30_1 to the circuit 51_1 [0] is completed.

After the potential of the wiring 55_1 [0] (WL_1 [0]) reaches the L level at time T06, the potential of the wiring 35_1 (VLL_1) and the potential of the wiring 36_1 (VHH_1) are set to "VDD / 2", respectively. .. As a result, the circuit 30_1 becomes inactive, so that power consumption can be reduced.

At time T11 to time T16, the imaging data held in the circuit 51_j-2 [0], the circuit 51_j-1 [0], and the circuit 51_0 [1] are read out to the outside. Further, at time T21 to time T24, the imaging data held in the circuit 51_j-2 [n-1] and the circuit 51_j-1 [n-1] are read out to the outside.

As described above, in the operation shown in FIG. 15, the imaging data is read from the circuit 51_0 [0] to the circuit 51_j-1 [0], and then the imaging data is read from the circuit 51_0 [1] to the circuit 51_j-1 [1]. Is read out, and the imaging data is read out in order from the circuit 51_0 [n-1] to the circuit 51_j-1 [n-1]. The above is the read operation in the circuit 16A shown in FIG.

In FIG. 15, while the circuit 30 included in the circuit 16A is reading out the imaging data, the circuit 51 included in the circuit 16A in another bank reads out the imaging data. For example, at time T03 to time T04, the reading of the imaging data transferred from the circuit 51_0 [0] to the circuit 30_1 and the transfer of the imaging data held in the circuit 51_1 [0] to the circuit 30_1 are performed in parallel. .. That is, the circuits 16A of the plurality of banks perform the read operation in parallel.

Generally, a circuit having a configuration like the circuit 51 has a slow read speed, and a latch circuit like the circuit 30 has a high read speed. Therefore, when the reading of the imaging data from the circuit 30 of the circuit 16A is completed and the reading of the imaging data from the circuit 51 of the circuit 16A of the next bank is started, the reading speed of the circuit 51 becomes rate-determining. Therefore, as shown in FIG. 15, by reading the imaging data from the circuit 51 of the circuit 16A in parallel with reading the imaging data from the circuit 30 of the circuit 16A of the previous bank, FIG. 13 The read speed of the entire system shown in (1) can be increased.

In FIG. 15, the reading of the imaging data from the circuit 51 of the circuit 16A was performed after the reading of the imaging data from the circuit 30 of the circuit 16A of the previous bank was started, but the circuit 16A of the same bank The circuit 30 of the circuit 30 can read the imaged data from the circuit 51 at an arbitrary time after the previous imaged data is read out. For example, the reading of the imaging data from the circuit 51_j-1 [0] may be started at the same time as the reading of the imaging data from the circuit 30_j-3, or at the same time as the reading of the imaging data from the circuit 30_0. May be good. Further, for example, the reading of the imaging data from the circuit 51_1 [1] may be started at the same time as the reading of the imaging data from the circuit 30_j-1, or may be started at the same time as the reading of the imaging data from the circuit 30_2. Good.

Further, for example, reading of the imaging data from the circuit 51_1 [0] may be started after reading the imaging data from the circuit 30_1. For example, the reading of the imaging data from the circuit 51_1 [0] and the reading of the imaging data from the circuit 30_1 may be started at the same time.

Regarding the writing operation shown in FIG. 14 and the reading operation shown in FIG. 15, all the potentials of the wiring 55_k [0] (WL_k [0]) to the wiring 55_k [n-1] (WL_k [n-1]) are L level. During this period, the potentials of the wiring 35_k (VLL_k) and the wiring 36_k (VHH_k) can be set to "VDD / 2" (k is an integer of 0 or more and j-1 or less). As a result, the circuit 30_k that is not performing the write operation and the read operation can be inactive, so that the power consumption can be reduced.

In the writing operation and reading operation of the circuit 16B, the potential of the wiring 81B (Wsw_enB) fluctuates in the same procedure as the potential of the wiring 81A (Wsw_enA), and the potential of the wiring 82B (Rsw_enB) is the potential of the wiring 82A (Rsw_enA). It fluctuates in the same procedure as. Further, the potentials of the wiring 83 (BS), the wiring 84 (BS +), the wiring 85 (BW) and the wiring 55 (WL) electrically connected to the circuit 17B fluctuate as shown in FIGS. 14 and 15. Other than this, it is the same as the writing operation of the circuit 16A shown in FIG. 14 and the reading operation of the circuit 16A shown in FIG.

Further, the present embodiment is not limited to the imaging device, and can be applied to other semiconductor devices. For example, the present embodiment can be applied to a storage device.

This embodiment can be implemented in combination with the configurations described in the other embodiments as appropriate.

(Embodiment 4)
In the present embodiment, a transistor having an oxide semiconductor that can be used in one aspect of the present invention will be described with reference to the drawings. In the drawings of the present embodiment, some elements are enlarged, reduced, or omitted for clarity.

FIG. 16A is a top view of the transistor 401 according to one aspect of the present invention. Further, the cross section in the direction of the alternate long and short dash line B1-B2 shown in FIG. 16 (A) corresponds to FIG. 16 (B). Further, the cross section in the direction of the alternate long and short dash line B3-B4 shown in FIG. 16 (A) corresponds to FIG. 18 (A). The alternate long and short dash line B1-B2 direction may be referred to as the channel length direction, and the alternate long and short dash line B3-B4 direction may be referred to as the channel width direction.

The transistor 401 includes a substrate 415, an insulating film 420, an oxide semiconductor film 430, a conductive film 440, a conductive film 450, an insulating film 460, a conductive film 470, an insulating film 475, and an insulating film 480. Has.

The insulating film 420 is in contact with the substrate 415, the oxide semiconductor film 430 is in contact with the insulating film 420, the conductive film 440 and the conductive film 450 are in contact with the insulating film 420 and the oxide semiconductor film 430, and the insulating film 460 is in contact with the insulating film 420 and oxidation. Material Semiconductor film 430, conductive film 440 and conductive film 450, conductive film 470 in contact with insulating film 460, insulating film 475 in contact with insulating film 420, conductive film 440, conductive film 450 and conductive film 470, insulating film 480. Is in contact with the insulating film 475.

Here, in the oxide semiconductor film 430, the region in contact with the conductive film 440 is referred to as a region 531, the region in contact with the conductive film 450 is referred to as a region 532, and the region in contact with the insulating film 460 is referred to as a region 533.

Further, the conductive film 440 and the conductive film 450 are electrically connected to the oxide semiconductor film 430.

The conductive film 440 has a function as a source electrode, the conductive film 450 has a function as a drain electrode, the insulating film 460 has a function as a gate insulating film, and the conductive film 470 has a function as a gate electrode.

Further, the region 531 shown in FIG. 16B has a function as a source region, a region 532 has a function as a drain region, and a region 533 has a function as a channel forming region.

Further, although the conductive film 440 and the conductive film 450 are shown in an example of being formed of a single layer, they may be laminated with two or more layers. Further, although the conductive film 470 is shown in an example of being formed of two layers of the conductive film 471 and the conductive film 472, it may be a single layer or a stack of three or more layers. The configuration can also be applied to other transistors described in this embodiment.

If necessary, the insulating film 480 may be provided with a function as a flattening film.

Further, the transistor of one aspect of the present invention may have the configuration shown in FIGS. 16C and 16D. FIG. 16C is a top view of the transistor 402. Further, the cross section in the direction of the alternate long and short dash line C1-C2 shown in FIG. 16 (C) corresponds to FIG. 16 (D). Further, the cross section in the direction of the alternate long and short dash line C3-C4 shown in FIG. 16C corresponds to FIG. 18B. The alternate long and short dash line C1-C2 direction may be referred to as the channel length direction, and the alternate long and short dash line C3-C4 direction may be referred to as the channel width direction.

The transistor 402 is different from the transistor 401 in that the end of the insulating film 460 and the end of the conductive film 470 do not match. In the structure of the transistor 402, since the conductive film 440 and the conductive film 450 are widely covered with the insulating film 460, the electric resistance between the conductive film 440 and the conductive film 450 and the conductive film 470 is high, and the gate leakage current is small. It has characteristics.

The transistor 401 and the transistor 402 have a top gate structure having a region where the conductive film 470, the conductive film 440, and the conductive film 450 overlap. The width of the region in the channel length direction is preferably 3 nm or more and less than 300 nm in order to reduce the parasitic capacitance. In this configuration, since the offset region is not formed on the oxide semiconductor film 430, it is easy to form a transistor having a high on-current.

Further, the transistor of one aspect of the present invention may have the configuration shown in FIGS. 16 (E) and 16 (F). FIG. 16E is a top view of the transistor 403. Further, the cross section in the direction of the alternate long and short dash line D1-D2 shown in FIG. 16 (E) corresponds to FIG. 16 (F). Further, the cross section in the direction of the alternate long and short dash line D3-D4 shown in FIG. 16 (E) corresponds to FIG. 18 (A). The alternate long and short dash line D1-D2 direction may be referred to as the channel length direction, and the alternate long and short dash line D3-D4 direction may be referred to as the channel width direction.

The insulating film 420 of the transistor 403 is in contact with the substrate 415, the oxide semiconductor film 430 is in contact with the insulating film 420, the insulating film 460 is in contact with the insulating film 420 and the oxide semiconductor film 430, and the conductive film 470 is in contact with the insulating film 460. The insulating film 475 is in contact with the insulating film 420, the oxide semiconductor film 430 and the conductive film 470, the insulating film 480 is in contact with the insulating film 475, and the conductive film 440 and the conductive film 450 are in contact with the oxide semiconductor film 430 and the insulating film 480.

An opening is provided in the insulating film 475 and the insulating film 480, and the conductive film 440 and the conductive film 450 are electrically connected to the oxide semiconductor film 430 through the opening.

If necessary, it may have an insulating film (flattening film) in contact with the conductive film 440, the conductive film 450, and the insulating film 480.

Further, in the oxide semiconductor film 430, a region in contact with the insulating film 475 and sandwiched between the region 531 and the region 533 is designated as the region 534. Further, the region in contact with the insulating film 475 and sandwiched between the region 532 and the region 533 is referred to as the region 535.

Further, the transistor of one aspect of the present invention may have the configuration shown in FIGS. 17A and 17B. FIG. 17A is a top view of the transistor 404. Further, the cross section in the direction of the alternate long and short dash line E1-E2 shown in FIG. 17 (A) corresponds to FIG. 17 (B). The cross section in the direction of the alternate long and short dash line E3-E4 shown in FIG. 17 (A) corresponds to FIG. 18 (A). The alternate long and short dash line E1-E2 direction may be referred to as the channel length direction, and the alternate long and short dash line E3-E4 direction may be referred to as the channel width direction.

The insulating film 420 of the transistor 404 is in contact with the substrate 415, the oxide semiconductor film 430 is in contact with the insulating film 420, the conductive film 440 and the conductive film 450 are in contact with the insulating film 420 and the oxide semiconductor film 430, and the insulating film 460 is an insulating film. The conductive film 470 is in contact with the insulating film 420, the oxide semiconductor film 430, the conductive film 440, the conductive film 450 and the conductive film 470, and the conductive film 470 is in contact with the insulating film 420 and the oxide semiconductor film 430. 480 is in contact with the insulating film 475.

The transistor 404 differs from the transistor 403 in that the conductive film 440 and the conductive film 450 are in contact with each other so as to cover the end portion of the oxide semiconductor film 430.

The transistor 403 and the transistor 404 have a self-aligned structure in which the conductive film 470 does not overlap with the conductive film 440 and the conductive film 450. Self-aligned transistors are suitable for high-speed operation applications because they have extremely small parasitic capacitances at the gate, source and drain.

Further, the transistor of one aspect of the present invention may have the configuration shown in FIGS. 17 (C) and 17 (D). FIG. 17C is a top view of the transistor 405. Further, the cross section in the direction of the alternate long and short dash line F1-F2 shown in FIG. 17 (C) corresponds to FIG. 17 (D). Further, the cross section in the direction of the alternate long and short dash line F3-F4 shown in FIG. 17C corresponds to FIG. 18A. The alternate long and short dash line F1-F2 direction may be referred to as the channel length direction, and the alternate long and short dash line F3-F4 direction may be referred to as the channel width direction.

In the transistor 405, the conductive film 440 is formed of two layers of the conductive film 441 and the conductive film 442, and the conductive film 450 is formed of two layers of the conductive film 451 and the conductive film 452. Further, the insulating film 420 is in contact with the substrate 415, the oxide semiconductor film 430 is in contact with the insulating film 420, the conductive film 441 and the conductive film 451 are in contact with the oxide semiconductor film 430, and the insulating film 460 is in contact with the insulating film 420 and the oxide semiconductor. The conductive film 430, the conductive film 441 and the conductive film 451 are in contact with each other, the conductive film 470 is in contact with the insulating film 460, the insulating film 475 is in contact with the insulating film 420, the conductive film 441, the conductive film 451 and the conductive film 470, and the insulating film 480 is insulated. It is in contact with the film 475, the conductive film 442 is in contact with the conductive film 441 and the insulating film 480, and the conductive film 452 is in contact with the conductive film 451 and the insulating film 480.

Here, the conductive film 441 and the conductive film 451 are configured to be in contact with the upper surface of the oxide semiconductor film 430 and not to the side surface.

If necessary, the conductive film 442, the conductive film 452, and the insulating film in contact with the insulating film 480 may be provided.

Further, the conductive film 441 and the conductive film 451 are electrically connected to the oxide semiconductor film 430. The conductive film 442 is electrically connected to the conductive film 441, and the conductive film 452 is electrically connected to the conductive film 451.

In the oxide semiconductor film 430, the region overlapping the conductive film 441 becomes a region 531 having a function as a source region, and a region 532 having a function as a region drain region overlapping the conductive film 451.

Further, the transistor of one aspect of the present invention may have the configuration shown in FIGS. 17 (E) and 17 (F). FIG. 17 (E) is a top view of the transistor 406. Further, the cross section in the direction of the alternate long and short dash line G1-G2 shown in FIG. 17 (E) corresponds to FIG. 17 (F). The cross section in the direction of the alternate long and short dash line G3-G4 shown in FIG. 17 (E) corresponds to FIG. 18 (A). The alternate long and short dash line G1-G2 direction may be referred to as the channel length direction, and the alternate long and short dash line G3-G4 direction may be referred to as the channel width direction.

The transistor 406 is different from the transistor 403 in that the conductive film 440 is formed of two layers of the conductive film 441 and the conductive film 442, and the conductive film 450 is formed of two layers of the conductive film 451 and the conductive film 452.

In the configuration of the transistor 405 and the transistor 406, since the conductive film 440 and the conductive film 450 are not in contact with the insulating film 420, oxygen in the insulating film 420 is less likely to be taken away by the conductive film 440 and the conductive film 450, and the insulating film The supply of oxygen from the 420 into the oxide semiconductor film 430 can be facilitated.

In addition, impurities for forming oxygen deficiency and increasing conductivity may be added to the regions 534 and 535 of the transistor 403, the transistor 404, and the transistor 406. As impurities that form oxygen deficiency in the oxide semiconductor film, for example, phosphorus, arsenic, antimony, boron, aluminum, silicon, nitrogen, helium, neon, argon, krypton, xenon, indium, fluorine, chlorine, titanium, zinc, etc. And one or more selected from any of carbon can be used. As a method for adding the impurities, a plasma treatment method, an ion implantation method, an ion doping method, a plasma imaging ion implantation method, or the like can be used.

When the above element is added to the oxide semiconductor film as an impurity element, the bond between the metal element and oxygen in the oxide semiconductor film is broken, and an oxygen deficiency is formed. The conductivity of the oxide semiconductor film can be increased by the interaction between the oxygen deficiency contained in the oxide semiconductor film and hydrogen remaining in the oxide semiconductor film or added later.

When hydrogen is added to an oxide semiconductor in which oxygen deficiency is formed by the addition of an impurity element, hydrogen enters the oxygen deficient site and a donor level is formed in the vicinity of the conduction band. As a result, an oxide conductor can be formed. Here, the oxide semiconductor made into a conductor is referred to as an oxide conductor. The oxide conductor has translucency like the oxide semiconductor.

The oxide conductor is a degenerate semiconductor, and it is presumed that the conduction band edge and the Fermi level coincide with or substantially coincide with each other. Therefore, the contact between the oxide conductor film and the conductive film having a function as a source and a drain is ohmic contact, and the contact resistance between the oxide conductor film and the conductive film having a function as a source and a drain. Can be reduced.

Further, in the transistors 401 to 406 in FIGS. 16 to 18, an example in which the oxide semiconductor film 430 is a single layer is shown, but the oxide semiconductor film 430 may be laminated. 19 (A) is a top view of the oxide semiconductor film 430, and FIGS. 19 (B) and 19 (C) are an oxide semiconductor film 430 having a two-layer structure of the oxide semiconductor film 430a and the oxide semiconductor film 430b. It is a cross-sectional view of. 19 (D) and 19 (E) are cross-sectional views of the oxide semiconductor film 430 having a three-layer structure of the oxide semiconductor film 430a, the oxide semiconductor film 430b, and the oxide semiconductor film 430c.

Since the oxide semiconductor film 430a and the oxide semiconductor film 430c do not form a channel region, they can also be called an insulating film.

For the oxide semiconductor film 430a, the oxide semiconductor film 430b, and the oxide semiconductor film 430c, oxide semiconductor films having different compositions can be used.

The oxide semiconductor film 430 of the transistors 401 to 406 can be replaced with the oxide semiconductor film 430 shown in FIGS. 19 (B), (C) or 19 (D), (E).

Further, the transistor of one aspect of the present invention may have the configuration shown in FIGS. 20 to 22. 20 (A), (C), (E) and 21 (A), (C), (E) are top views of transistors 407 to 412. Further, the cross section of the alternate long and short dash line H1-H2 direction to M1-M2 direction shown in FIGS. 20 (A), (C), (E) and 21 (A), (C), (E) is shown in FIG. 20 (B). , (D), (F) and FIGS. 21 (B), (D), (F). Further, the cross sections in the directions of the alternate long and short dash lines H3-H4 and J3-J4 to M3-M4 shown in FIGS. 20 (A) and 20 (A) and 21 (A), (C) and (E) are shown in FIG. 22 (A). Equivalent to. Further, the cross section in the direction of the alternate long and short dash line I3-I4 shown in FIG. 20 (C) corresponds to FIG. 22 (B). The alternate long and short dash line H1-H2 direction to M1-M2 direction may be referred to as the channel length direction, and the alternate long and short dash line H3-H4 direction to M3-M4 direction may be referred to as the channel width direction.

In the transistor 407 and the transistor 408, the oxide semiconductor film 430 has two layers (oxide semiconductor film 430a, oxide semiconductor film 430b) in the region 531 and the region 532, and the oxide semiconductor film 430 has three layers (oxide semiconductor film 430a, oxide semiconductor film 430b) in the region 533. Oxide semiconductor film 430a, oxide semiconductor film 430b, oxide semiconductor film 430c), and a part of the oxide semiconductor film (oxide) between the conductive film 440 and the conductive film 450 and the insulating film 460. It has the same configuration as the transistor 401 and the transistor 402 except that the semiconductor film 430c) is interposed.

In the region 533, the transistor 409, the transistor 410, and the transistor 412 have two layers (oxide semiconductor film 430a, oxide semiconductor film 430b) of the oxide semiconductor film 430 in the regions 531 and 532, the region 534, and the region 535. It has the same configuration as the transistor 403, the transistor 404, and the transistor 406, except that the oxide semiconductor film 430 has three layers (oxide semiconductor film 430a, oxide semiconductor film 430b, and oxide semiconductor film 430c).

In the transistor 411, the oxide semiconductor film 430 has two layers (oxide semiconductor film 430a and the oxide semiconductor film 430b) in the region 531 and the region 532, and the oxide semiconductor film 430 has three layers (oxide semiconductor) in the region 533. A part of the oxide semiconductor film (oxide semiconductor film 430c) between the film 430a, the oxide semiconductor film 430b, the oxide semiconductor film 430c), and the conductive film 441 and the conductive film 451 and the insulating film 460. ) Is intervened, and has the same configuration as the transistor 405.

Further, the transistors according to one aspect of the present invention are shown in FIGS. 23 (A), (B), (C), (D), (E), (F) and 24 (A), (B), (C). , (D), (E), (F), a cross-sectional view of the transistors 401 to 412 in the channel length direction, and FIG. 18 (C), a cross-sectional view of the transistors 401 to 406 in the channel width direction, and FIG. 22. As shown in the cross-sectional view of the transistors 407 to 412 in the channel width direction shown in (C), a conductive film 473 may be provided between the oxide semiconductor film 430 and the substrate 415. By using the conductive film 473 as a second gate (also referred to as a back gate), the channel forming region of the oxide semiconductor film 430 is electrically surrounded by the conductive film 470 and the conductive film 473. The structure of such a transistor is called a surroundd channel (s-channel) structure. This makes it possible to increase the on-current. In addition, the threshold voltage can be controlled. It should be noted that FIGS. 23 (A), (B), (C), (D), (E), (F) and 24 (A), (B), (C), (D), (E), In the cross-sectional view shown in (F), the width of the conductive film 473 may be shorter than that of the oxide semiconductor film 430. Further, the width of the conductive film 473 may be shorter than the width of the conductive film 470.

In order to increase the on-current, for example, the conductive film 470 and the conductive film 473 may have the same potential and be driven as a double gate transistor. Further, in order to control the threshold voltage, a constant potential different from that of the conductive film 470 may be supplied to the conductive film 473. In order to make the conductive film 470 and the conductive film 473 have the same potential, for example, as shown in FIGS. 18 (D) and 22 (D), the conductive film 470 and the conductive film 473 are electrically connected through a contact hole. Just connect.

Further, the transistor according to one aspect of the present invention may have the configuration shown in FIGS. 25 (A), 25 (B), and (C). FIG. 25A is a top view. Further, FIG. 25 (B) is a cross-sectional view corresponding to the alternate long and short dash line N1-N2 shown in FIG. 25 (A). Further, FIG. 25 (C) is a cross-sectional view corresponding to the alternate long and short dash line N3-N4 shown in FIG. 25 (A). In the top view of FIG. 25A, some elements are omitted for the sake of clarity.

The insulating film 420 of the transistor 413 is in contact with the substrate 415, and the oxide semiconductor film 430 (oxide semiconductor film 430a, oxide semiconductor film 430b and oxide semiconductor film 430c) is in contact with the insulating film 420, and the conductive film 440 and the conductive film 450 are in contact with each other. Is in contact with the oxide semiconductor film 430b, the insulating film 460 is in contact with the oxide semiconductor film 430c, the conductive film 470 is in contact with the insulating film 460, and the insulating film 480 is in contact with the insulating film 420, the conductive film 440 and the conductive film 450. The oxide semiconductor film 430c, the insulating film 460, and the conductive film 470 are provided in the insulating film 480 and are provided in the opening reaching the oxide semiconductor film 430b.

In the configuration of the transistor 413, the parasitic capacitance can be reduced because the region where the conductive film 440 or the conductive film 450 and the conductive film 470 overlap is smaller than the configuration of the other transistors described above. Therefore, the transistor 413 is suitable as an element of a circuit that requires high-speed operation. The upper surface of the transistor 413 is preferably flattened by using a CMP (Chemical Mechanical Polishing) method or the like as shown in FIGS. 25 (B) and 25 (C), but it may not be flattened.

Further, the conductive film 440 and the conductive film 450 in the transistor of one aspect of the present invention are the conductive film 440 and the conductive film 450 rather than the width ( _WOS ) of the oxide semiconductor film as shown in the top view shown in FIG. 26 (A). The width ( _WSD ) of the above may be formed to be long, or may be formed to be short as shown in the top view shown in FIG. 26 (B). In particular, by setting W _OS ≥ W _SD (W _SD is W _OS or less), the gate electric field is likely to be applied to the entire oxide semiconductor film 430, and the electrical characteristics of the transistor can be improved. Further, as shown in FIG. 26C, the conductive film 440 and the conductive film 450 may be formed only in the region overlapping the oxide semiconductor film 430.

In FIGS. 26A, 26B, and 26C, only the oxide semiconductor film 430, the conductive film 440, and the conductive film 450 are shown.

Further, in the transistor having the oxide semiconductor film 430a and the oxide semiconductor film 430b, and the transistor having the oxide semiconductor film 430a, the oxide semiconductor film 430b and the oxide semiconductor film 430c, the oxide semiconductor film 430 is formed. By appropriately selecting the material of the layer or the three layers, a current can be passed through the oxide semiconductor film 430b. Since the current flows through the oxide semiconductor film 430b, it is not easily affected by interfacial scattering, and a high on-current can be obtained. Therefore, the on-current may be improved by thickening the oxide semiconductor film 430b.

By using the transistor having the above configuration, it is possible to impart good electrical characteristics to the semiconductor device.

The configuration shown in this embodiment can be used in combination with the configuration shown in other embodiments as appropriate.

(Embodiment 5)
In the present embodiment, the components of the transistor shown in the fourth embodiment will be described in detail.

<Board>
As the substrate 415, a glass substrate, a quartz substrate, a semiconductor substrate, a ceramic substrate, a metal substrate whose surface is insulated, or the like can be used. Alternatively, a silicon substrate on which a transistor or a photodiode is formed, or a silicon substrate on which an insulating film, wiring, a conductor having a function as a contact plug, or the like is formed can be used. When forming a p-ch type transistor on a silicon substrate, it is preferable to use a silicon substrate having an n ^- type conductive type. Alternatively, it may be an SOI substrate having an n ^- type or i-type silicon layer. When the transistor provided on the silicon substrate is of the p-ch type, it is preferable to use the silicon substrate having the (110) plane as the plane orientation of the surface on which the transistor is formed. By forming the p-ch type transistor on the (110) plane, the mobility can be increased.

<Base insulating film>
The insulating film 420 having a function as an underlying insulating film has a role of preventing the diffusion of impurities from the elements contained in the substrate 415 and also can play a role of supplying oxygen to the oxide semiconductor film 430. Therefore, the insulating film 420 is preferably an insulating film containing oxygen, and more preferably an insulating film containing more oxygen than the stoichiometric composition. For example, in the TDS method in which the surface temperature of the film is 100 ° C. or higher and 700 ° C. or lower, preferably 100 ° C. or higher and 500 ° C. or lower, the amount of oxygen released in terms of oxygen atoms is 1.0 × 10 ¹⁹ atoms. The film is / cm ³ or more. Further, when the substrate 415 is a substrate on which another device is formed, the insulating film 420 also has a function as an interlayer insulating film. In that case, it is preferable to perform a flattening treatment by a CMP method or the like so that the surface becomes flat.

For example, the insulating film 420 is provided with an oxide insulating film such as aluminum oxide, magnesium oxide, silicon oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide and tantalum oxide. , A nitride insulating film such as silicon nitride, silicon nitride oxide, aluminum nitride, aluminum nitride, or a mixed material thereof can be used. Further, the above materials may be laminated.

<Oxide semiconductor film>
The oxide semiconductor film 430 can have a three-layer structure in which the oxide semiconductor film 430a, the oxide semiconductor film 430b, and the oxide semiconductor film 430c are stacked in order from the insulating film 420 side.

When the oxide semiconductor film 430 is a single layer, the layer corresponding to the oxide semiconductor film 430b shown in the present embodiment may be used.

When the oxide semiconductor film 430 has two layers, a laminate in which a layer corresponding to the oxide semiconductor film 430a and a layer corresponding to the oxide semiconductor film 430b are stacked in order from the insulating film 420 side may be used. In the case of this configuration, the oxide semiconductor film 430a and the oxide semiconductor film 430b can be interchanged.

As an example, as the oxide semiconductor film 430b, an oxide semiconductor having a higher electron affinity (energy from the vacuum level to the lower end of the conduction band) than the oxide semiconductor film 430a and the oxide semiconductor film 430c is used.

In such a structure, when an electric field is applied to the conductive film 470, a channel is formed in the oxide semiconductor film 430b having the smallest energy at the lower end of the conduction band among the oxide semiconductor films 430. Therefore, it can be said that the oxide semiconductor film 430b has a region that functions as a semiconductor, but it can also be said that the oxide semiconductor film 430a and the oxide semiconductor film 430c have a region that functions as an insulator or a semi-insulator.

Further, the oxide semiconductor that can be used as the oxide semiconductor film 430a, the oxide semiconductor film 430b, and the oxide semiconductor film 430c preferably contains at least In or Zn. Alternatively, it is preferable to contain both In and Zn. Further, in order to reduce variations in the electrical characteristics of transistors using the oxide semiconductor, it is preferable to include a stabilizer together with them.

Stabilizers include Ga, Sn, Hf, Al, Zr and the like. In addition, other stabilizers include lanthanoids such as La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu.

The oxide semiconductor film 430a, the oxide semiconductor film 430b, and the oxide semiconductor film 430c preferably include a crystal portion. In particular, by using a crystal oriented on the c-axis, stable electrical characteristics can be imparted to the transistor. Further, the crystal oriented on the c-axis is resistant to distortion, and the reliability of the semiconductor device using the flexible substrate can be improved.

<Source electrode and drain electrode>
The conductive film 440 acting as a source electrode and the conductive film 450 acting as a drain electrode include, for example, an alloy of Al, Cr, Cu, Ta, Ti, Mo, W, Ni, Mn, Nd, Sc, and the metal material. A single layer or a laminate of materials selected from the above can be used. Typically, it is more preferable to use W, which has a high melting point, because Ti, which is particularly easy to bond with oxygen, and the subsequent process temperature can be relatively high. Further, a laminate of a low resistance alloy such as Cu or Cu-Mn and the above material may be used. In the transistor 405, the transistor 406, the transistor 411, and the transistor 412, for example, W can be used for the conductive film 441 and 451 and a laminated film of Ti and Al can be used for the conductive film 442 and the conductive film 452.

The above-mentioned material has a property of extracting oxygen from an oxide semiconductor film. Therefore, oxygen in the oxide semiconductor film is desorbed in a part of the region of the oxide semiconductor film in contact with the material, and oxygen deficiency is formed. The region is remarkably n-shaped due to the combination of a small amount of hydrogen contained in the membrane and the oxygen deficiency. Therefore, the n-type region can act as a source or drain of a transistor.

Further, when W is used for the conductive film 440 and the conductive film 450, nitrogen may be doped. By doping with nitrogen, the property of extracting oxygen can be appropriately weakened, and it is possible to prevent the n-type region from expanding to the channel region. Further, the conductive film 440 and the conductive film 450 are laminated with the n-type semiconductor layer, and the n-type semiconductor layer and the oxide semiconductor film are brought into contact with each other to prevent the n-type region from expanding to the channel region. be able to. As the n-type semiconductor layer, nitrogen-added In-Ga-Zn oxide, zinc oxide, indium oxide, tin oxide, indium tin oxide and the like can be used.

<Gate insulating film>
The insulating film 460 that acts as a gate insulating film includes aluminum oxide, magnesium oxide, silicon oxide, silicon nitride nitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, and neodymium oxide. An insulating film containing one or more of hafnium oxide and tantalum oxide can be used. Further, the insulating film 460 may be a laminate of the above materials. The insulating film 460 may contain La, N, Zr and the like as impurities.

Moreover, an example of the laminated structure of the insulating film 460 will be described. The insulating film 460 has, for example, oxygen, nitrogen, silicon, hafnium and the like. Specifically, it is preferable to contain hafnium oxide and silicon oxide or silicon nitride nitride.

Hafnium oxide and aluminum oxide have a higher relative permittivity than silicon oxide and silicon nitride. Therefore, since the film thickness of the insulating film 460 can be increased as compared with the case where silicon oxide is used, the leakage current due to the tunnel current can be reduced. That is, it is possible to realize a transistor having a small off-current. Further, hafnium oxide having a crystal structure has a higher relative permittivity than hafnium oxide having an amorphous structure. Therefore, in order to obtain a transistor having a small off-current, it is preferable to use hafnium oxide having a crystal structure. Examples of the crystal structure include a monoclinic system and a cubic system. However, one aspect of the present invention is not limited to these.

Further, as the insulating film 420 and the insulating film 460 in contact with the oxide semiconductor film 430, it is preferable to use films having a small amount of nitrogen oxides released. When an insulating film that emits a large amount of nitrogen oxides is in contact with an oxide semiconductor, the level density due to nitrogen oxides may increase. As the insulating film 420 and the insulating film 460, for example, an oxide insulating film such as a silicon oxide film or an aluminum nitride film that emits a small amount of nitrogen oxides can be used.

A silicon oxynitride film with a small amount of nitrogen oxides released is a film that releases more ammonia than the amount of nitrogen oxides released in the TDS method, and typically emits 1 × 10 ¹⁸ / cm of ammonia. ³ or more and 5 × 10 ¹⁹ / cm ³ or less. The amount of ammonia released is the amount released by heat treatment at which the surface temperature of the film is 50 ° C. or higher and 650 ° C. or lower, preferably 50 ° C. or higher and 550 ° C. or lower.

By using the oxide insulating film as the insulating film 420 and the insulating film 460, it is possible to reduce the shift of the threshold voltage of the transistor, and it is possible to reduce the fluctuation of the electrical characteristics of the transistor.

<Gate electrode>
As the conductive film 470 acting as a gate electrode, for example, conductive films such as Al, Ti, Cr, Co, Ni, Cu, Y, Zr, Mo, Ru, Ag, Mn, Nd, Sc, Ta and W are used. be able to. Further, an alloy of the above material or a conductive nitride of the above material may be used. Further, a plurality of materials selected from the above materials, alloys of the above materials, and conductive nitrides of the above materials may be laminated. Typically, tungsten, a laminate of tungsten and titanium nitride, a laminate of tungsten and tantalum nitride, and the like can be used. Further, a low-resistance alloy such as Cu or Cu-Mn or a laminate of the above material and an alloy such as Cu or Cu-Mn may be used. In the present embodiment, tantalum nitride is used for the conductive film 471 and tungsten is used for the conductive film 472 to form the conductive film 470.

<Protective insulating film>
As the insulating film 475 having a function as a protective insulating film, a silicon nitride film containing hydrogen, an aluminum nitride film, or the like can be used. In the transistor 403, transistor 404, transistor 406, transistor 409, transistor 410, and transistor 412 shown in the fourth embodiment, a part of the oxide semiconductor film is n-type by using an insulating film containing hydrogen as the insulating film 475. Can be transformed into. In addition, the nitride insulating film also acts as a blocking film for moisture and the like, and can improve the reliability of the transistor.

Further, an aluminum oxide film can also be used as the insulating film 475. In particular, in the transistor 401, the transistor 402, the transistor 405, the transistor 407, the transistor 408, and the transistor 411 shown in the fourth embodiment, it is preferable to use an aluminum oxide film as the insulating film 475. The aluminum oxide film has a high blocking effect that does not allow the film to permeate both impurities such as hydrogen and water, and oxygen. Therefore, the aluminum oxide film prevents impurities such as hydrogen and moisture from being mixed into the oxide semiconductor film 430, prevents oxygen from being released from the oxide semiconductor film, and from the insulating film 420 during and after the manufacturing process of the transistor. It is suitable for use as a protective film having the effect of preventing unnecessary release of oxygen. In addition, oxygen contained in the aluminum oxide film can be diffused into the oxide semiconductor film.

Further, it is preferable that the insulating film 480 is formed on the insulating film 475. The insulating film contains one or more of magnesium oxide, silicon oxide, silicon nitride nitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide and tantalum oxide. An insulating film can be used. Further, the insulating film may be a laminate of the above materials.

Here, it is preferable that the insulating film 480 has more oxygen than the stoichiometric composition like the insulating film 420. Since the oxygen released from the insulating film 480 can be diffused into the channel forming region of the oxide semiconductor film 430 via the insulating film 460, oxygen can be supplemented to the oxygen deficiency formed in the channel forming region. .. Therefore, stable electric characteristics of the transistor can be obtained.

Miniaturization of transistors is indispensable for highly integrated semiconductor devices. On the other hand, it is known that the electrical characteristics of a transistor deteriorate due to the miniaturization of the transistor, and the on-current decreases particularly when the channel width is reduced.

In the transistors 407 to 412 of one aspect of the present invention, the oxide semiconductor film 430c is formed so as to cover the oxide semiconductor film 430b on which the channel is formed, and the channel forming layer and the gate insulating film are not in contact with each other. It has become. Therefore, it is possible to suppress the scattering of carriers generated at the interface between the channel forming layer and the gate insulating film, and it is possible to increase the on-current of the transistor.

Further, in the transistor of one aspect of the present invention, since the gate electrode (conductive film 470) is formed so as to electrically surround the channel width direction of the oxide semiconductor film 430 as described above, the oxide semiconductor film 430 In addition to the gate electric field from the direction perpendicular to the upper surface, the gate electric field is applied from the direction perpendicular to the side surface. That is, the gate electric field is applied to the channel cambium as a whole, and the effective channel width is expanded, so that the on-current can be further increased.

<Film formation method>
Various films such as the metal film, the semiconductor film, and the inorganic insulating film described in the present embodiment can be typically formed by a sputtering method or a plasma CVD method, but by another method, for example, a thermal CVD method. It may be formed. Examples of the thermal CVD method include a MOCVD (Metalorganic Chemical Vapor Deposition) method and an ALD (Atomic Layer Deposition) method.

Since the thermal CVD method is a film forming method that does not use plasma, it has an advantage that defects are not generated due to plasma damage.

Further, in the thermal CVD method, the raw material gas and the oxidizing agent are sent into the chamber at the same time, the inside of the chamber is set to atmospheric pressure or reduced pressure, and the reaction is carried out near or on the substrate to deposit on the substrate to form a film. May be good.

In the ALD method, the inside of the chamber is set to atmospheric pressure or reduced pressure, the raw material gas for the reaction is introduced into the chamber and reacted, and this is repeated to form a film. An inert gas (argon, nitrogen, etc.) may be introduced as a carrier gas together with the raw material gas. For example, two or more kinds of raw material gases may be supplied to the chamber in order. At that time, after the reaction of the first raw material gas, the inert gas is introduced and the second raw material gas is introduced so that the plurality of kinds of raw material gases are not mixed. Alternatively, instead of introducing the inert gas, the first raw material gas may be discharged by vacuum exhaust, and then the second raw material gas may be introduced. The first raw material gas is adsorbed and reacted on the surface of the substrate to form a first layer, and the second raw material gas introduced later is adsorbed and reacted on the first layer. That is, the second layer is laminated on the first layer to form a thin film. By repeating this process a plurality of times until a desired thickness is obtained while controlling the gas introduction order, a thin film having excellent step covering property can be formed. Since the thickness of the thin film can be adjusted by the number of times the gas is introduced repeatedly, the film thickness can be precisely adjusted, which is suitable for manufacturing a fine FET.

Thermal CVD methods such as the MOCVD method and the ALD method can form various films such as the metal film, the semiconductor film, and the inorganic insulating film disclosed in the embodiments described so far, and for example, In-Ga-Zn. When forming the −O layer, trimethylindium (In (CH ₃ ) ₃ ), trimethylgallium (Ga (CH ₃ ) ₃ ), and dimethylzinc (Zn (CH ₃ ) ₂ ) can be used. Not limited to these combinations, triethylgallium (Ga (C ₂ H ₅ ) ₃ ) can be used instead of trimethylgallium, and diethylzinc (Zn (C ₂ H ₅ ) ₂ ) can be used instead of dimethylzinc. You can also do it.

For example, when a hafnium oxide film is formed by a film forming apparatus using ALD, a liquid containing a solvent and a hafnium precursor (hafnium alkoxide or tetrakisdimethylamide hafnium (TDHA, Hf [N (CH ₃ ) ₂ ] ₂ ] ₄ ) and and tetrakis (ethylmethylamido) material gases hafnium amide) is vaporized, such as hafnium, using two types of gas ozone (O ₃₎ as an oxidizing agent.

For example, when an aluminum oxide film is formed by a film forming apparatus using ALD, a liquid containing a solvent and an aluminum precursor (trimethylaluminum (TMA, Al (CH ₃ ) ₃ ), etc.) is vaporized with a raw material gas. , using two types of gases _{H 2} O as the oxidizing agent. Other materials include tris (dimethylamide) aluminum, triisobutylaluminum, aluminum tris (2,2,6,6-tetramethyl-3,5-heptanetone) and the like.

For example, when a silicon oxide film is formed by a film forming apparatus using ALD, hexachlorodisilane is adsorbed on the surface to be formed, and radicals of an oxidizing gas (O ₂ , dinitrogen monoxide) are supplied and adsorbed. React with things.

For example, when a tungsten film is formed by a film forming apparatus using ALD, WF ₆ gas and B ₂ H ₆ gas are sequentially introduced to form an initial tungsten film, and then WF ₆ gas and H ₂ gas are formed. Are sequentially introduced to form a tungsten film. In addition, SiH ₄ gas may be used instead of B ₂ H ₆ gas.

For example, when an oxide semiconductor film, for example, an In-Ga-Zn-O layer is formed by a film forming apparatus using ALD, In (CH ₃ ) ₃ gas and O ₃ gas are sequentially introduced to form In-. An O layer is formed, and then Ga (CH ₃ ) ₃ gas and O ₃ gas are sequentially introduced to form a GaO layer, and then Zn (CH ₃ ) ₂ gas and O ₃ gas are sequentially introduced to form a ZnO layer. To form. The order of these layers is not limited to this example. These gases may be used to form a mixed compound layer such as an In—Ga—O layer, an In—Zn—O layer, and a Ga—Zn—O layer. Incidentally, instead of the O ₃ gas may be used of H _{2 O} gas obtained by bubbling with an inert gas such as Ar, but better to use an O ₃ gas containing no H are preferred.

A counter-target sputtering apparatus can also be used for forming the oxide semiconductor film. The film forming method using the opposed target sputtering apparatus can also be called VDSP (vapor deposition SP).

By forming the oxide semiconductor film using the opposed target sputtering apparatus, it is possible to reduce the plasma damage during the film formation of the oxide semiconductor film. Therefore, oxygen deficiency in the membrane can be reduced. In addition, since film formation at low pressure is possible by using an opposed target sputtering device, the concentration of impurities (for example, hydrogen, rare gas (argon, etc.), water, etc.) in the filmed oxide semiconductor film is reduced. Can be made to.

The configuration shown in this embodiment can be used in combination with the configuration shown in other embodiments as appropriate.

(Embodiment 6)
In the present embodiment, an oxide semiconductor material that can be used in one aspect of the present invention will be described.

The oxide semiconductor preferably contains at least indium or zinc. In particular, it preferably contains indium and zinc. In addition to them, aluminum, gallium, yttrium, tin and the like are preferably contained. Further, one or more kinds selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium and the like may be contained.

Here, consider the case where the oxide semiconductor has indium, the element M, and zinc. The element M is aluminum, gallium, yttrium, tin, or the like. Examples of elements applicable to the other element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. However, as the element M, a plurality of the above-mentioned elements may be combined in some cases.

First, a preferable range of atomic number ratios of indium, element M, and zinc contained in the oxide semiconductor according to the present invention will be described with reference to FIGS. 27 (A), 27 (B), and 27 (C). Note that FIG. 27 does not show the atomic number ratio of oxygen. Further, the respective terms of the atomic number ratios of indium, element M, and zinc contained in the oxide semiconductor are [In], [M], and [Zn].

In FIGS. 27 (A), 27 (B), and 27 (C), the broken line indicates the atomic number ratio of [In]: [M]: [Zn] = (1 + α) :( 1-α): 1. Line where (-1 ≤ α ≤ 1), [In]: [M]: [Zn] = (1 + α): (1-α): Line where the atomic number ratio is 2, [In]: [M] : [Zn] = (1 + α): (1-α): A line having an atomic number ratio of 3, [In]: [M]: [Zn] = (1 + α): (1-α): 4 atomic numbers It represents a line having a ratio and a line having an atomic number ratio of [In]: [M]: [Zn] = (1 + α) :( 1-α): 5.

The one-point chain line is a line having an atomic number ratio of [In]: [M]: [Zn] = 1: 1: β (β ≧ 0), [In]: [M]: [Zn] = 1: 2: Atomic number ratio of β, [In]: [M]: [Zn] = 1: 3: Atomic number ratio of β, [In]: [M]: [Zn] = 1: 4: Atomic number ratio of β, [In]: [M]: [Zn] = 2: 1: β atomic number ratio, and [In]: [M]: [Zn] = 5 Represents a line with an atomic number ratio of 1: β.

27 (A) and 27 (B) show an example of a preferable range of atomic number ratios of indium, element M, and zinc contained in the oxide semiconductor of one aspect of the present invention.

As an example, FIG. 28 shows the crystal structure of InMZnO ₄ in which [In]: [M]: [Zn] = 1: 1: 1. Further, FIG. 28 shows the crystal structure of InMZnO ₄ when observed from a direction parallel to the b-axis. The metal element in the layer having M, Zn, and oxygen (hereinafter, (M, Zn) layer) shown in FIG. 28 represents the element M or zinc. In this case, it is assumed that the ratios of the element M and zinc are equal. The elements M and zinc can be substituted and the arrangement is irregular.

InMZnO ₄ has a layered crystal structure (also referred to as a layered structure), and as shown in FIG. 28, the layer having indium and oxygen (hereinafter referred to as the In layer) has 1 and the elements M, zinc, and oxygen. The number of (M, Zn) layers is 2.

Further, indium and element M can be replaced with each other. Therefore, the element M of the (M, Zn) layer can be replaced with indium and expressed as the (In, M, Zn) layer. In that case, it has a layered structure in which the In layer is 1 and the (In, M, Zn) layer is 2.

An oxide semiconductor having an atomic number ratio of [In]: [M]: [Zn] = 1: 1: 2 has a layered structure in which the In layer is 1 and the (M, Zn) layer is 3. That is, when [Zn] is larger than [In] and [M], the ratio of the (M, Zn) layer to the In layer increases when the oxide semiconductor is crystallized.

However, in the oxide semiconductor, when the number of layers of the (M, Zn) layer is non-integer with respect to one layer of the In layer, the number of layers of the (M, Zn) layer is larger than that of one layer of the In layer. It may have multiple types of layered structures that are integers. For example, when [In]: [M]: [Zn] = 1: 1: 1.5, a layered structure in which the In layer is 1 and the (M, Zn) layer is 2, and (M, Zn) ) The layered structure may be a mixture of the layered structure having 3 layers.

For example, when an oxide semiconductor is formed into a film by a sputtering apparatus, a film having an atomic number ratio deviating from the target atomic number ratio is formed. In particular, depending on the substrate temperature at the time of film formation, the film [Zn] may be smaller than the target [Zn].

In addition, a plurality of phases may coexist in the oxide semiconductor (two-phase coexistence, three-phase coexistence, etc.). For example, at an atomic number ratio that is close to the atomic number ratio of [In]: [M]: [Zn] = 0: 2: 1, two phases of a spinel-type crystal structure and a layered crystal structure coexist. Cheap. Further, in the atomic number ratio, which is a value close to the atomic number ratio indicating [In]: [M]: [Zn] = 1: 0: 0, the two phases of the big bite type crystal structure and the layered crystal structure are present. Easy to coexist. When a plurality of phases coexist in an oxide semiconductor, grain boundaries (also referred to as grain boundaries) may be formed between different crystal structures.

Further, by increasing the indium content, the carrier mobility (electron mobility) of the oxide semiconductor can be increased. This is because in oxide semiconductors containing indium, element M, and zinc, the s orbitals of heavy metals mainly contribute to carrier conduction, and by increasing the content of indium, the region where the s orbitals overlap becomes larger. This is because an oxide semiconductor having a high indium content has a higher carrier mobility than an oxide semiconductor having a low indium content.

On the other hand, when the content of indium and zinc in the oxide semiconductor is low, the carrier mobility is low. Therefore, in the atomic number ratio showing [In]: [M]: [Zn] = 0: 1: 0 and the atomic number ratio which is a value close to the ratio (for example, region C shown in FIG. 27C), the insulating property Will be higher.

Therefore, it is preferable that the oxide semiconductor of one aspect of the present invention has the atomic number ratio shown in the region A of FIG. 27 (A), which tends to have a layered structure having high carrier mobility and few grain boundaries.

Further, the region B shown in FIG. 27 (B) shows [In]: [M]: [Zn] = 4: 2: 3 to 4.1, and values in the vicinity thereof. The neighborhood value includes, for example, an atomic number ratio of [In]: [M]: [Zn] = 5: 3: 4. The oxide semiconductor having the atomic number ratio shown in the region B is an excellent oxide semiconductor having high crystallinity and high carrier mobility.

The conditions under which the oxide semiconductor forms a layered structure are not uniquely determined by the atomic number ratio. Depending on the atomic number ratio, there are differences in the difficulty of forming a layered structure. On the other hand, even if the atomic number ratio is the same, it may or may not have a layered structure depending on the formation conditions. Therefore, the region shown in the figure is a region showing the atomic number ratio of the oxide semiconductor having a layered structure, and the boundary between the regions A and C is not strict.

Subsequently, a case where the oxide semiconductor is used for a transistor will be described.

By using the oxide semiconductor for the transistor, carrier scattering and the like at the grain boundaries can be reduced, so that a transistor having high field effect mobility can be realized. Moreover, a highly reliable transistor can be realized.

Further, it is preferable to use an oxide semiconductor having a low carrier density for the transistor. For example, oxide semiconductors have a carrier density of less than 8 × 10 ¹¹ / cm ³ , preferably less than 1 × 10 ¹¹ / cm ³ , more preferably less than 1 × 10 ¹⁰ / cm ³ , and 1 × 10 ^-9 /. It may be cm ³ or more.

In addition, since the oxide semiconductor having high purity intrinsicity or substantially high purity intrinsicity has few carrier sources, the carrier density can be lowered. Further, since the oxide semiconductor having high purity intrinsicity or substantially high purity intrinsicity has a low defect level density, the trap level density may also be low.

In addition, the charge captured at the trap level of the oxide semiconductor takes a long time to disappear, and may behave as if it were a fixed charge. Therefore, a transistor in which a channel region is formed in an oxide semiconductor having a high trap level density may have unstable electrical characteristics.

Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. Further, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to reduce the impurity concentration in the adjacent film. Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon and the like.

Here, the influence of each impurity in the oxide semiconductor will be described.

When silicon or carbon, which is one of the Group 14 elements, is contained in the oxide semiconductor, a defect level is formed in the oxide semiconductor. Therefore, the concentration of silicon and carbon in the oxide semiconductor and the concentration of silicon and carbon near the interface with the oxide semiconductor (concentration obtained by Secondary Ion Mass Spectrometry (SIMS)) are set to 2. × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁷ atoms / cm ³ or less.

Further, when the oxide semiconductor contains an alkali metal or an alkaline earth metal, a defect level may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have a normally-on characteristic. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the oxide semiconductor. Specifically, the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is set to 1 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁶ atoms / cm ³ or less.

Further, in an oxide semiconductor, when nitrogen is contained, electrons as carriers are generated, the carrier density increases, and the n-type is easily formed. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have a normally-on characteristic. Therefore, it is preferable that nitrogen is reduced as much as possible in the oxide semiconductor, for example, the nitrogen concentration in the oxide semiconductor is less than 5 × 10 ¹⁹ atoms / cm ^{3 in} SIMS, preferably 5 × 10 ¹⁸ Atoms / cm ³ or less, more preferably 1 × 10 ¹⁸ atoms / cm ³ or less, still more preferably 5 × 10 ¹⁷ atoms / cm ³ or less.

Further, hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to become water, which may form an oxygen deficiency. When hydrogen enters the oxygen deficiency, electrons that are carriers may be generated. In addition, a part of hydrogen may be combined with oxygen that is bonded to a metal atom to generate an electron as a carrier. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have a normally-on characteristic. Therefore, it is preferable that hydrogen in the oxide semiconductor is reduced as much as possible. Specifically, in oxide semiconductors, the hydrogen concentration obtained by SIMS is less than 1 × 10 ²⁰ atoms / cm ³ , preferably less than 1 × 10 ¹⁹ atoms / cm ³ , more preferably 5 × 10 ¹⁸ atoms / cm. Less than ³ , more preferably less than 1 × 10 ¹⁸ atoms / cm ³ .

By using an oxide semiconductor in which impurities are sufficiently reduced in the channel formation region of the transistor, stable electrical characteristics can be imparted.

Subsequently, a case where the oxide semiconductor has a two-layer structure or a three-layer structure will be described. Regarding the band diagram of the insulator in contact with the laminated structure of the oxide semiconductor S1, the oxide semiconductor S2, and the oxide semiconductor S3, and the band diagram of the insulator in contact with the laminated structure of the oxide semiconductor S2 and the oxide semiconductor S3. This will be described with reference to FIG. 29.

FIG. 29A is an example of a band diagram in the film thickness direction of a laminated structure having an insulator I1, an oxide semiconductor S1, an oxide semiconductor S2, an oxide semiconductor S3, and an insulator I2. Further, FIG. 29B is an example of a band diagram in the film thickness direction of the laminated structure having the insulator I1, the oxide semiconductor S2, the oxide semiconductor S3, and the insulator I2. The band diagram shows the energy levels (Ec) of the lower end of the conduction band of the insulator I1, the oxide semiconductor S1, the oxide semiconductor S2, the oxide semiconductor S3, and the insulator I2 for easy understanding.

The oxide semiconductor S1 and the oxide semiconductor S3 have an energy level at the lower end of the conduction band closer to the vacuum level than the oxide semiconductor S2, and typically, the energy level at the lower end of the conduction band of the oxide semiconductor S2 and the energy level. The difference from the energy level at the lower end of the conduction band of the oxide semiconductor S1 and the oxide semiconductor S3 is preferably 0.15 eV or more, 0.5 eV or more, and 2 eV or less, or 1 eV or less. That is, the electron affinity of the oxide semiconductor S2 is larger than the electron affinity of the oxide semiconductor S1 and the oxide semiconductor S3, and the electron affinity of the oxide semiconductor S1 and the oxide semiconductor S3 and the electron affinity of the oxide semiconductor S2 The difference is preferably 0.15 eV or more, 0.5 eV or more, and 2 eV or less, or 1 eV or less.

As shown in FIGS. 29 (A) and 29 (B), in the oxide semiconductor S1, the oxide semiconductor S2, and the oxide semiconductor S3, the energy level at the lower end of the conduction band changes gently. In other words, it can also be said to be continuously changing or continuously joining. In order to have such a band diagram, the defect level density of the mixed layer formed at the interface between the oxide semiconductor S1 and the oxide semiconductor S2 or the interface between the oxide semiconductor S2 and the oxide semiconductor S3 is lowered. It is good to do.

Specifically, the oxide semiconductor S1 and the oxide semiconductor S2, and the oxide semiconductor S2 and the oxide semiconductor S3 have a common element (main component) other than oxygen, so that the defect level density is low. Layers can be formed. For example, when the oxide semiconductor S2 is an In-Ga-Zn oxide semiconductor, In-Ga-Zn oxide semiconductor, Ga-Zn oxide semiconductor, gallium oxide or the like is used as the oxide semiconductor S1 and the oxide semiconductor S3. It is good.

At this time, the main path of the carrier is the oxide semiconductor S2. Since the defect level density at the interface between the oxide semiconductor S1 and the oxide semiconductor S2 and the interface between the oxide semiconductor S2 and the oxide semiconductor S3 can be lowered, the influence of interfacial scattering on carrier conduction is small. High on-current can be obtained.

When electrons are trapped at the trap level, the trapped electrons behave like a fixed charge, and the threshold voltage of the transistor shifts in the positive direction. By providing the oxide semiconductor S1 and the oxide semiconductor S3, the trap level can be kept away from the oxide semiconductor S2. With this configuration, it is possible to prevent the threshold voltage of the transistor from shifting in the positive direction.

The oxide semiconductor S1 and the oxide semiconductor S3 use materials having a sufficiently low conductivity as compared with the oxide semiconductor S2. At this time, the oxide semiconductor S2, the interface between the oxide semiconductor S2 and the oxide semiconductor S1, and the interface between the oxide semiconductor S2 and the oxide semiconductor S3 mainly function as a channel region. For example, for the oxide semiconductor S1 and the oxide semiconductor S3, the oxide semiconductor having the atomic number ratio shown in the region C where the insulating property is high may be used in FIG. 27 (C). The region C shown in FIG. 27 (C) shows the atomic number ratio which is [In]: [M]: [Zn] = 0: 1: 0 or a value in the vicinity thereof.

In particular, when an oxide semiconductor having an atomic number ratio shown in region A is used for the oxide semiconductor S2, the oxide semiconductor S1 and the oxide semiconductor S3 have [M] / [In] of 1 or more, preferably 2 or more. It is preferable to use an oxide semiconductor. Further, as the oxide semiconductor S3, it is preferable to use an oxide semiconductor having [M] / ([Zn] + [In]) of 1 or more, which can obtain sufficiently high insulating properties.

The configuration shown in this embodiment can be used in combination with the configuration shown in other embodiments as appropriate.

(Embodiment 7)
In the present embodiment, an oxide semiconductor material that can be used in one aspect of the present invention will be described.

In the present specification, "parallel" means a state in which two straight lines are arranged at an angle of −10 ° or more and 10 ° or less. Therefore, the case of −5 ° or more and 5 ° or less is also included. Further, "substantially parallel" means a state in which two straight lines are arranged at an angle of −30 ° or more and 30 ° or less. Further, "vertical" means a state in which two straight lines are arranged at an angle of 80 ° or more and 100 ° or less. Therefore, the case of 85 ° or more and 95 ° or less is also included. Further, "substantially vertical" means a state in which two straight lines are arranged at an angle of 60 ° or more and 120 ° or less.

Further, in the present specification, when the crystal is a trigonal crystal or a rhombohedral crystal, it is represented as a hexagonal system.

Oxide semiconductors are divided into single crystal oxide semiconductors and other non-single crystal oxide semiconductors. Examples of the non-single crystal oxide semiconductor include CAAC-OS (c-axis-aligned crystal linear semiconductor), polycrystalline oxide semiconductor, nc-OS (nanocrystalline oxide semiconductor), and pseudoamorphic oxide semiconductor (a-like). : Amorphos-like oxide semiconductor) and amorphous oxide semiconductors.

From another viewpoint, oxide semiconductors are divided into amorphous oxide semiconductors and other crystalline oxide semiconductors. Examples of the crystalline oxide semiconductor include a single crystal oxide semiconductor, CAAC-OS, a polycrystalline oxide semiconductor, and nc-OS.

Amorphous structures are generally isotropic and have no heterogeneous structure, are in a metastable state with unfixed atomic arrangements, have flexible bond angles, have short-range order but long-range order. It is said that it does not have.

That is, a stable oxide semiconductor cannot be called a complete amorphous oxide semiconductor. Further, an oxide semiconductor that is not isotropic (for example, has a periodic structure in a minute region) cannot be called a completely amorphous oxide semiconductor. On the other hand, a-like OS is not isotropic, but has an unstable structure having voids (also referred to as voids). In terms of instability, the a-like OS is physically close to an amorphous oxide semiconductor.

<CAAC-OS>
First, CAAC-OS will be described.

CAAC-OS is a kind of oxide semiconductor having a plurality of c-axis oriented crystal portions (also referred to as pellets).

A case where CAAC-OS is analyzed by X-ray diffraction (XRD: X-Ray Diffraction) will be described. For example, when a structural analysis is performed on a CAAC-OS having crystals of InGaZnO ₄ classified in the space group R-3m by the out-of-plane method, the diffraction angle (2θ) is as shown in FIG. 30 (A). A peak appears near 31 °. Since this peak is attributed to the (009) plane of the InGaZnO ₄ crystal, in CAAC-OS, the crystal has c-axis orientation and the c-axis forms the CAAC-OS film (formed). It can be confirmed that the surface is oriented substantially perpendicular to the surface) or the upper surface. In addition to the peak where 2θ is in the vicinity of 31 °, a peak may appear in the vicinity where 2θ is in the vicinity of 36 °. The peak in which 2θ is in the vicinity of 36 ° is due to the crystal structure classified into the space group Fd-3m. Therefore, it is preferable that CAAC-OS does not show the peak.

On the other hand, when structural analysis is performed by the in-plane method in which X-rays are incident on CAAC-OS from a direction parallel to the surface to be formed, a peak appears in the vicinity of 2θ at 56 °. This peak is attributed to the (110) plane of the InGaZnO ₄ crystal. Then, even if 2θ is fixed in the vicinity of 56 ° and analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis), it is clear as shown in FIG. 30 (B). No peak appears. On the other hand, when 2θ is fixed in the vicinity of 56 ° and φ-scanned with respect to the single crystal InGaZnO ₄ , six peaks attributed to the crystal plane equivalent to the (110) plane are observed as shown in FIG. 30 (C). Will be done. Therefore, from the structural analysis using XRD, it can be confirmed that the orientation of the a-axis and the b-axis of CAAC-OS is irregular.

Next, the CAAC-OS analyzed by electron diffraction will be described. For example, when an electron beam having a probe diameter of 300 nm is incident on a CAAC-OS having a crystal of InGaZnO ₄ in parallel with the surface to be formed of the CAAC-OS, a diffraction pattern (selected area) as shown in FIG. An electron diffraction pattern) may appear. This diffraction pattern includes spots due to the (009) plane of the InGaZnO ₄ crystal. Therefore, it can be seen from the electron diffraction that the pellets contained in CAAC-OS have c-axis orientation and the c-axis is oriented substantially perpendicular to the surface to be formed or the upper surface. On the other hand, FIG. 30 (E) shows a diffraction pattern when an electron beam having a probe diameter of 300 nm is incident on the same sample perpendicularly to the sample surface. From FIG. 30 (E), a ring-shaped diffraction pattern is confirmed. Therefore, it can be seen that the a-axis and b-axis of the pellets contained in CAAC-OS do not have orientation even by electron diffraction using an electron beam having a probe diameter of 300 nm. It is considered that the first ring in FIG. 30 (E) is caused by the (010) plane and the (100) plane of the crystal of InGaZnO ₄ . Further, it is considered that the second ring in FIG. 30 (E) is caused by the surface (110) and the like.

In addition, when observing a composite analysis image (also referred to as a high-resolution TEM image) of a bright-field image of CAAC-OS and a diffraction pattern with a transmission electron microscope (TEM: Transmission Electron Microscope), a plurality of pellets can be confirmed. Can be done. On the other hand, even in a high-resolution TEM image, the boundary between pellets, that is, the grain boundary (also referred to as grain boundary) may not be clearly confirmed. Therefore, it can be said that CAAC-OS is unlikely to cause a decrease in electron mobility due to grain boundaries.

FIG. 31 (A) shows a high-resolution TEM image of a cross section of CAAC-OS observed from a direction substantially parallel to the sample surface. The spherical aberration correction (Spherical Aberration Corrector) function was used for observing the high-resolution TEM image. A high-resolution TEM image using the spherical aberration correction function is particularly called a Cs-corrected high-resolution TEM image. The Cs-corrected high-resolution TEM image can be observed, for example, with an atomic resolution analysis electron microscope JEM-ARM200F manufactured by JEOL Ltd.

From FIG. 31 (A), pellets, which are regions in which metal atoms are arranged in layers, can be confirmed. It can be seen that the size of one pellet is 1 nm or more and 3 nm or more. Therefore, pellets can also be referred to as nanocrystals (nc: nanocrystals). Further, CAAC-OS can also be referred to as an oxide semiconductor having CANC (C-Axis Aligned nanocrystals). The pellets reflect the irregularities on the surface or top surface of the CAAC-OS to be formed and are parallel to the surface or top surface of the CAAC-OS to be formed.

Further, FIGS. 31 (B) and 31 (C) show Cs-corrected high-resolution TEM images of the plane of CAAC-OS observed from a direction substantially perpendicular to the sample surface. 31 (D) and 31 (E) are images obtained by image-processing FIGS. 31 (B) and 31 (C), respectively. The image processing method will be described below. First, an FFT image is acquired by performing a fast Fourier transform (FFT) process on FIG. 31 (B). Then, relative to the origin in the FFT image acquired, for masking leaves a range between 5.0 nm ^-1 from 2.8 nm ^-1. Next, the masked FFT image is subjected to an inverse fast Fourier transform (IFFT) process to obtain an image-processed image. The image obtained in this way is called an FFT filtering image. The FFT filtering image is an image obtained by extracting a periodic component from a Cs-corrected high-resolution TEM image, and shows a grid array.

In FIG. 31 (D), the disordered portion of the lattice arrangement is shown by a broken line. The area surrounded by the broken line is one pellet. The part indicated by the broken line is the connecting portion between the pellets. Since the broken line has a hexagonal shape, it can be seen that the pellet has a hexagonal shape. The shape of the pellet is not limited to a regular hexagonal shape, and is often a non-regular hexagonal shape.

In FIG. 31 (E), a dotted line is shown between the region where the grid arrangement is aligned and the region where another grid arrangement is aligned. A clear grain boundary cannot be confirmed even in the vicinity of the dotted line. By connecting the surrounding grid points around the grid points near the dotted line, a distorted hexagon, pentagon and / or heptagon can be formed. That is, it can be seen that the formation of grain boundaries is suppressed by distorting the lattice arrangement. This is because CAAC-OS can tolerate distortion due to the fact that the atomic arrangement is not dense in the ab plane direction and that the bond distance between atoms changes due to the substitution of metal elements. Conceivable.

As shown above, CAAC-OS has a c-axis orientation and has a distorted crystal structure in which a plurality of pellets (nanocrystals) are connected in the ab plane direction. Therefore, CAAC-OS can also be referred to as an oxide semiconductor having a CAA crystal (c-axis-aligned a-b-plane-anchored crystal).

CAAC-OS is a highly crystalline oxide semiconductor. Since the crystallinity of an oxide semiconductor may decrease due to the mixing of impurities or the formation of defects, CAAC-OS can be said to be an oxide semiconductor having few impurities and defects (oxygen deficiency, etc.).

Impurities are elements other than the main components of oxide semiconductors, such as hydrogen, carbon, silicon, and transition metal elements. For example, an element such as silicon, which has a stronger bond with oxygen than the metal element constituting the oxide semiconductor, disturbs the atomic arrangement of the oxide semiconductor by depriving the oxide semiconductor of oxygen and lowers the crystallinity. It becomes a factor. Further, heavy metals such as iron and nickel, argon, carbon dioxide, and the like have a large atomic radius (or molecular radius), which disturbs the atomic arrangement of the oxide semiconductor and causes a decrease in crystallinity.

<Nc-OS>
Next, the nc-OS will be described.

The case where the nc-OS is analyzed by XRD will be described. For example, when structural analysis is performed on nc-OS by the out-of-plane method, a peak indicating orientation does not appear. That is, the crystals of nc-OS have no orientation.

Further, for example, when nc-OS having a crystal of InGaZnO ₄ is sliced and an electron beam having a probe diameter of 50 nm is incident on a region having a thickness of 34 nm in parallel with the surface to be formed, FIG. 32 (A) shows. A ring-shaped diffraction pattern (nanobeam electron diffraction pattern) as shown is observed. Further, FIG. 32 (B) shows a diffraction pattern (nanobeam electron diffraction pattern) when an electron beam having a probe diameter of 1 nm is incident on the same sample. From FIG. 32 (B), a plurality of spots are observed in the ring-shaped region. Therefore, the order of the nc-OS is not confirmed by injecting an electron beam having a probe diameter of 50 nm, but the order is confirmed by injecting an electron beam having a probe diameter of 1 nm.

Further, when an electron beam having a probe diameter of 1 nm is incident on a region having a thickness of less than 10 nm, an electron diffraction pattern in which spots are arranged in a substantially regular hexagonal shape is observed as shown in FIG. 32 (C). May occur. Therefore, it can be seen that the nc-OS has a highly ordered region, that is, a crystal in a thickness range of less than 10 nm. Since the crystals are oriented in various directions, there are some regions where a regular electron diffraction pattern is not observed.

FIG. 32 (D) shows a Cs-corrected high-resolution TEM image of the cross section of the nc-OS observed from a direction substantially parallel to the surface to be formed. The nc-OS has a region in which a crystal portion can be confirmed, such as a portion indicated by an auxiliary line, and a region in which a clear crystal portion cannot be confirmed in a high-resolution TEM image. The crystal portion contained in nc-OS has a size of 1 nm or more and 10 nm or less, and in particular, it often has a size of 1 nm or more and 3 nm or less. An oxide semiconductor having a crystal portion larger than 10 nm and 100 nm or less may be referred to as a microcrystal oxide semiconductor (micro crystal oxide semiconductor). In the nc-OS, for example, the crystal grain boundary may not be clearly confirmed in a high-resolution TEM image. It should be noted that nanocrystals may have the same origin as pellets in CAAC-OS. Therefore, in the following, the crystal part of nc-OS may be referred to as a pellet.

As described above, the nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). In addition, nc-OS does not show regularity in crystal orientation between different pellets. Therefore, no orientation is observed in the entire film. Therefore, the nc-OS may be indistinguishable from the a-like OS and the amorphous oxide semiconductor depending on the analysis method.

Since the crystal orientation is not regular among pellets (nanocrystals), nc-OS is an oxide semiconductor having RANC (Random Aligned nanocrystals) or an oxide having NANC (Non-Aligned nanocrystals). It can also be called a semiconductor.

nc-OS is an oxide semiconductor having higher regularity than an amorphous oxide semiconductor. Therefore, the defect level density of nc-OS is lower than that of a-like OS and amorphous oxide semiconductors. However, nc-OS does not show regularity in crystal orientation between different pellets. Therefore, nc-OS has a higher defect level density than CAAC-OS.

<A-like OS>
The a-like OS is an oxide semiconductor having a structure between nc-OS and an amorphous oxide semiconductor.

FIG. 33 shows a high-resolution cross-sectional TEM image of the a-like OS. Here, FIG. 33 (A) is a high-resolution cross-sectional TEM image of the a-like OS at the start of electron irradiation. FIG. 33 (B) is a high-resolution cross-sectional TEM image of the a-like OS after irradiation with electrons (e ⁻ ) of 4.3 × 10 ⁸ e ⁻ / nm ² . From FIGS. 33 (A) and 33 (B), it can be seen that in the a-like OS, a striped bright region extending in the vertical direction is observed from the start of electron irradiation. It can also be seen that the shape of the bright region changes after electron irradiation. The bright region is presumed to be a void or a low density region.

Due to its porosity, the a-like OS has an unstable structure. In the following, in order to show that the a-like OS has an unstable structure as compared with CAAC-OS and nc-OS, the structural change due to electron irradiation is shown.

As samples, a-like OS, nc-OS and CAAC-OS are prepared. Both samples are In-Ga-Zn oxides.

First, a high-resolution cross-sectional TEM image of each sample is acquired. According to the high-resolution cross-sectional TEM image, each sample has a crystal part.

The unit cell of the crystal of InGaZnO ₄ has a structure in which a total of 9 layers are stacked in a layered manner in the c-axis direction, which has 3 In-O layers and 6 Ga-Zn-O layers. Are known. The distance between these adjacent layers is about the same as the grid plane distance (also referred to as d value) of the (009) plane, and the value is determined to be 0.29 nm from the crystal structure analysis. Therefore, in the following, the portion where the interval between the lattice fringes is 0.28 nm or more and 0.30 nm or less is regarded as the crystal portion of InGaZnO ₄ . The plaids correspond to the ab planes of the InGaZnO ₄ crystal.

FIG. 34 is an example of investigating the average size of the crystal portions (22 to 30 locations) of each sample. The length of the above-mentioned plaid is defined as the size of the crystal portion. From FIG. 34, it can be seen that in the a-like OS, the crystal portion becomes larger according to the cumulative irradiation amount of electrons related to the acquisition of the TEM image and the like. From FIG. 34, in the initially observed by TEM (also referred to as initial nuclei.) Crystal portion was a size of about 1.2nm and electrons (e ^-) cumulative dose is 4.2 × ¹⁰ 8 ^e of the - / nm ^It can be seen that in No. ² , it has grown to a size of about 1.9 nm. On the other hand, in nc-OS and CAAC-OS, there is no change in the size of the crystal part in the range where the cumulative electron irradiation amount is 4.2 × 10 ⁸ e ⁻ / nm ² from the start of electron irradiation. I understand. From FIG. 34, it can be seen that the sizes of the crystal portions of nc-OS and CAAC-OS are about 1.3 nm and about 1.8 nm, respectively, regardless of the cumulative irradiation amount of electrons. A Hitachi transmission electron microscope H-9000 NAR was used for electron beam irradiation and TEM observation. The electron beam irradiation conditions were an acceleration voltage of 300 kV, a current density of 6.7 × 10 ⁵ e ⁻ / (nm ² · s), and a diameter of the irradiation region of 230 nm.

As described above, in the a-like OS, growth of the crystal portion may be observed by electron irradiation. On the other hand, in nc-OS and CAAC-OS, almost no growth of the crystal portion due to electron irradiation is observed. That is, it can be seen that the a-like OS has an unstable structure as compared with the nc-OS and the CAAC-OS.

Further, since it has a void, the a-like OS has a structure having a lower density than that of the nc-OS and the CAAC-OS. Specifically, the density of a-like OS is 78.6% or more and less than 92.3% of the density of a single crystal having the same composition. Further, the density of nc-OS and the density of CAAC-OS are 92.3% or more and less than 100% of the density of a single crystal having the same composition. It is difficult to form an oxide semiconductor having a density of less than 78% of a single crystal.

For example, in an oxide semiconductor satisfying In: Ga: Zn = 1: 1: 1 [atomic number ratio], the density of the single crystal InGaZnO ₄ having a rhombohedral structure is 6.357 g / cm ³ . Therefore, for example, in an oxide semiconductor satisfying In: Ga: Zn = 1: 1: 1 [atomic number ratio], the density of a-like OS is 5.0 g / cm ³ or more and less than 5.9 g / cm ^3. .. Further, for example, in an oxide semiconductor satisfying In: Ga: Zn = 1: 1: 1 [atomic number ratio], the density of nc-OS and the density of CAAC-OS are 5.9 g / cm ³ or more and 6.3 g /. It is less than cm ³ .

When single crystals having the same composition do not exist, the density corresponding to the single crystal in the desired composition can be estimated by combining single crystals having different compositions at an arbitrary ratio. The density corresponding to a single crystal having a desired composition may be estimated by using a weighted average with respect to the ratio of combining single crystals having different compositions. However, the density is preferably estimated by combining as few types of single crystals as possible.

As described above, oxide semiconductors have various structures, and each has various characteristics. The oxide semiconductor may be, for example, a laminated film having two or more of amorphous oxide semiconductor, a-like OS, nc-OS, and CAAC-OS.

<Carrier density of oxide semiconductor>
Next, the carrier density of the oxide semiconductor will be described below.

Factors that affect the carrier density of the oxide semiconductor include oxygen deficiency ( _VO ) in the oxide semiconductor, impurities in the oxide semiconductor, and the like.

When the oxygen vacancies in the oxide semiconductor is increased, when the hydrogen to the oxygen deficiency linked (this state is also referred to as V _{O H),} the higher the density of defect states. Alternatively, when the amount of impurities in the oxide semiconductor increases, the defect level density increases due to the impurities. Therefore, the carrier density of the oxide semiconductor can be controlled by controlling the defect level density in the oxide semiconductor.

Here, consider a transistor that uses an oxide semiconductor in the channel region.

When the purpose is to suppress the negative shift of the threshold voltage of the transistor or reduce the off-current of the transistor, it is preferable to lower the carrier density of the oxide semiconductor. When the carrier density of the oxide semiconductor is lowered, the impurity concentration in the oxide semiconductor may be lowered and the defect level density may be lowered. In the present specification and the like, a low impurity concentration and a low defect level density is referred to as high-purity intrinsic or substantially high-purity intrinsic. The carrier density of the high-purity intrinsic oxide semiconductor is less than 8 × 10 ¹⁵ cm ^-3 , preferably less than 1 × 10 ¹¹ cm ^-3 , more preferably less than 1 × 10 ¹⁰ cm ^-3 , and 1 × 10 ^It may be ^-9 cm ^-3 or more.

On the other hand, when the purpose is to improve the on-current of the transistor or the mobility of the electric field effect of the transistor, it is preferable to increase the carrier density of the oxide semiconductor. When the carrier density of the oxide semiconductor is increased, the impurity concentration of the oxide semiconductor may be slightly increased, or the defect level density of the oxide semiconductor may be slightly increased. Alternatively, the bandgap of the oxide semiconductor may be made smaller. For example, an oxide semiconductor having a slightly high impurity concentration or a slightly high defect level density can be regarded as substantially true in the range where the on / off ratio of the Id-Vg characteristic of the transistor can be obtained. Further, an oxide semiconductor having a large electron affinity and a correspondingly small bandgap, resulting in an increase in the density of thermally excited electrons (carriers), can be regarded as substantially genuine. When an oxide semiconductor having a higher electron affinity is used, the threshold voltage of the transistor becomes lower.

The above-mentioned oxide semiconductor having an increased carrier density is slightly n-type. Therefore, an oxide semiconductor having an increased carrier density may be referred to as "Slightly-n".

The carrier density of the substantially intrinsic oxide semiconductor is preferably 1 × 10 ⁵ cm ^-3 or more and less than 1 × 10 ¹⁸ cm ^-3, more preferably 1 × 10 ⁷ cm ^-3 or more and 1 × 10 ¹⁷ cm ^-3 or less. preferably, 1 × ¹⁰ 9 ^{cm -3} or more 5 × ¹⁰ 16 ^{cm -3} and more preferably less, more preferably 1 × ^{10 10 cm -3} or higher than 1 × ¹⁰ 16 ^{cm -3,} 1 × ¹⁰ 11 ^{cm -3} or more It is more preferably 1 × 10 ¹⁵ cm ^-3 or less.

The configuration shown in this embodiment can be used in combination with the configuration shown in other embodiments as appropriate.

(Embodiment 8)
In this embodiment, an example of a package and a module containing an image sensor chip will be described. For the image sensor chip, the configuration of the imaging device according to one aspect of the present invention can be used.

FIG. 35 (A) is an external perspective view of the upper surface side of the package containing the image sensor chip. The package includes a package substrate 610 for fixing the image sensor chip 650, a cover glass 620, an adhesive 630 for adhering both, and the like.

FIG. 35B is an external perspective view of the lower surface side of the package. The lower surface of the package has a BGA (Ball grid array) configuration in which solder balls are bumps 640. In addition, it is not limited to BGA, and may be LGA (Land grid array), PGA (Pin grid array), or the like.

FIG. 35 (C) is a perspective view of the package shown by omitting a part of the cover glass 620 and the adhesive 630, and FIG. 35 (D) is a cross-sectional view of the package. An electrode pad 660 is formed on the package substrate 610, and the electrode pad 660 and the bump 640 are electrically connected to each other via a through hole 680 and a land 685. The electrode pad 660 is electrically connected to the electrode of the image sensor chip 650 by a wire 670.

Further, FIG. 36A is an external perspective view of the upper surface side of the camera module in which the image sensor chip is housed in a lens-integrated package. The camera module includes a package substrate 611 for fixing the image sensor chip 651, a lens cover 621, a lens 635, and the like. Further, an IC chip 690 having functions such as a drive circuit for an image pickup device and a signal conversion circuit is also provided between the package substrate 611 and the image sensor chip 651, and has a configuration as a SiP (System in package). There is.

FIG. 36B is an external perspective view of the lower surface side of the camera module. The lower surface and the four side surfaces of the package substrate 611 have a QFN (Quad flat no-lead package) configuration in which land 641 for mounting is provided. The configuration is an example, and may be a QFP (Quad flat package), the above-mentioned BGA, or the like.

FIG. 36 (C) is a perspective view of the module shown by omitting a part of the lens cover 621 and the lens 635, and FIG. 36 (D) is a cross-sectional view of the camera module. A part of the land 641 is used as an electrode pad 661, and the electrode pad 661 is electrically connected to the electrodes of the image sensor chip 651 and the IC chip 690 by a wire 671.

By housing the image sensor chip in a package having the above-mentioned form, it can be easily mounted and incorporated into various semiconductor devices and electronic devices.

The present embodiment is not limited to the imaging device, and can be applied to other semiconductor devices. For example, the present embodiment can be applied to a storage device.

The configuration shown in this embodiment can be used in combination with the configuration shown in other embodiments as appropriate.

(Embodiment 9)
In the present embodiment, an example of an electronic device to which the imaging device according to one aspect of the present invention can be applied will be described.

As an image pickup device according to one aspect of the present invention and an electronic device capable of using the semiconductor device including the image pickup device, a display device, a personal computer, an image storage device or an image reproduction device provided with a recording medium, a mobile phone, a portable device, etc. Game machines including molds, portable data terminals, electronic book terminals, video cameras, cameras such as digital still cameras, goggle type displays (head mount displays), navigation systems, sound playback devices (car audio, digital audio players, etc.), copying Examples include machines, facsimiles, printers, multifunction printers, automatic cash deposit / payment machines (ATMs), and vending machines. Specific examples of these electronic devices are shown in FIG. 37.

FIG. 37A is a surveillance camera, which includes a housing 701, a lens 702, a support portion 703, and the like. An imaging device according to an aspect of the present invention can be provided as one of the components for acquiring an image in the surveillance camera. It should be noted that the surveillance camera is a conventional name and does not limit its use. For example, a device having a function as a surveillance camera is also called a camera or a video camera.

FIG. 37B is a video camera, which includes a first housing 711, a second housing 712, a display unit 713, an operation key 714, a lens 715, a connection unit 716, and the like. The operation keys 714 and the lens 715 are provided in the first housing 711, and the display unit 713 is provided in the second housing 712. An image pickup device according to an aspect of the present invention can be provided as one of the components for acquiring an image in the video camera.

FIG. 37C is a portable data terminal, which includes a housing 721, a display unit 722, a camera 723, and the like. Information can be input and output by the touch panel function of the display unit 722. An imaging device according to an aspect of the present invention can be provided as one of the components for acquiring an image in the portable data terminal.

FIG. 37 (D) is a wristwatch-type information terminal, which includes a housing 731, a display unit 732, a wristband 733, an operation button 734, a crown 735, a camera 736, and the like. The display unit 732 may be a touch panel. An image pickup device according to an aspect of the present invention can be provided as one of the parts for acquiring an image in the information terminal.

FIG. 37 (E) is a portable game machine, which includes a housing 741, a housing 742, a display unit 743, a display unit 744, a microphone 745, a speaker 746, an operation key 747, a stylus 748, and a camera 794. The portable game machine shown in FIG. 37 (E) has two display units 743 and a display unit 744, but the number of display units of the portable game machine is not limited to this. An image pickup device according to an aspect of the present invention can be provided as one of the parts for acquiring an image in the portable game machine.

FIG. 37 (F) is an inspection device, which includes a housing 751 and a sensor 752. The inspection device can detect scratches generated on the product 754 arranged on the belt conveyor 753, for example. As the sensor 752, the image pickup apparatus of one aspect of the present invention can be used.

The electronic device shown above is not particularly limited as long as the image pickup device according to one aspect of the present invention is provided.

Further, the electronic device shown in the present embodiment does not have to be equipped with the imaging device of one aspect of the present invention, but may be provided with the semiconductor device of one aspect of the present invention. For example, the electronic device shown in the present embodiment may be provided with the storage device of one aspect of the present invention. Further, as long as the semiconductor device according to one aspect of the present invention is provided, the electronic device is not particularly limited as shown above.

This embodiment can be appropriately combined with other embodiments shown herein.

10 Imaging device 11 pixels 12 pixels Array 13 Circuit 14 Circuit 15 Circuit 16 Circuit 16A Circuit 16B Circuit 17 Circuit 17A Circuit 17B Circuit 20 Circuit 21 Transistor 22 Transistor 23 Transistor 24 Transistor 25 Transistor 26 Transistor 27 Wiring 28 Wiring 29 Wiring 30 Circuit 31 Transistor 32 Transistor 33 Transistor 34 Transistor 35 Wiring 36 Wiring 40 Circuit 41 Transistor 42 Transistor 43 Transistor 44 Wiring 45 Wiring 50 Circuit 51 Circuit 52a Circuit 52b Circuit 53 Transistor 53a Transistor 53b Transistor 54 Capacitive element 54a Capacitive element 54b Capacitive element 55 Wiring 56 Wiring 61a Wiring 61b Wiring 62a Wiring 62b Wiring 63a Wiring 63b Wiring 70 Circuit 71 Transistor 72 Transistor 73 Transistor 74 Transistor 75a Wiring 75b Wiring 76 Wiring 77 Wiring 78 Wiring 80 Area 81A Wiring 81B Wiring 82 Wiring 82A Wiring 82B Wiring 83 Wiring 84 Wiring 85 Wiring 401 Transistor 402 Transistor 403 Transistor 404 Transistor 405 Transistor 406 Transistor 407 Transistor 408 Transistor 409 Transistor 410 Transistor 411 Transistor 412 Transistor 413 Transistor 415 Substrate 420 Insulation film 430 Oxide semiconductor film 430a Oxide semiconductor film 430b Oxide semiconductor film 430c Oxide semiconductor film 440 Conductive 441 Conductive 442 Conductive 450 Conductive 451 Conductive 452 Conductive 460 Insulating film 470 Conductive 471 Conductive 472 Conductive 473 Conductive 475 Insulating film 480 Insulating film 531 Region 532 Region 533 Region 534 Region 535 Region 610 Package board 611 Package board 620 Cover glass 621 Lens cover 630 Adhesive 635 Lens 640 Bump 641 Land 650 Image sensor chip 651 Image sensor chip 660 Electrode pad 661 Electrode pad 670 Wire 671 Wire 680 Through hole 685 Land 690 IC chip 701 Housing 702 Lens 703 Support part 711 Housing 712 Housing 713 Display unit 714 Operation key 715 Lens 716 connection Part 721 Housing 722 Display 723 Camera 731 Housing 732 Display 733 Wristband 734 Button 735 Crown 736 Camera 741 Housing 742 Housing 743 Display 744 Display 745 Microphone 746 Speaker 747 Operation key 748 Stylus 749 Camera 751 752 Sensor 753 Belt Conveyor 754 Product

Claims (2)

It has a line buffer that can perform write and read operations.
The line buffer includes a first circuit, a second circuit, a third circuit, and a fourth circuit.
The first circuit, the second circuit, the third circuit, and the fourth circuit are electrically connected to each other by the first wiring.
The first circuit, the second circuit, the third circuit, and the fourth circuit are electrically connected to each other by a second wiring.
The second circuit has a function of storing 1-bit complementary data.
The third circuit has a function of precharging the first wiring and the second wiring.
The fourth circuit has a function of holding the 1-bit complementary data written from the second circuit. The first circuit has a third circuit when the line buffer performs the write operation. It has a function of transferring a signal input from the wiring to the first wiring and transferring a signal input from the fourth wiring to the second wiring.
When the line buffer performs the read operation, the first circuit outputs a signal input from the first wiring to the fifth wiring, and outputs a signal input from the second wiring to the fifth wiring. It has a function to output to the wiring of 6.
The second circuit has a function of writing the complementary data stored in the second circuit to the fourth circuit when the line buffer performs the write operation.
The second circuit, when said line buffer performs the read operation is to have a function of amplifying the complementary data transferred from the fourth circuit,
The transistor contained in the first circuit to the third circuit has silicon in the active layer, and the transistor has silicon.
The transistor included in the fourth circuit has an oxide semiconductor in the active layer and has an oxide semiconductor.
The fourth circuit is a semiconductor device provided so as to be superposed on a region in which the first circuit to the third circuit is formed . In claim 1,
The fourth circuit includes a first transistor, a second transistor, a first capacitive element, and a second capacitive element.
One of the source or drain of the first transistor is electrically connected to the first wire.
The other of the source or drain of the first transistor is electrically connected to one terminal of the first capacitive element.
One of the source or drain of the second transistor is electrically connected to the second wire.
The other of the source or drain of the second transistor is electrically connected to one terminal of the second capacitive element.
The other terminal of the first capacitive element is electrically connected to the other terminal of the second capacitive element.
The first transistor and the second transistor are semiconductor devices having an oxide semiconductor in the active layer.