JP2015179555A - Semiconductor device, electronic component, and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device of a novel structure that achieves reduction in both chip size and production costs.SOLUTION: In a circuit based on an SRAM, such a structure is employed that an OMOS transistor is provided in an inverter loop, and an n channel type transistor comprising an Si transistor in the SRAM is used as the OMOS transistor. According to the structure, when elements in the semiconductor device are made finer, decrease in mobility associated with short channel effect can be suppressed. In addition, when power is supplied, operation equal to that of a normal SRAM can be performed, and when power supply is stopped, data can be held by a gate of the inverter.

Description

One embodiment of the present invention relates to a semiconductor device, an electronic component, and an electronic device.

Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter). Therefore, as a technical field of one embodiment of the present invention disclosed more specifically in this specification, a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, a driving method thereof, or a manufacturing method thereof, Can be cited as an example.

An SRAM (Static Random Access Memory) is used for a cache memory such as a processor in that data can be written / read at a high speed.

Since SRAM is a volatile memory, data is lost when power supply is stopped. Therefore, a configuration in which a transistor using an oxide semiconductor (OS transistor) and a capacitor are added to a semiconductor layer in which a channel is formed is added to the SRAM configuration to prevent data loss (for example, see Patent Document 1). reference).

JP2013-9285A

In a configuration in which an OS transistor and a capacitor are added to a circuit based on SRAM, the chip size is increased, and thus the manufacturing cost is increased. In particular, the capacitor element needs a large area to hold data, and thus increases the cell area.

Thus, an object of one embodiment of the present invention is to provide a semiconductor device or the like having a novel structure that can suppress an increase in chip size. Another object of one embodiment of the present invention is to provide a semiconductor device or the like having a novel structure that can suppress an increase in manufacturing cost. Another object of one embodiment of the present invention is to provide a novel semiconductor device or the like.

Note that the problems of one embodiment of the present invention are not limited to the problems listed above. The problems listed above do not disturb the existence of other problems. Other issues are issues not mentioned in this section, which are described in the following description. Problems not mentioned in this item can be derived from descriptions of the specification or drawings by those skilled in the art, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention solves at least one of the above-described description and / or other problems.

One embodiment of the present invention is a semiconductor device including first to fourth transistors and first and second inverters, and a gate of the first transistor is electrically connected to a first wiring. , One of a source and a drain of the first transistor is electrically connected to the second wiring, and a gate of the second transistor is electrically connected to the first wiring, and the source or the drain of the second transistor One of the drains is electrically connected to the third wiring, the gate of the third transistor is electrically connected to the fourth wiring, and one of the source and the drain of the third transistor is connected to the first wiring The other of the source and the drain of the transistor is electrically connected, the gate of the fourth transistor is electrically connected to the fourth wiring, and one of the source and the drain of the fourth transistor is connected to the second transistor. The first terminal of the first inverter is electrically connected to the other of the source or drain of the third transistor, and the second terminal of the first inverter is electrically connected to the other of the source and drain of the transistor. , Electrically connected to one of a source or a drain of the fourth transistor, and a first terminal of the second inverter is electrically connected to the other of the source or the drain of the fourth transistor, and The second terminal is electrically connected to one of a source and a drain of the third transistor, the first wiring has a function of transmitting a first signal, and the second wiring The third wiring has a function capable of transmitting the third signal, and the fourth wiring has a function capable of transmitting the fourth signal. 1st to 1st The first transistor is an n-channel transistor in which a semiconductor layer includes an oxide semiconductor, and the first signal is set in a conductive state and the potential of the third signal is set to the source of the third transistor or The first signal has a function capable of being applied to one of the drains, and the potential of the fourth signal can be applied to one of the source and the drain of the fourth transistor with the second transistor in a conductive state. And the second signal has a function of making the third transistor conductive and supplying one potential of the source or drain of the third transistor to the first terminal of the first inverter. The second signal turns off the third transistor and keeps the potential of one of the source and drain of the third transistor at the first terminal of the first inverter. And the second signal can set the potential of one of the source and the drain of the fourth transistor to the first terminal of the second inverter with the fourth transistor turned on. The second signal has a function capable of holding the potential of one of the source and the drain of the fourth transistor at the first terminal of the second inverter by making the fourth transistor non-conductive. And a semiconductor device.

Note that other aspects of the present invention are described in the following embodiments and drawings.

One embodiment of the present invention can provide a semiconductor device or the like having a novel structure that can suppress an increase in chip size. Therefore, the semiconductor device can be reduced in size. Alternatively, according to one embodiment of the present invention, a semiconductor device or the like having a novel structure that can suppress an increase in manufacturing cost can be provided. Therefore, the manufacturing cost of the semiconductor device can be reduced. Alternatively, according to one embodiment of the present invention, a novel semiconductor device or the like can be provided.

Note that the effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. The other effects are effects not mentioned in this item described in the following description. Effects not mentioned in this item can be derived from the description of the specification or drawings by those skilled in the art, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention has at least one of the above effects and / or other effects. Accordingly, one embodiment of the present invention may not have the above-described effects depending on circumstances.

FIG. 10 is a circuit diagram illustrating one embodiment of the present invention. FIG. 10 is a circuit diagram illustrating one embodiment of the present invention. 4 is a timing chart for describing one embodiment of the present invention. FIG. 10 is a circuit block diagram illustrating one embodiment of the present invention. FIG. 10 is a circuit diagram illustrating one embodiment of the present invention. FIG. 10 is a circuit diagram illustrating one embodiment of the present invention. FIG. 10 is a circuit diagram illustrating one embodiment of the present invention. FIG. 10 is a circuit diagram illustrating one embodiment of the present invention. FIG. 10 is a circuit diagram illustrating one embodiment of the present invention. FIG. 10 is a circuit diagram illustrating one embodiment of the present invention. Sectional TEM image and local Fourier transform image of an oxide semiconductor. The figure which shows the nano beam electron diffraction pattern of an oxide semiconductor film, and the figure which shows an example of a transmission electron diffraction measuring apparatus. The figure which shows an example of the structural analysis by a transmission electron diffraction measurement, and a plane TEM image. FIG. 6 is a cross-sectional view illustrating one embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating one embodiment of the present invention. The flowchart and perspective schematic diagram which show the manufacturing process of an electronic component. Electronic equipment using electronic components.

Hereinafter, embodiments will be described with reference to the drawings. However, the embodiments can be implemented in many different modes, and it is easily understood by those skilled in the art that the modes and details can be variously changed without departing from the spirit and scope thereof. . Therefore, the present invention should not be construed as being limited to the description of the following embodiments.

In the drawings, the size, the layer thickness, or the region is exaggerated for simplicity in some cases. Therefore, it is not necessarily limited to the scale. The drawings schematically show an ideal example, and are not limited to the shapes or values shown in the drawings. For example, variation in signal, voltage, or current due to noise, variation in signal, voltage, or current due to timing shift can be included.

In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A channel region is provided between the drain (drain terminal, drain region or drain electrode) and the source (source terminal, source region or source electrode), and a current flows through the drain, channel region, and source. It is something that can be done.

Here, since the source and the drain vary depending on the structure or operating conditions of the transistor, it is difficult to limit which is the source or the drain. Therefore, a portion that functions as a source and a portion that functions as a drain are not referred to as a source or a drain, but one of the source and the drain is referred to as a first electrode, and the other of the source and the drain is referred to as a second electrode. There is a case.

Note that the ordinal numbers “first”, “second”, and “third” used in this specification are added to avoid confusion between components, and are not limited in number. To do.

Note that in this specification, A and B are connected to each other, including A and B being directly connected, as well as those being electrically connected. Here, A and B are electrically connected. When there is an object having some electrical action between A and B, it is possible to send and receive electrical signals between A and B. It says that.

Note that for example, the source (or the first terminal) of the transistor is electrically connected to X through (or not through) Z1, and the drain (or the second terminal or the like) of the transistor is connected to Z2. Through (or without), Y is electrically connected, or the source (or the first terminal, etc.) of the transistor is directly connected to a part of Z1, and another part of Z1 Is directly connected to X, and the drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2, and another part of Z2 is directly connected to Y. Then, it can be expressed as follows.

For example, “X and Y, and the source (or the first terminal or the like) and the drain (or the second terminal or the like) of the transistor are electrically connected to each other. The drain of the transistor (or the second terminal, etc.) and the Y are electrically connected in this order. ” Or “the source (or the first terminal or the like) of the transistor is electrically connected to X, the drain (or the second terminal or the like) of the transistor is electrically connected to Y, and X or the source ( Or the first terminal or the like, the drain of the transistor (or the second terminal, or the like) and Y are electrically connected in this order. Or “X is electrically connected to Y through the source (or the first terminal) and the drain (or the second terminal) of the transistor, and X is the source of the transistor (or the first terminal). Terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y are provided in this connection order. By using the same expression method as in these examples and defining the order of connection in the circuit configuration, the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor are separated. Apart from that, the technical scope can be determined. In addition, these expression methods are examples, and are not limited to these expression methods. Here, it is assumed that X, Y, Z1, and Z2 are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, and the like).

Note that in this specification, terms such as “above” and “below” are used for convenience in describing the positional relationship between components with reference to the drawings. Moreover, the positional relationship between components changes suitably according to the direction which draws each structure. Therefore, the present invention is not limited to the words and phrases described in the specification, and can be appropriately rephrased depending on the situation.

In addition, the arrangement of each circuit block in the block diagram in the drawing specifies the positional relationship for the sake of explanation, and even if it is shown that different functions are realized by different circuit blocks, the same circuit block in the actual circuit block In some cases, different functions can be realized. In addition, the function of each circuit block in the drawing is to specify the function for explanation. Even if the function is shown as one circuit block, in an actual circuit block, processing performed by one circuit block is performed by a plurality of circuit blocks. In some cases, it is provided.

(Embodiment 1)
In this embodiment, a circuit diagram of a semiconductor device and a structural example of a timing chart will be described.

In this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Therefore, a RAM (Random Access Memory) including a semiconductor element such as a transistor, a memory cell included in the RAM, a memory circuit, or the like is a semiconductor device.

FIG. 1 is a diagram illustrating a circuit configuration of a memory cell which is a semiconductor device.

The memory cell MC illustrated in FIG. 1 includes a transistor 11, a transistor 12, a transistor 13, a transistor 14, an inverter INV1, and an inverter INV2.

In FIG. 1, a node between the transistor 11, the transistor 13, and the inverter INV2 is illustrated as a node N1. A node between the transistor 12, the transistor 14, and the inverter INV1 is illustrated as a node N2. A node between the transistor 13 and the inverter INV1 is illustrated as a node N3. A node between the transistor 14 and the inverter INV2 is illustrated as a node N4.

Further, the memory cell MC shown in FIG. 1 is provided with a wiring WL for supplying the word signal WS, a wiring MEL for supplying the data holding control signal MES, a wiring BL for supplying the data signal data, and an inverted data signal dataab. A wiring BLB for this purpose is shown.

As an example, the memory cell MC is a memory cell constituting a RAM. The memory cell MC controls the word signal WS and the capacitor word signal CES, is supplied with the potential of the data signal data and the inverted data signal dataab, and data is written therein. The written data is held in the memory cell MC by controlling the data holding control signal MES. In addition, the memory cell MC can control the word signal WS, detect a change in the potential of the wiring BL and the wiring BLB by an external circuit, and read data.

In the configuration of the memory cell MC in FIG. 1, in the circuit based on the SRAM, the transistor 11 and the transistor 12 functioning as switches are OS transistors, and the transistor 13 and the transistor as the OS transistors functioning as switches in the inverter loop. 14 is provided. With this structure, when each element included in the semiconductor device is miniaturized, reduction in mobility associated with the short channel effect can be suppressed. Further, with this configuration, an operation equivalent to that of a normal SRAM can be performed when power is supplied, and data can be held at the gate of the inverter when the power is stopped.

The OS transistor used in the configuration of the memory cell MC in FIG. 1 is an accumulation type transistor using electrons as majority carriers. In this case, an electric field extending from the conductive layer functioning as a source electrode and a drain electrode in contact with the oxide semiconductor layer to the channel formation region can be shielded at a short distance. For this reason, the OS transistor hardly causes a short channel effect. Since the short channel effect does not easily occur, it is not necessary to provide an LDD region. Therefore, the mobility of the OS transistor does not decrease even when the channel length is shortened.

On the other hand, when the Si transistor has a short channel, a short channel effect occurs. In order to suppress this short channel effect, it is necessary to provide an LDD region in the Si transistor. Due to the influence of the LDD region, the mobility of the Si transistor is lowered. Therefore, the configuration of the memory cell MC having the OS transistor can solve the problem that the mobility is reduced when the Si transistor is miniaturized due to the gate length dependency of the mobility.

When the gate length is such that the short channel effect does not appear, if the mobility difference between the Si transistor and the OS transistor is large, it is necessary to design the gate width of the OS transistor larger than that of the Si transistor. On the other hand, the difference in mobility between the Si transistor and the OS transistor becomes small at the gate length where the short channel effect appears by miniaturization. Therefore, the configuration of the memory cell MC having the OS transistor can be designed by making the gate widths of the OS transistor and the Si transistor close to each other.

As a result, the memory cell MC having an OS transistor suppresses a decrease in mobility associated with the short channel effect when each element is miniaturized such that the channel length is greater than 5 nm and less than or equal to 1 μm, preferably greater than 5 nm and less than or equal to 20 nm. be able to. Therefore, an increase in the chip size of the semiconductor device having the memory cell MC can be suppressed. And by suppressing the increase in chip size, the number of chip sizes that can be manufactured from a single substrate increases, so that an increase in manufacturing cost can be suppressed.

Further, the OS transistor used in the configuration of the memory cell MC in FIG. 1 can be a transistor that can obtain an extremely low off-state current in addition to the suppression of the chip size and the increase in manufacturing cost.

The OS transistor used in the structure of the memory cell MC in FIG. 1 can reduce the off-state current by reducing the impurity concentration in the oxide semiconductor and making the oxide semiconductor intrinsic or substantially intrinsic. Here, substantially intrinsic means that the carrier density in the oxide semiconductor is less than 1 × 10 ¹⁷ / cm ³ , preferably less than 1 × 10 ¹⁵ / cm ³ , and more preferably 1 × It indicates less than 10 ¹³ / cm ³ . In an oxide semiconductor, hydrogen, nitrogen, carbon, silicon, and metal elements other than main components are impurities. For example, hydrogen and nitrogen contribute to the formation of donor levels and increase the carrier density.

A transistor including an intrinsic or substantially intrinsic oxide semiconductor has low carrier density, and thus has less electrical characteristics with a negative threshold voltage. In addition, a transistor including the oxide semiconductor has few carrier traps in the oxide semiconductor, and thus has a small change in electrical characteristics and has high reliability. In addition, a transistor including the oxide semiconductor can have extremely low off-state current.

Note that in an OS transistor with a low off-state current, the normalized off-current per channel width of 1 μm at room temperature (about 25 ° C.) is 1 × 10 ⁻¹⁸ A or less, preferably 1 × 10 ⁻²¹ A or less, more preferably ^{May be} 1 × 10 ⁻²⁴ A or less, or 1 × 10 ⁻¹⁵ A or less at 85 ° C., preferably 1 × 10 ⁻¹⁸ A or less, and more preferably 1 × 10 ⁻²¹ A or less.

Note that in the case of an n-channel transistor, off-state current refers to a current that flows between a source and a drain when the transistor is off. If the threshold voltage of the n-channel transistor is, for example, about 0 V to 2 V, the current flowing between the source and the drain when the voltage applied between the gate and the source is a negative voltage is referred to as an off current. be able to.

As a result, the memory cell MC including the OS transistor can be a transistor from which an extremely low off-state current can be obtained. Therefore, even when the OS transistor is turned off and power supply is stopped, charge can be held in the memory cell MC. And it can be in the state before stopping power supply by restarting power supply according to the held electric charge.

In addition, the OS transistor used in the configuration of the memory cell MC in FIG. 1 has a good switching characteristic in addition to a reduction in chip size, and thus an increase in manufacturing cost, and a transistor with an extremely low off-state current. The resulting transistor can be obtained.

Note that the OS transistor used in the structure of the memory cell MC in FIG. 1 is a transistor formed over an insulating surface. Therefore, unlike the case where a semiconductor substrate is used as it is as a channel formation region like a Si transistor, no parasitic capacitance is formed between the gate electrode and the body or the semiconductor substrate. Therefore, when an OS transistor is used, carriers can be easily controlled by a gate electric field, and good switching characteristics can be obtained.

In addition, since the OS transistor used in the configuration of the memory cell MC of FIG. 1 can suppress the short channel effect described above, it is necessary to form a thin gate insulating film that has been taken to suppress the short channel effect in the Si transistor. There is no. Therefore, the OS transistor can be formed with a thick gate insulating film, and a reduction in parasitic capacitance can be expected. Further, the OS transistor does not need to be provided with the LDD region described above. Therefore, further reduction of parasitic capacitance can be expected.

As described above, since the formation of parasitic capacitance can be suppressed, in the transistors 11 to 14 functioning as switches in the memory cell MC in FIG. 1, the gate capacitance can be reduced. Therefore, the field-through effect that occurs when the transistors 11 to 14 are turned off can be made difficult to appear.

For the transistors 13 and 14 connected to the inverters INV1 and INV2, the decrease in potential due to the field-through effect is the ratio of the gate potential by the ratio of the holding capacity (gate capacity of the inverter) and the gate capacity of the transistors 13 and 14. Decline is decided. Therefore, the field through effect can be reduced in the memory cell MC of FIG. 1 in which the gate capacitances of the transistors 13 and 14 are reduced.

As a result, the memory cell MC having the OS transistor can reduce various capacitances parasitic on the transistor when each element is miniaturized. Therefore, it is not necessary to add an element such as adding a storage capacitor for suppressing the field through effect, and an increase in the chip size of the semiconductor device having the memory cell MC can be suppressed.

Next, each configuration of the memory cell MC will be described. Note that in the circuit diagram described with reference to the drawings, an OS symbol is also illustrated to indicate an OS transistor.

The gate of the transistor 11 is connected to the wiring WL. One of the source and the drain of the transistor 11 is connected to the wiring BL. The other of the source and the drain of the transistor 11 is connected to one of the source and the drain of the transistor 13, that is, the node N1.

The transistor 12 has a gate connected to the wiring WL. One of the source and the drain of the transistor 12 is connected to the wiring BLB. The other of the source and the drain of the transistor 12 is connected to one of the source and the drain of the transistor 14, that is, the node N2.

A word signal WS given to the wiring WL is a signal for controlling the conduction state of the transistors 11 and 12. In this specification, the transistors 11 and 12 are described as n-channel transistors. Therefore, when the word signal WS is at an H level potential, the transistors 11 and 12 are turned on. When the word signal WS is at an L level potential, the transistors 11 and 12 are turned off. The word signal WS is also referred to as a first signal.

The data signal “data” given to the wiring BL is a signal based on data written to the memory cell MC. Further, the inverted data signal “datab” given to the wiring BL is a signal obtained by inverting the data signal “data”. For example, the data signal “data” is an H level potential if the data is “1”, and an L level potential if the data is “0”. For example, the inverted data signal “datab” is an L level potential if the data is “1”, and an H level potential if the data is “0”. The data signal data is also referred to as a third signal. The inverted data signal dataab is also referred to as a fourth signal.

The data signal data is given to the node N1 through the transistor 11. The inverted data signal dataab is given to the node N2 through the transistor 12.

The word signal WS has a function capable of turning on the transistor 11 and supplying the potential of the data signal data to one of the source and the drain of the transistor 13, and the potential of the inverted data signal dataab in the transistor 14 with the transistor 12 turned on. It has a function that can be given to either the source or the drain.

The word signal WS makes the transistors 11 and 12 conductive when data is written. The word signal WS turns on the transistors 11 and 12 when reading data. The word signal WS turns off the transistors 11 and 12 except when data is written and read.

The gate of the transistor 13 is connected to the wiring MEL. One of the source and the drain of the transistor 13 is connected to the other of the source and the drain of the transistor 11, that is, the node N1. The other of the source and the drain of the transistor 13 is connected to the first terminal (also referred to as an input terminal) of the inverter INV1, that is, the node N3.

The gate of the transistor 14 is connected to the wiring MEL. One of the source and the drain of the transistor 14 is connected to the other of the source and the drain of the transistor 12, that is, the node N2. The other of the source and the drain of the transistor 14 is connected to the first terminal of the inverter INV2, that is, the node N4.

The inverter INV1 has a first terminal connected to the other of the source and the drain of the transistor 13, that is, the node N3. The inverter INV1 has a second terminal (also referred to as an output terminal) connected to one of the source and the drain of the transistor 14, that is, the node N2.

The inverter INV2 has a first terminal connected to the other of the source and the drain of the transistor 14, that is, the node N4. The inverter INV1 has a second terminal connected to one of the source and the drain of the transistor 13, that is, the node N1.

The storage control signal MES given to the wiring MEL is a signal for controlling the conduction state of the transistors 13 and 14. In this specification, the transistors 13 and 14 are described as n-channel transistors. Therefore, when the storage control signal MES is at an H level potential, the transistors 13 and 14 are turned on, and when the storage control signal MES is at an L level potential, the transistors 13 and 14 are turned off. The storage control signal MES is also referred to as a second signal.

The memory control signal MES has a function of allowing the transistor 13 to be in a conductive state and supplying one potential of the source or drain of the transistor 13 to the first terminal of the inverter INV1, and the source of the transistor 13 to be in a non-conductive state. Or a function of holding one potential of the drain at the first terminal of the inverter INV1. In addition, the memory control signal MES has a function of turning on the transistor 14 and supplying one of the source and drain potentials of the transistor 14 to the first terminal of the inverter INV2, and setting the transistor 14 in a non-conductive state. And holding the potential of one of the source and drain at the first terminal of the inverter INV2.

The storage control signal MES makes the transistors 13 and 14 conductive during a period in which power supply is continuously performed. By making the transistors 13 and 14 conductive, the inverters INV1 and INV2 can function in the same manner as an inverter loop included in the SRAM. Therefore, a circuit having a function equivalent to that of a circuit used in an SRAM can be used as a circuit for writing data and a circuit for reading data.

In addition, the storage control signal MES turns off the transistors 13 and 14 during a period in which the power supply is stopped. By setting the transistors 13 and 14 to a non-conducting state, electric charge corresponding to the potential of the node N3 is held at the node N3. The potential of the node N3 is held even when power supply is stopped by the gate capacitance of the transistor included in the inverter INV1 and the transistor 13 with low off-state current. Therefore, the written data can be held in the memory cell MC even during the period when the power supply is stopped.

The stop of the power supply in the memory cell MC is to stop the power supply to the inverters INV1 and INV2. For example, FIG. 2 shows a diagram in which a wiring VHL for applying a potential VH and a wiring VLL for applying a potential VL (<VH) are added to the inverters INV1 and INV2 shown in FIG. In FIG. 2, in a period in which power supply is continuously performed, the wiring VHL is set to the potential VH and the wiring VLL is set to VL. Further, in a period in which power supply is stopped, the wiring VHL and the wiring VLL are equipotential. Note that the potential VH may be VDD and the potential VL may be VSS or GND.

As described above, in the structure of the memory cell MC in FIGS. 1 and 2, when each element included in the semiconductor device is miniaturized, a decrease in mobility due to the short channel effect can be suppressed. By switching the storage control signal MES depending on whether or not power is supplied, it is possible to switch between the operation equivalent to that of a normal SRAM and the data holding operation at high speed. 1 and FIG. 2 includes an OS transistor, so that in addition to suppressing the chip size and thus suppressing an increase in manufacturing cost, and a transistor capable of obtaining an extremely low off-state current, it is favorable. A transistor having switching characteristics can be obtained.

Next, the operation of the memory cell MC shown in FIG. 2 in which the wirings VHL and VLL are additionally shown in FIG. 1 will be described. FIG. 3 shows a timing chart of signals and node potentials input and output in the circuit diagram shown in FIG. 2 during normal operation.

Note that FIG. 3 illustrates changes in potentials of the data signal data, the inverted data signal dataab, the word signal WS, the storage control signal MES, the nodes N1 to N4, the wiring VHL, and the wiring VLL illustrated in FIG. In FIG. 3, times T1 to T9 are given for explanation. A data writing operation is shown from time T1 to T3, a data saving operation is shown from time T3 to T4, a power stop operation is shown from time T4 to T5, a data restoration operation is shown from time T5 to T7, and a data reading operation is shown from time T6 to T9.

In FIG. 3, data to be written to the memory cell MC is represented as “d [0] / db [0]”. “D [0] / db [0]” is illustrated as a data signal “data” / inverted data signal “datab” written with a potential of data “0”. The case where data “1” is written to and read from the memory cell MC is not described because the potential is only inverted.

Note that the potential of each signal and each wiring shown in FIG. 3 is switched between an H level potential VH and an L level potential VL for the sake of explanation. In the following description, switching to the H level or L level will be described, and switching to another potential will be described as necessary.

First, at time T1, the write operation of data “0” is started. Since the write operation is performed at the H level of the storage control signal MES, the write operation is equivalent to a normal SRAM.

At time T1, the word signal WS and the storage control signal MES are set to the H level. The transistors 11, 12, 13, and 14 are turned on, and the nodes N1 to N4 have potentials corresponding to the data “0”. Note that power supply is continued by setting the wiring VHL to the H level and the wiring VLL to the L level.

At time T2, the operation of writing data “0” is completed.

At time T2, the word signal WS is set to L level and the storage control signal MES is set to H level. The transistors 11 and 12 are in a non-conducting state, the transistors 13 and 14 are in a conducting state, and the data “0” of the node N1 is held in the inverter loop by the inverters INV1 and INV2. Note that power supply is continued by setting the wiring VHL to the H level and the wiring VLL to the L level.

At time T3, an operation of saving data is started so that the data “0” can be held even when the power supply is stopped.

At time T3, the word signal WS and the storage control signal MES are set to L level. The transistors 11, 12, 13, and 14 are turned off, and the nodes N1 to N4 have potentials corresponding to the data “0”. Note that power supply is continued by setting the wiring VHL to the H level and the wiring VLL to the L level. Note that the data signal data / inverted data signal dataab is set to the L level because data is not written or read.

At time T4, power supply is stopped and data “0” is held.

At time T4, the word signal WS and the storage control signal MES are set to the L level. The transistors 11, 12, 13, and 14 are turned off, the nodes N1 and N2 are indefinite values (indicated as “unknown” in the figure), and the nodes N3 and N4 are at a potential corresponding to the data “0”. Note that the power supply is stopped by setting the wirings VHL and VLL to the L level.

By keeping the transistors 13 and 14 in a non-conductive state, the memory cell MC can hold a potential corresponding to data. Note that a predetermined voltage may be continuously supplied to the transistors 13 and 14 in a period in which a potential corresponding to data is held. For example, the gates of the transistors 13 and 14 may be continuously supplied with a voltage that completely turns off the transistors. Alternatively, there is a case where a voltage at which the transistor threshold voltage is shifted and the transistor is in a normally-off state is continuously supplied to the back gate of the transistor. In such a case, the voltage is supplied in the case of the memory cell MC in the period for retaining the information, but almost no electric current is consumed because almost no current flows. Therefore, since power is hardly consumed, even if a predetermined voltage is supplied to the memory cell MC, the memory cell MC can be substantially expressed as being non-volatile.

At time T5, power supply is resumed.

At time T5, the word signal WS and the storage control signal MES are set to L level. The transistors 11, 12, 13, and 14 are turned off, and the nodes N1 to N4 have potentials corresponding to the data “0”. Note that power supply is resumed by setting the wiring VHL to the H level and the wiring VLL to the L level.

At time T6, the inverters INV1 and INV2 resume holding data “0” in the inverter loop.

At time T6, the word signal WS is set to L level and the storage control signal MES is set to H level. The transistors 11 and 12 are in a non-conducting state, the transistors 13 and 14 are in a conducting state, and the data “0” of the node N1 is held in the inverter loop by the inverters INV1 and INV2. Note that power supply is continued by setting the wiring VHL to the H level and the wiring VLL to the L level.

At time T7, a precharge operation for reading data “0” is started. Since the precharge operation and the read operation are performed at the storage control signal MES at the H level, the operations are the same as those of a normal SRAM.

At time T7, the word signal WS is set to L level and the storage control signal MES is set to H level. The data signal data / inverted data signal dataab is precharged to an intermediate potential between the potentials Vh and VL in order to read data. The transistors 11 and 12 are in a non-conducting state, the transistors 13 and 14 are in a conducting state, and the data “0” of the node N1 is held in the inverter loop by the inverters INV1 and INV2. Note that power supply is continued by setting the wiring VHL to the H level and the wiring VLL to the L level.

At time T8, the operation of reading data “0” starts.

At time T8, the word signal WS and the storage control signal MES are set to the H level. The transistors 11, 12, 13, and 14 are turned on, and the nodes N1 to N4 have potentials corresponding to the data “0”. Note that power supply is continued by setting the wiring VHL to the H level and the wiring VLL to the L level. The wiring BL and the wiring BLB are switched from the precharged potential to the potential corresponding to the data “0”. For example, if the data is “0”, it is L level, and if the data is “1”, it is H level.

At time T9, the operation of reading data “0” is completed. The word signal WS is set to L level and the storage control signal MES is set to H level. The transistors 11 and 12 are in a non-conductive state, the transistors 13 and 14 are in a conductive state, and the data “0” of the node N1 is held in the inverter loop by the inverters INV1 and INV2. Note that power supply is continued by setting the wiring VHL to the H level and the wiring VLL to the L level.

In the operation of the memory cell MC described above, an operation equivalent to that of a normal SRAM can be performed while the power supply is continuously performed, and data once written can be held during a period in which the power supply is stopped. In addition, in the configuration of the memory cell MC in FIGS. 1 and 2, when each element included in the semiconductor device is miniaturized, a decrease in mobility due to the short channel effect can be suppressed. By switching the storage control signal MES depending on whether or not power is supplied, it is possible to switch between the operation equivalent to that of a normal SRAM and the data holding operation at high speed.

Note that the memory cells MC can be a RAM including semiconductor elements such as transistors by being arranged in a matrix.

FIG. 4 is a block diagram showing a configuration example of a RAM having the memory cell MC described in FIG. Since the memory cell MC is a circuit having an OS transistor, the RAM is shown as OS-SRAM in FIG.

An OS-SRAM 110 illustrated in FIG. 4 includes a memory cell array MCA in which a plurality of memory cells MC described in FIG. 1 are provided, a row selection driver 111, and a column selection driver 112. Note that the OS-SRAM 110 includes memory cells MC provided in a matrix of m rows and n columns (m and n are natural numbers of 2 or more).

In FIG. 4, the wirings WL [0] to [m−1], the wirings MEL [0] to [m−1], the wirings BL [0] to [n−1], and the wirings BLB [0] to [n− 1], a wiring VHL and a wiring VLL are shown.

The row selection driver 111 has a function of supplying a word signal to the wirings WL [0] to [m−1] connected to the memory cell MC and a storage control signal MES to the wirings MEL [0] to [m−1]. It is. The row selection driver 111 is a circuit that applies a signal to each wiring, and may be simply referred to as a circuit.

The row selection driver 111 may be a circuit that outputs the word signal WS at the H level during data writing and reading, and the L level during other periods. The row selection driver 111 may be a circuit that outputs the storage control signal MES at the L level when power supply is stopped and the H level during other periods. Note that power supply may be stopped by setting the potentials of the wiring VHL and the wiring VLL to be equal.

The column selection driver 112 may be a circuit that outputs a data signal data to the wiring BL and an inversion data to the wiring BLB when writing data. In addition, the column selection driver 112 may be configured to output a data signal read out to the wiring BL by applying a precharge potential to the wiring BLB and using a circuit such as a sense amplifier when reading data. The column selection driver 112 is a circuit that applies a signal or a potential to each wiring, and may be simply referred to as a circuit.

Each memory cell MC is connected to the wiring VHL and the wiring VLL, and is supplied with potentials VH and VL generated by the power supply circuit.

This embodiment can be implemented in appropriate combination with any of the other embodiments.

(Embodiment 2)
In the present embodiment, a modified example of the memory cell MC described with reference to FIGS. 1 and 2 will be described.

1 and 2, the inverters INV1 and INV2 are indicated by circuit symbols in FIGS. 1 and 2, but a p-channel transistor formed using a Si transistor and an n-channel transistor formed using an OS transistor are combined. A CMOS inverter may be used.

Specifically, as shown in FIG. 5, the inverters INV1 and INV2 are formed by transistors 15 and 17 which are p-channel transistors and transistors 16 and 18 which are n-channel transistors. Further, with the structure shown in FIG. 5, since the Si transistor and the OS transistor can be stacked, the chip size can be further reduced.

Although FIG. 5 shows a configuration in which the inverters INV1 and INV2 are CMOS inverters, a resistance load type inverter may be used.

Specifically, as shown in FIG. 6, inverters INV1 and INV2 are formed by resistance elements 19 and 20 and transistors 16 and 18 which are n-channel transistors. In addition, with the configuration shown in FIG. 6, a memory cell can be formed using an OS transistor, so that the manufacturing process can be further reduced.

Although one embodiment of the present invention has been described with reference to FIGS. 1 and 2 as a circuit functioning as an SRAM, the present invention can also be applied to a circuit functioning as a latch.

Specifically, as shown in FIG. 7, the transistor 12 and the wiring BLB are omitted from the circuit configuration of FIG. As shown in FIG. 7, the circuit configuration according to one embodiment of the present invention can be operated by extracting a part of the circuit.

Although one embodiment of the present invention is described as a circuit functioning as an SRAM in FIGS. 1 and 2, the invention can also be applied to a circuit functioning as a flip-flop.

Specifically, as shown in FIG. 8, the transistors 11 and 12, the wiring WL, the wiring BL, and the wiring BLB are omitted from the circuit configuration of FIG. 5, and a clocked inverter 21 is added. As shown in FIG. 8, the circuit configuration according to one embodiment of the present invention can be operated by extracting a part of the circuit and adding another circuit.

1 and 2, the wiring to be connected to the memory cell MC is described with the minimum configuration, but even a wiring for supplying a signal having the same function is connected to the memory cell MC as a different wiring. be able to.

Specifically, as illustrated in FIG. 9, the wiring MEL having the circuit configuration illustrated in FIG. 5 is the wirings MEL1 and MEL2, and the storage control signals MES1 and MES2 are supplied. The storage control signals MES1 and MES2 may be signals that perform the same control or signals that perform different controls. As shown in FIG. 9, the circuit structure according to one embodiment of the present invention can be divided into a plurality of structures having the same function.

5 may be a transistor having a back gate (also referred to as a second gate) in the transistors 11 to 14 in FIG. For example, as illustrated in FIG. 10, the transistors 11 to 14 in FIG. 5 may be transistors 11_BG to 14_BG having back gates.

This embodiment can be implemented in appropriate combination with any of the other embodiments.

(Embodiment 3)
In this embodiment, an oxide semiconductor layer that can be used for the semiconductor layer of the transistor with low off-state current described in the above embodiment will be described.

An oxide semiconductor used for a channel formation region in the semiconductor layer of the transistor preferably contains at least indium (In) or zinc (Zn). In particular, it is preferable to contain In and Zn. In addition to these, it is preferable to have a stabilizer that strongly binds oxygen. The stabilizer may include at least one of gallium (Ga), tin (Sn), zirconium (Zr), hafnium (Hf), and aluminum (Al).

As other stabilizers, lanthanoids such as lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb) , Dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), or lutetium (Lu).

Examples of the oxide semiconductor used as the semiconductor layer of the transistor include indium oxide, tin oxide, zinc oxide, In—Zn oxide, Sn—Zn oxide, Al—Zn oxide, and Zn—Mg oxide. Sn-Mg oxide, In-Mg oxide, In-Ga oxide, In-Ga-Zn oxide (also referred to as IGZO), In-Al-Zn oxide, In-Sn -Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, Sn-Al-Zn oxide, In-Hf-Zn oxide, In-Zr-Zn oxide In-Ti-Zn-based oxide, In-Sc-Zn-based oxide, In-Y-Zn-based oxide, In-La-Zn-based oxide, In-Ce-Zn-based oxide, In-Pr- Zn-based oxide, In-Nd-Zn-based oxide, In-Sm Zn-based oxide, In-Eu-Zn-based oxide, In-Gd-Zn-based oxide, In-Tb-Zn-based oxide, In-Dy-Zn-based oxide, In-Ho-Zn-based oxide, In-Er-Zn-based oxide, In-Tm-Zn-based oxide, In-Yb-Zn-based oxide, In-Lu-Zn-based oxide, In-Sn-Ga-Zn-based oxide, In-Hf -Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al-Zn oxide, In-Sn-Hf-Zn oxide, In-Hf-Al-Zn oxide There are things.

  For example, In: Ga: Zn = 1: 1: 1, In: Ga: Zn = 3: 1: 2, or In: Ga: Zn = 2: 1: 3 atomic ratio In—Ga—Zn-based oxidation An oxide in the vicinity of the product or its composition may be used.

  When a large amount of hydrogen is contained in the oxide semiconductor film included in the semiconductor layer, a part of the hydrogen serves as a donor and an electron serving as a carrier is generated by bonding with the oxide semiconductor. As a result, the threshold voltage of the transistor shifts in the negative direction. Therefore, after the oxide semiconductor film is formed, dehydration treatment (dehydrogenation treatment) is performed to remove hydrogen or moisture from the oxide semiconductor film so that impurities are contained as little as possible. preferable.

  Note that oxygen may be reduced from the oxide semiconductor film due to dehydration treatment (dehydrogenation treatment) of the oxide semiconductor film. Therefore, it is preferable to perform treatment in which oxygen is added to the oxide semiconductor film in order to fill oxygen vacancies increased by dehydration treatment (dehydrogenation treatment) of the oxide semiconductor film. In this specification and the like, the case where oxygen is supplied to the oxide semiconductor film may be referred to as oxygenation treatment or peroxygenation treatment, or oxygen contained in the oxide semiconductor film is determined from a stoichiometric composition. The case where the amount is increased is sometimes referred to as a peroxygenation treatment.

In this manner, the oxide semiconductor film is made i-type (intrinsic) or i-type by removing hydrogen or moisture by dehydration treatment (dehydrogenation treatment) and filling oxygen vacancies by oxygenation treatment. An oxide semiconductor film that is substantially i-type (intrinsic) can be obtained. Note that substantially intrinsic means that the number of carriers derived from a donor in the oxide semiconductor film is extremely small (near zero), and the carrier density is 1 × 10 ¹⁷ / cm ³ or less, 1 × 10 ¹⁶ / cm ³ or less, It means 1 × 10 ¹⁵ / cm ³ or less, 1 × 10 ¹⁴ / cm ³ or less, and 1 × 10 ¹³ / cm ³ or less.

As described above, a transistor including an i-type or substantially i-type oxide semiconductor film can achieve extremely excellent off-state current characteristics. For example, the drain current when the transistor including an oxide semiconductor film is off is 1 × 10 ⁻¹⁸ A or less, preferably 1 × 10 ⁻²¹ A or less, more preferably 1 at room temperature (about 25 ° C.). × 10 ⁻²⁴ A or less, or 1 × 10 ⁻¹⁵ A or less, preferably 1 × 10 ⁻¹⁸ A or less, more preferably 1 × 10 ⁻²¹ A or less at 85 ° C. Note that an off state of a transistor means a state where a gate voltage is sufficiently lower than a threshold voltage in the case of an n-channel transistor. Specifically, when the gate voltage is 1 V or higher, 2 V or higher, or 3 V or lower than the threshold voltage, the transistor is turned off.

An oxide semiconductor film includes an oxide semiconductor having a single crystal structure (hereinafter referred to as a single crystal oxide semiconductor), an oxide semiconductor having a polycrystalline structure (hereinafter referred to as a polycrystalline oxide semiconductor), and a microcrystalline structure. One or more of an oxide semiconductor (hereinafter referred to as a microcrystalline oxide semiconductor) and an oxide semiconductor having an amorphous structure (hereinafter referred to as an amorphous oxide semiconductor) may be used. The oxide semiconductor film may be a CAAC-OS film. The oxide semiconductor film may be formed using an amorphous oxide semiconductor and an oxide semiconductor having crystal grains. As typical examples, a CAAC-OS and a microcrystalline oxide semiconductor are described below.

First, the CAAC-OS film is described.

The CAAC-OS film is one of oxide semiconductor films having a plurality of c-axis aligned crystal parts.

When the CAAC-OS film is observed with a transmission electron microscope (TEM), a clear boundary between crystal parts, that is, a grain boundary (also referred to as a grain boundary) cannot be confirmed. Therefore, it can be said that the CAAC-OS film is unlikely to decrease in electron mobility due to crystal grain boundaries.

When the CAAC-OS film is observed by TEM (cross-sectional TEM observation) from a direction substantially parallel to the sample surface, it can be confirmed that metal atoms are arranged in layers in the crystal part. Each layer of metal atoms has a shape reflecting unevenness of a surface (also referred to as a formation surface) or an upper surface on which the CAAC-OS film is formed, and is arranged in parallel with the formation surface or the upper surface of the CAAC-OS film. .

On the other hand, when the CAAC-OS film is observed by TEM (planar TEM observation) from a direction substantially perpendicular to the sample surface, it can be confirmed that metal atoms are arranged in a triangular shape or a hexagonal shape in the crystal part. However, there is no regularity in the arrangement of metal atoms between different crystal parts.

FIG. 11A is a cross-sectional TEM image of the CAAC-OS film. FIG. 11 (b) is a cross-sectional TEM image obtained by further enlarging FIG. 11 (a), and the atomic arrangement is highlighted for easy understanding.

FIG. 11C is a local Fourier transform image of a circled region (diameter approximately 4 nm) between A-O-A ′ in FIG. From FIG. 11C, the c-axis orientation can be confirmed in each region. Further, since the direction of the c-axis is different between A-O and O-A ′, it is suggested that the grains are different. Further, it can be seen that the angle of the c-axis continuously changes little by little, such as 14.3 °, 16.6 °, and 26.4 ° between A and O. Similarly, it can be seen that the angle of the c-axis continuously changes little by little between −18.3 °, −17.6 °, and −15.9 ° between O and A ′.

Note that when electron diffraction is performed on the CAAC-OS film, spots (bright spots) indicating orientation are observed. For example, when electron diffraction (also referred to as nanobeam electron diffraction) using an electron beam of 1 nm to 30 nm is performed on the top surface of the CAAC-OS film, spots are observed (see FIG. 12A).

From the cross-sectional TEM observation and the planar TEM observation, it is found that the crystal part of the CAAC-OS film has orientation.

Note that most crystal parts included in the CAAC-OS film fit in a cube whose one side is less than 100 nm. Therefore, the case where a crystal part included in the CAAC-OS film fits in a cube whose one side is less than 10 nm, less than 5 nm, or less than 3 nm is included. Note that a plurality of crystal parts included in the CAAC-OS film may be connected to form one large crystal region. For example, in a planar TEM image, a crystal region that is 2500 nm ² or more, 5 μm ² or more, or 1000 μm ² or more may be observed.

When structural analysis is performed on a CAAC-OS film using an X-ray diffraction (XRD) apparatus, for example, in the analysis of a CAAC-OS film having an InGaZnO ₄ crystal by an out-of-plane method, A peak may appear when the diffraction angle (2θ) is around 31 °. Since this peak is attributed to the (009) plane of the InGaZnO ₄ crystal, the CAAC-OS film crystal has c-axis orientation, and the c-axis is in a direction substantially perpendicular to the formation surface or the top surface. Can be confirmed.

On the other hand, when the CAAC-OS film is analyzed by an in-plane method in which X-rays are incident from a direction substantially perpendicular to the c-axis, a peak may appear when 2θ is around 56 °. This peak is attributed to the (110) plane of the InGaZnO ₄ crystal. In the case of a single crystal oxide semiconductor film of InGaZnO ₄ , when 2θ is fixed in the vicinity of 56 ° and analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis), Six peaks attributed to the crystal plane equivalent to the (110) plane are observed. On the other hand, in the case of a CAAC-OS film, a peak is not clearly observed even when φ scan is performed with 2θ fixed at around 56 °.

From the above, in the CAAC-OS film, the orientation of the a-axis and the b-axis is irregular between different crystal parts, but the c-axis is aligned, and the c-axis is a normal line of the formation surface or the top surface. It can be seen that the direction is parallel to the vector. Therefore, each layer of metal atoms arranged in a layer shape confirmed by the above-mentioned cross-sectional TEM observation is a plane parallel to the ab plane of the crystal.

Note that the crystal part is formed when a CAAC-OS film is formed or when crystallization treatment such as heat treatment is performed. As described above, the c-axis of the crystal is oriented in a direction parallel to the normal vector of the formation surface or the top surface of the CAAC-OS film. Therefore, for example, when the shape of the CAAC-OS film is changed by etching or the like, the c-axis of the crystal may not be parallel to the normal vector of the formation surface or the top surface of the CAAC-OS film.

In the CAAC-OS film, the distribution of c-axis aligned crystal parts is not necessarily uniform. For example, in the case where the crystal part of the CAAC-OS film is formed by crystal growth from the vicinity of the upper surface of the CAAC-OS film, the ratio of the crystal part in which the region near the upper surface is c-axis aligned than the region near the formation surface May be higher. In addition, in the CAAC-OS film to which an impurity is added, a region to which the impurity is added may be changed, and a region having a different ratio of a partially c-axis aligned crystal part may be formed.

Note that when the CAAC-OS film including an InGaZnO ₄ crystal is analyzed by an out-of-plane method, a peak may also appear when 2θ is around 36 ° in addition to the peak where 2θ is around 31 °. A peak at 2θ of around 36 ° indicates that a crystal having no c-axis alignment is included in part of the CAAC-OS film. The CAAC-OS film preferably has a peak at 2θ of around 31 ° and no peak at 2θ of around 36 °.

The CAAC-OS film is an oxide semiconductor film with a low impurity concentration. The impurity is an element other than the main component of the oxide semiconductor film, such as hydrogen, carbon, silicon, or a transition metal element. In particular, an element such as silicon, which has a stronger bonding force with oxygen than the metal element included in the oxide semiconductor film, disturbs the atomic arrangement of the oxide semiconductor film by depriving the oxide semiconductor film of oxygen, and has crystallinity. It becomes a factor to reduce. In addition, heavy metals such as iron and nickel, argon, carbon dioxide, and the like have large atomic radii (or molecular radii). Therefore, if they are contained inside an oxide semiconductor film, the atomic arrangement of the oxide semiconductor film is disturbed, resulting in crystallinity. It becomes a factor to reduce. Note that the impurity contained in the oxide semiconductor film might serve as a carrier trap or a carrier generation source.

The CAAC-OS film is an oxide semiconductor film with a low density of defect states. For example, oxygen vacancies in the oxide semiconductor film can serve as carrier traps or can generate carriers by capturing hydrogen.

A low impurity concentration and a low density of defect states (small number of oxygen vacancies) is called high purity intrinsic or substantially high purity intrinsic. A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has few carrier generation sources, and thus can have a low carrier density. Therefore, a transistor including the oxide semiconductor film rarely has electrical characteristics (also referred to as normally-on) in which the threshold voltage is negative. A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has few carrier traps. Therefore, a transistor including the oxide semiconductor film has a small change in electrical characteristics and has high reliability. Note that the charge trapped in the carrier trap of the oxide semiconductor film takes a long time to be released, and may behave as if it were a fixed charge. Therefore, a transistor including an oxide semiconductor film with a high impurity concentration and a high density of defect states may have unstable electrical characteristics.

In addition, a transistor including a CAAC-OS film has little variation in electrical characteristics due to irradiation with visible light or ultraviolet light.

Next, a microcrystalline oxide semiconductor film is described.

In the microcrystalline oxide semiconductor film, there is a case where a crystal part cannot be clearly confirmed in an observation image using a TEM. In most cases, a crystal part included in the microcrystalline oxide semiconductor film has a size of 1 nm to 100 nm, or 1 nm to 10 nm. In particular, an oxide semiconductor film including a nanocrystal (nc) that is a microcrystal of 1 nm to 10 nm, or 1 nm to 3 nm is referred to as an nc-OS (nanocrystalline Oxide Semiconductor) film. In the nc-OS film, for example, a crystal grain boundary may not be clearly confirmed in an observation image using a TEM.

The nc-OS film has periodicity in atomic arrangement in a very small region (eg, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In addition, the nc-OS film does not have regularity in crystal orientation between different crystal parts. Therefore, orientation is not seen in the whole film. Therefore, the nc-OS film may not be distinguished from an amorphous oxide semiconductor film depending on an analysis method. For example, when structural analysis is performed on the nc-OS film using an XRD apparatus using X-rays having a diameter larger than that of the crystal part, a peak indicating a crystal plane is not detected in the analysis by the out-of-plane method. Further, when electron diffraction (also referred to as limited-field electron diffraction) using an electron beam with a probe diameter (for example, 50 nm or more) larger than that of the crystal part is performed on the nc-OS film, a diffraction pattern such as a halo pattern is observed. Is done. On the other hand, when nanobeam electron diffraction is performed on the nc-OS film using an electron beam having a probe diameter that is close to or smaller than the size of the crystal part, spots are observed. In addition, when nanobeam electron diffraction is performed on the nc-OS film, a region with high luminance may be observed so as to draw a circle (in a ring shape). Further, when nanobeam electron diffraction is performed on the nc-OS film, a plurality of spots may be observed in the ring-shaped region (see FIG. 12B).

The nc-OS film is an oxide semiconductor film that has higher regularity than an amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower density of defect states than the amorphous oxide semiconductor film. Note that the nc-OS film does not have regularity in crystal orientation between different crystal parts. Therefore, the nc-OS film has a higher density of defect states than the CAAC-OS film.

Note that the oxide semiconductor film may be a stacked film including two or more of an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, and a CAAC-OS film, for example.

In the case where the oxide semiconductor film has a plurality of structures, the structure analysis may be possible by using nanobeam electron diffraction.

12C shows an electron gun chamber 70, an optical system 72 below the electron gun chamber 70, a sample chamber 74 below the optical system 72, an optical system 76 below the sample chamber 74, and an optical system 76. 1 shows a transmission electron diffraction measurement apparatus having an observation room 80 below, a camera 78 installed in the observation room 80, and a film chamber 82 below the observation room 80. The camera 78 is installed toward the inside of the observation room 80. Note that the film chamber 82 may not be provided.

FIG. 12D shows an internal structure of the transmission electron diffraction measurement apparatus shown in FIG. Inside the transmission electron diffraction measurement apparatus, electrons emitted from the electron gun installed in the electron gun chamber 70 are irradiated to the substance 88 arranged in the sample chamber 74 through the optical system 72. The electrons that have passed through the substance 88 are incident on the fluorescent plate 92 installed inside the observation chamber 80 via the optical system 76. On the fluorescent plate 92, a transmission electron diffraction pattern can be measured by the appearance of a pattern corresponding to the intensity of incident electrons.

The camera 78 is installed facing the fluorescent screen 92 and can capture a pattern that appears on the fluorescent screen 92. The angle formed between the center of the lens of the camera 78 and the straight line passing through the center of the fluorescent plate 92 and the upper surface of the fluorescent plate 92 is, for example, 15 ° to 80 °, 30 ° to 75 °, or 45 ° to 70 °. The following. The smaller the angle, the greater the distortion of the transmission electron diffraction pattern captured by the camera 78. However, if the angle is known in advance, the distortion of the obtained transmission electron diffraction pattern can be corrected. The camera 78 may be installed in the film chamber 82 in some cases. For example, the camera 78 may be installed in the film chamber 82 so as to face the incident direction of the electrons 84. In this case, a transmission electron diffraction pattern with little distortion can be taken from the back surface of the fluorescent plate 92.

In the sample chamber 74, a holder for fixing the substance 88 as a sample is installed. The holder is structured to transmit electrons passing through the substance 88. The holder may have a function of moving the substance 88 to the X axis, the Y axis, the Z axis, and the like, for example. The movement function of the holder may have an accuracy of moving in the range of 1 nm to 10 nm, 5 nm to 50 nm, 10 nm to 100 nm, 50 nm to 500 nm, 100 nm to 1 μm, and the like. These ranges may be set to optimum ranges depending on the structure of the substance 88.

Next, a method for measuring a transmission electron diffraction pattern of a substance using the above-described transmission electron diffraction measurement apparatus will be described.

For example, as shown in FIG. 12D, it is possible to confirm how the structure of the substance changes by changing (scanning) the irradiation position of the electron 84 that is a nanobeam in the substance. At this time, when the substance 88 is a CAAC-OS film, a diffraction pattern as illustrated in FIG. Alternatively, when the substance 88 is an nc-OS film, a diffraction pattern as illustrated in FIG.

By the way, even when the substance 88 is a CAAC-OS film, a diffraction pattern which is partially the same as that of the nc-OS film or the like may be observed. Therefore, the quality of the CAAC-OS film can be expressed by a ratio of a region where a diffraction pattern of the CAAC-OS film is observed in a certain range (also referred to as a CAAC conversion rate) in some cases. For example, in the case of a high-quality CAAC-OS film, the CAAC conversion ratio is 50% or more, preferably 80% or more, more preferably 90% or more, and more preferably 95% or more. Note that the ratio of a region where a diffraction pattern different from that of the CAAC-OS film is observed is referred to as a non-CAAC conversion rate.

As an example, a transmission electron diffraction pattern was acquired while scanning the upper surface of each sample having a CAAC-OS film immediately after film formation (denoted as-sputtered) or after 450 ° C. heat treatment in an atmosphere containing oxygen. . Here, the diffraction pattern was observed while scanning at a speed of 5 nm / second for 60 seconds, and the observed diffraction pattern was converted into a still image every 0.5 seconds, thereby deriving the CAAC conversion rate. As the electron beam, a nano beam having a probe diameter of 1 nm was used. The same measurement was performed on 6 samples. And the average value in 6 samples was used for calculation of CAAC conversion rate.

The CAAC conversion rate in each sample is shown in FIG. The CAAC conversion rate of the CAAC-OS film immediately after deposition was 75.7% (non-CAAC conversion rate was 24.3%). The CAAC conversion rate of the CAAC-OS film after heat treatment at 450 ° C. was 85.3% (non-CAAC conversion rate was 14.7%). It can be seen that the CAAC conversion rate after 450 ° C. heat treatment is higher than that immediately after the film formation. That is, it can be seen that the heat treatment at a high temperature (for example, 400 ° C. or higher) reduces the non-CAAC conversion rate (the CAAC conversion rate increases). Further, it can be seen that a CAAC-OS film having a high CAAC conversion rate can be obtained by heat treatment at less than 500 ° C.

Here, most of the diffraction patterns different from those of the CAAC-OS film were the same as those of the nc-OS film. Further, the amorphous oxide semiconductor film could not be confirmed in the measurement region. Accordingly, it is suggested that the region having a structure similar to that of the nc-OS film is rearranged and affected by the influence of the structure of the adjacent region due to the heat treatment.

13B and 13C are planar TEM images of the CAAC-OS film immediately after film formation and after heat treatment at 450 ° C. Comparison between FIG. 13B and FIG. 13C indicates that the CAAC-OS film after heat treatment at 450 ° C. has a more uniform film quality. That is, it can be seen that heat treatment at a high temperature improves the quality of the CAAC-OS film.

When such a measurement method is used, the structure analysis of an oxide semiconductor film having a plurality of structures may be possible.

Note that the structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 4)
In this embodiment, an example of a cross-sectional structure of a transistor used for a semiconductor device according to one embodiment of the disclosed invention will be described with reference to drawings.

FIG. 14 illustrates an example of part of a cross-sectional structure of a circuit portion according to one embodiment of the present invention. Note that FIG. 14 illustrates a cross-sectional structure of the transistor 13 and the transistor 15 illustrated in FIG. 5 of Embodiment 2 as an example. Note that a region indicated by a broken line A1-A2 indicates the structure of the transistors 13 and 15 in the channel length direction, and a region indicated by a broken line A3-A4 indicates the structure of the transistors 13 and 15 in the channel width direction. Show. Note that in one embodiment of the present invention, the channel length direction of the transistor 13 and the channel length direction of the transistor 15 do not necessarily match.

Note that the channel length direction means a direction in which carriers move at the shortest distance between a pair of impurity regions functioning as a source region and a drain region, and the channel width direction is a direction perpendicular to the channel length direction. means.

FIG. 14 illustrates the case where the transistor 13 having a channel formation region in an oxide semiconductor film is formed over the transistor 15 having a channel formation region in a single crystal silicon substrate. With the structure in FIG. 14, a part of the transistors, for example, the channel formation region of the transistor included in the inverter INV1 or INV2, and the channel formation region of the transistor 11, 12, 13, or 14 are provided to overlap each other. Can do. Alternatively, with the structure shown in FIG. 14, a part of the transistors, for example, the channel formation region of the transistor 15 or 17 and the channel formation region of the transistor 11, 12, 13, 14, 16, or 18 are provided to overlap each other. be able to. Therefore, the layout area of the semiconductor device can be reduced as the structure.

The transistor 15 may have a channel formation region in a semiconductor film or a semiconductor substrate such as silicon or germanium that is amorphous, microcrystalline, polycrystalline, or single crystal. Alternatively, the transistor 15 may include a channel formation region in the oxide semiconductor film or the oxide semiconductor substrate. In the case where all transistors have a channel formation region in an oxide semiconductor film or an oxide semiconductor substrate, the transistor 13 does not have to be stacked over the transistor 15, and the transistor 13 and the transistor 15 are the same layer. It may be formed.

In the case where the transistor 15 is formed using a silicon thin film, amorphous silicon produced by a vapor deposition method such as a plasma CVD method or a sputtering method, or amorphous silicon is formed on the thin film by a process such as laser annealing. Crystallized polycrystalline silicon, single crystal silicon in which hydrogen ions or the like are implanted into a single crystal silicon wafer and a surface layer portion is peeled off can be used.

As the substrate 400 over which the transistor 15 is formed, for example, a silicon substrate, a germanium substrate, a silicon germanium substrate, or the like can be used. FIG. 14 illustrates the case where a single crystal silicon substrate is used as the substrate 400.

The transistor 15 is electrically isolated by an element isolation method. As an element isolation method, a trench isolation method (STI method: Shallow Trench Isolation) or the like can be used. FIG. 14 illustrates a case where the transistor 15 is electrically isolated using a trench isolation method. Specifically, in FIG. 14, an insulating material containing silicon oxide or the like is embedded in a trench formed in the substrate 400 by etching or the like, and then the insulating material is partially removed by etching or the like. The case where the transistor 15 is isolated by the element isolation region 401 is illustrated.

In addition, an impurity region 402 and an impurity region 403 of the transistor 15 and a channel formation region 404 sandwiched between the impurity region 402 and the impurity region 403 are provided on the convex portion of the substrate 400 that exists in a region other than the trench. . Further, the transistor 15 includes an insulating film 405 that covers the channel formation region 404 and a gate electrode 406 that overlaps with the channel formation region 404 with the insulating film 405 interposed therebetween.

In the transistor 15, the side and upper portions of the protrusions in the channel formation region 404 overlap with the gate electrode 406 with the insulating film 405 interposed therebetween, so that the transistor 15 can cover a wide range including the side and upper portions of the channel formation region 404. A career flows. Therefore, the amount of carrier movement in the transistor 15 can be increased while keeping the exclusive area of the transistor 15 on the substrate small. As a result, the transistor 15 has an increased on-current and an increased field effect mobility. In particular, when the length in the channel width direction (channel width) of the protrusion in the channel formation region 404 is W and the film thickness of the protrusion in the channel formation region 404 is T, this corresponds to the ratio of the film thickness T to the channel width W. When the aspect ratio is high, the range in which carriers flow is wider, so that the on-state current of the transistor 15 can be increased and the field-effect mobility can be further increased.

In the case of the transistor 15 using a bulk semiconductor substrate, the aspect ratio is preferably 0.5 or more, and more preferably 1 or more.

An insulating film 411 is provided over the transistor 15. An opening is formed in the insulating film 411. In the opening, an impurity region 402, a conductive film 412 and a conductive film 413 electrically connected to the impurity region 403, and a conductive film 414 electrically connected to the gate electrode 406, Is formed.

The conductive film 412 is electrically connected to the conductive film 416 formed over the insulating film 411, and the conductive film 413 is electrically connected to the conductive film 417 formed over the insulating film 411. The conductive film 414 is electrically connected to the conductive film 418 formed over the insulating film 411.

An insulating film 420 is provided over the conductive films 416 to 418. An insulating film 421 having a blocking effect for preventing diffusion of oxygen, hydrogen, and water is provided over the insulating film 420. The insulating film 421 has a higher blocking effect as the density is higher and denser, and as the insulating film 421 is chemically stable with fewer dangling bonds. As the insulating film 421 having a blocking effect for preventing diffusion of oxygen, hydrogen, and water, for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, or the like is used. be able to. As the insulating film 421 having a blocking effect for preventing diffusion of hydrogen and water, for example, silicon nitride, silicon nitride oxide, or the like can be used.

An insulating film 422 is provided over the insulating film 421, and the transistor 13 is provided over the insulating film 422.

The transistor 13 includes a semiconductor film 430 including an oxide semiconductor over the insulating film 422, a conductive film 432 and a conductive film 433 that are electrically connected to the semiconductor film 430 and function as a source electrode or a drain electrode, a semiconductor film A gate insulating film 431 covering 430 and a gate electrode 434 which overlaps with the semiconductor film 430 with the gate insulating film 431 interposed therebetween. Note that an opening is provided in the insulating films 420 to 422, and the conductive film 433 is connected to the conductive film 418 in the opening.

Note that in FIG. 14, the transistor 13 may have at least the gate electrode 434 on one side of the semiconductor film 430, but further includes a gate electrode that overlaps with the semiconductor film 430 with the insulating film 422 interposed therebetween. May be.

When the transistor 13 includes a pair of gate electrodes, a signal for controlling a conduction state or a non-conduction state is given to one gate electrode, and a potential is given to the other gate electrode from the other. You may be in the state. In this case, a pair of gate electrodes may be given the same potential, or a fixed potential such as a ground potential may be given only to the other gate electrode. By controlling the level of the potential applied to the other gate electrode, the threshold voltage of the transistor can be controlled.

FIG. 14 illustrates the case where the transistor 13 has a single gate structure having one channel formation region corresponding to one gate electrode 434. However, the transistor 13 may have a multi-gate structure in which a plurality of channel electrodes are formed in one active layer by including a plurality of electrically connected gate electrodes.

Further, as illustrated in FIG. 14, the transistor 13 illustrates the case where the semiconductor film 430 includes oxide semiconductor films 430 a to 430 c which are sequentially stacked over the insulating film 422. Note that in one embodiment of the present invention, the semiconductor film 430 included in the transistor 13 may be a single metal oxide film.

The insulating film 422 is preferably an insulating film having a function of supplying part of oxygen to the oxide semiconductor films 430a to 430c by heating. The insulating film 422 preferably has few defects. Typically, the density of a spin having g = 2.001 derived from a dangling bond of silicon obtained by ESR measurement is 1 × 10 ¹⁸ spins / It is preferable that it is cm ³ or less.

The insulating film 422 is preferably an oxide because it has a function of supplying part of the oxygen to the oxide semiconductor films 430a to 430c by heating, for example, aluminum oxide, magnesium oxide, or silicon oxide. Silicon oxynitride, silicon nitride oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and the like can be used. The insulating film 422 can be formed by a plasma CVD (Chemical Vapor Deposition) method, a sputtering method, or the like.

Note that in this specification, oxynitride refers to a material having a higher oxygen content than nitrogen as its composition, and nitride oxide refers to a material having a higher nitrogen content than oxygen as its composition. Point to.

Note that the transistor 13 illustrated in FIGS. 14A to 14C includes an end portion of the oxide semiconductor film 430b where a channel region is formed, which does not overlap with the conductive films 432 and 433, in other words, the conductive film 432 and the conductive film. An end portion located in a region different from the region where 433 is located and the gate electrode 434 overlap with each other. When the end portion of the oxide semiconductor film 430b is exposed to plasma by etching for forming the end portion, chlorine radicals, fluorine radicals, and the like generated from the etching gas are formed with metal elements included in the oxide semiconductor. Easy to combine. Therefore, oxygen bonded to the metal element is likely to be released at the end portion of the oxide semiconductor film, so that an oxygen vacancy is formed and the n-type is easily formed. However, in the transistor 13 illustrated in FIGS. 14A and 14B, the end portion of the oxide semiconductor film 430b which does not overlap with the conductive film 432 and the conductive film 433 overlaps with the gate electrode 434; therefore, by controlling the potential of the gate electrode 434, The electric field applied to the end portion can be controlled. Therefore, the current flowing between the conductive films 432 and 433 through the end portion of the oxide semiconductor film 430b can be controlled by the potential applied to the gate electrode 434. Such a structure of the transistor 13 is referred to as a Surrounded Channel (S-Channel) structure.

Specifically, in the case of the S-Channel structure, when a potential at which the transistor 13 is turned off is applied to the gate electrode 434, an off-current that flows between the conductive film 432 and the conductive film 433 through the end portion is reduced. It can be kept small. Therefore, in the transistor 13, the channel length is shortened in order to obtain a large on-state current. As a result, even if the length between the conductive film 432 and the conductive film 433 at the end portion of the oxide semiconductor film 430 b is shortened, the transistor 13 off-current can be kept small. Therefore, by shortening the channel length, the transistor 13 can obtain a large on-state current when turned on, and can keep the off-state current small when turned off.

Specifically, in the case of the S-Channel structure, when a potential at which the transistor 13 is turned on is applied to the gate electrode 434, current flowing between the conductive films 432 and 433 through the end portion. Can be increased. The current contributes to an increase in field effect mobility and on-current of the transistor 13. The end portion of the oxide semiconductor film 430b and the gate electrode 434 overlap with each other, so that a region where carriers flow in the oxide semiconductor film 430b is not only near the interface of the oxide semiconductor film 430b near the gate insulating film 431. Since carriers flow in a wide range of the oxide semiconductor film 430b, the amount of carrier movement in the transistor 13 increases. As a result, the on-state current of the transistor 13 is increased and the field effect mobility is increased. Typically, the field effect mobility is 10 cm ² / V · s or more, and further 20 cm ² / V · s or more. Note that the field-effect mobility here is not an approximate value of mobility as a physical property value of the oxide semiconductor film but an index of current driving force in the saturation region of the transistor and is an apparent field-effect mobility. .

Note that although described with reference to FIG. 14, one embodiment of the present invention is not limited to this. For example, a structure as shown in FIG.

Note that the structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 5)
The conductive film and the semiconductor film disclosed in the above embodiment can be formed by a sputtering method, but may be formed by another method, for example, a thermal CVD method. As an example of the thermal CVD method, an MOCVD (Metal Organic Chemical Deposition) method or an ALD (Atomic Layer Deposition) method may be used.

The thermal CVD method has an advantage that no defect is generated due to plasma damage because it is a film forming method that does not use plasma.

In the thermal CVD method, the inside of the chamber may be under atmospheric pressure or reduced pressure, and the source gas and the oxidant may be simultaneously sent into the chamber, reacted in the vicinity of the substrate or on the substrate, and deposited on the substrate. .

Further, in the ALD method, film formation may be performed by setting the inside of the chamber to atmospheric pressure or reduced pressure, sequentially introducing source gases for reaction into the chamber, and repeating the order of introducing the gases. For example, each switching valve (also referred to as a high-speed valve) is switched to supply two or more types of source gases to the chamber in order, so that a plurality of types of source gases are not mixed with the first source gas at the same time or thereafter. An active gas (such as argon or nitrogen) is introduced, and a second source gas is introduced. When the inert gas is introduced at the same time, the inert gas becomes a carrier gas, and the inert gas may be introduced at the same time when the second raw material gas is introduced. Further, instead of introducing the inert gas, the second raw material gas may be introduced after the first raw material gas is exhausted by evacuation. The first source gas is adsorbed on the surface of the substrate to form a first monoatomic layer, reacts with a second source gas introduced later, and the second monoatomic layer becomes the first monoatomic layer. A thin film is formed by being stacked on the atomic layer. By repeating this gas introduction sequence a plurality of times until the desired thickness is achieved, a thin film having excellent step coverage can be formed. Since the thickness of the thin film can be adjusted by the number of times the gas introduction sequence is repeated, precise film thickness adjustment is possible, which is suitable for manufacturing a fine FET.

Thermal CVD methods such as the MOCVD method and the ALD method can form the conductive film and the semiconductor film disclosed in the embodiments described so far, for example, when an InGaZnO _x (X> 0) film is formed. For this, trimethylindium, trimethylgallium, and diethylzinc are used. Note that the chemical formula of trimethylindium is In (CH ₃ ) ₃ . The chemical formula of trimethylgallium is Ga (CH ₃ ) ₃ . The chemical formula of dimethylzinc is Zn (CH ₃ ) ₂ . Moreover, it is not limited to these combinations, Triethylgallium (chemical formula Ga (C ₂ H ₅ ) ₃ ) can be used instead of trimethylgallium, and diethylzinc (chemical formula Zn (C ₂ H ₅ ) is used instead of diethylzinc. ₂ ) can also be used.

For example, in the case where a tungsten film is formed by a film forming apparatus using ALD, an initial tungsten film is formed by repeatedly introducing WF ₆ gas and B ₂ H ₆ gas successively, and then WF ₆ gas and H _2. Gases are simultaneously introduced to form a tungsten film. Note that SiH ₄ gas may be used instead of B ₂ H ₆ gas.

For example, in the case where an oxide semiconductor film, for example, an InGaZnO _x (X> 0) film is formed by a film formation apparatus using ALD, In (CH ₃ ) ₃ gas and O ₃ gas are sequentially introduced and InO is sequentially introduced. _Two layers are formed, and then Ga (CH ₃ ) ₃ gas and O ₃ gas are simultaneously introduced to form a GaO layer, and then Zn (CH ₃ ) ₂ and O ₃ gas are simultaneously introduced to form a ZnO layer. Form. Note that the order of these layers is not limited to this example. Alternatively, a mixed compound layer such as an InGaO ₂ layer, an InZnO ₂ layer, a GaInO layer, a ZnInO layer, or a GaZnO layer may be formed by mixing these gases. Incidentally, O ₃ may be used of H _{2 O} gas obtained by bubbling with an inert gas such as Ar in place of the gas, but better to use an O ₃ gas containing no H are preferred. Further, In (C ₂ H ₅ ) ₃ gas may be used instead of In (CH ₃ ) ₃ gas. Further, Ga (C ₂ H ₅ ) ₃ gas may be used instead of Ga (CH ₃ ) ₃ gas. Alternatively, Zn (CH ₃ ) ₂ gas may be used.

As described above, the structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

(Embodiment 6)
In this embodiment, an example in which the semiconductor device described in any of the above embodiments is applied to an electronic component and an example in which the semiconductor device is applied to an electronic device including the electronic component will be described with reference to FIGS.

FIG. 16A illustrates an example in which the semiconductor device described in the above embodiment is applied to an electronic component. Note that the electronic component is also referred to as a semiconductor package or an IC package. This electronic component has a plurality of standards and names depending on the terminal take-out direction and the shape of the terminal. Therefore, in this embodiment, an example will be described.

A semiconductor device including a transistor as shown in FIG. 14 of the above-described fourth embodiment is completed by assembling a plurality of detachable components on a printed board through an assembly process (post-process).

The post-process can be completed through each process shown in FIG. Specifically, after the element substrate obtained in the previous process is completed (step S1), the back surface of the substrate is ground (step S2). This is because by reducing the thickness of the substrate at this stage, it is possible to reduce the warpage of the substrate in the previous process and to reduce the size of the component.

A dicing process is performed in which the back surface of the substrate is ground to separate the substrate into a plurality of chips. Then, a die bonding process is performed in which the separated chips are individually picked up and mounted on the lead frame and bonded (step S3). For the bonding between the chip and the lead frame in this die bonding process, a suitable method is appropriately selected according to the product, such as bonding with a resin or bonding with a tape. The die bonding step may be mounted on the interposer and bonded.

Next, wire bonding is performed in which the lead of the lead frame and the electrode on the chip are electrically connected by a thin metal wire (wire) (step S4). A silver wire or a gold wire can be used as the metal thin wire. For wire bonding, ball bonding or wedge bonding can be used.

The wire-bonded chip is subjected to a molding process that is sealed with an epoxy resin or the like (step S5). By performing the molding process, the inside of the electronic component is filled with resin, which can reduce damage to the built-in circuit part and wires due to mechanical external force, and can reduce deterioration of characteristics due to moisture and dust. it can.

Next, the lead of the lead frame is plated. Then, the lead is cut and molded (step S6). By this plating treatment, rusting of the lead can be prevented, and soldering when mounting on a printed circuit board can be performed more reliably.

Next, a printing process (marking) is performed on the surface of the package (step S7). An electronic component is completed through a final inspection process (step S8) (step S9).

The electronic component described above can include the semiconductor device described in the above embodiment. Therefore, an electronic component that is reduced in size and cost can be realized.

A perspective schematic view of the completed electronic component is shown in FIG. FIG. 16B shows a schematic perspective view of a QFP (Quad Flat Package) as an example of an electronic component. An electronic component 700 illustrated in FIG. 16B illustrates a lead 701 and a circuit portion 703. An electronic component 700 illustrated in FIG. 16B is mounted on a printed circuit board 702, for example. A plurality of such electronic components 700 are combined and each is electrically connected on the printed circuit board 702 so that the electronic component 700 can be mounted inside the electronic device. The completed circuit board 704 is provided inside an electronic device or the like.

Next, electronic devices such as computers, portable information terminals (including mobile phones, portable game machines, sound playback devices, etc.), electronic paper, television devices (also referred to as televisions or television receivers), digital video cameras, etc. A case where the above-described electronic component is applied will be described.

FIG. 17A illustrates a portable information terminal including a housing 901, a housing 902, a first display portion 903a, a second display portion 903b, and the like. At least part of the housing 901 and the housing 902 is provided with an electronic component including the semiconductor device described in the above embodiment. Therefore, a portable information terminal that is reduced in size and cost is realized.

Note that the first display portion 903a is a panel having a touch input function. For example, as illustrated in the left diagram of FIG. 17A, a selection button 904 displayed on the first display portion 903a displays “touch input”. "Or" keyboard input "can be selected. Since the selection buttons can be displayed in various sizes, a wide range of people can feel ease of use. Here, for example, when “keyboard input” is selected, a keyboard 905 is displayed on the first display portion 903a as shown in the right diagram of FIG. As a result, as in the conventional information terminal, quick character input by key input and the like are possible.

In addition, in the portable information terminal illustrated in FIG. 17A, one of the first display portion 903a and the second display portion 903b can be removed as illustrated in the right diagram of FIG. . The second display portion 903b is also a panel having a touch input function, and can be further reduced in weight when carried, and can be operated with the other hand while holding the housing 902 with one hand. is there.

FIG. 17A illustrates a function for displaying various information (still images, moving images, text images, and the like), a function for displaying a calendar, date, time, or the like on the display unit, and operating or editing information displayed on the display unit. A function, a function of controlling processing by various software (programs), and the like can be provided. In addition, an external connection terminal (such as an earphone terminal or a USB terminal), a recording medium insertion portion, or the like may be provided on the rear surface or side surface of the housing.

In addition, the portable information terminal illustrated in FIG. 17A may be configured to transmit and receive information wirelessly. It is also possible to adopt a configuration in which desired book data or the like is purchased and downloaded from an electronic book server wirelessly.

Further, the housing 902 illustrated in FIG. 17A may have an antenna, a microphone function, or a wireless function, and may be used as a mobile phone.

FIG. 17B illustrates an electronic book 910 mounted with electronic paper, which includes two housings, a housing 911 and a housing 912. A display portion 913 and a display portion 914 are provided in the housing 911 and the housing 912, respectively. The housing 911 and the housing 912 are connected by a shaft portion 915 and can be opened and closed with the shaft portion 915 as an axis. The housing 911 includes a power source 916, operation keys 917, a speaker 918, and the like. At least one of the housing 911 and the housing 912 is provided with an electronic component including a semiconductor device. Therefore, an electronic book that is reduced in size and cost is realized.

FIG. 17C illustrates a television device, which includes a housing 921, a display portion 922, a stand 923, and the like. The television device 920 can be operated with a switch included in the housing 921 or a remote controller 924. An electronic component including the semiconductor device described in any of the above embodiments is mounted on the housing 921 and the remote controller 924. Therefore, a television device that is reduced in size and cost can be realized.

FIG. 17D illustrates a smartphone. A main body 930 is provided with a display portion 931, a speaker 932, a microphone 933, operation buttons 934, and the like. In the main body 930, an electronic component including the semiconductor device described in the above embodiment is provided. As a result, a smartphone that is reduced in size and cost is realized.

FIG. 17E illustrates a digital camera, which includes a main body 941, a display portion 942, operation switches 943, and the like. In the main body 941, an electronic component including the semiconductor device described in the above embodiment is provided. Therefore, a digital camera with a reduced size and reduced cost is realized.

As described above, an electronic component including the semiconductor device according to any of the above embodiments is mounted on the electronic device described in this embodiment. For this reason, the electronic device in which size reduction and cost reduction were achieved is realized.

A1-A2 Broken line A3-A4 Broken line INV1 Inverter INV2 Inverter N1 Node N2 Node N3 Node N4 Node T1 Time T2 Time T3 Time T4 Time T5 Time T6 Time T7 Time T8 Time T9 Time 11 Transistor 11_BG Transistor 12 Transistor 13 Transistor 14 Transistor 14_BG Transistor 15 transistor 16 transistor 17 transistor 18 transistor 19 resistive element 20 resistive element 21 clocked inverter 70 electron gun chamber 72 optical system 74 sample chamber 76 optical system 78 camera 80 observation chamber 82 film chamber 84 electron 88 substance 92 fluorescent screen 110 OS-SRAM
111 row selection driver 112 column selection driver 400 substrate 401 element isolation region 402 impurity region 403 impurity region 404 channel formation region 405 insulating film 406 gate electrode 411 insulating film 412 conductive film 413 conductive film 414 conductive film 417 conductive film 417 conductive film 418 conductive Film 420 Insulating film 421 Insulating film 422 Insulating film 430 Semiconductor film 430a Oxide semiconductor film 430b Oxide semiconductor film 430c Oxide semiconductor film 431 Gate insulating film 432 Conductive film 433 Conductive film 434 Gate electrode 700 Electronic component 701 Lead 702 Printed substrate 703 Circuit unit 704 Circuit board 901 Case 902 Case 903a Display unit 903b Display unit 904 Selection button 905 Keyboard 910 Electronic book 911 Case 912 Case 913 Display unit 914 Display unit 915 Shaft unit 916 Power supply 17 operation keys 918 speaker 920 television device 921 housing 922 display unit 923 stand 924 remote controller 930 body 931 display unit 932 speaker 933 microphone 934 operation button 941 body 942 display unit 943 operation switch

Claims (8)

A semiconductor device having first to fourth transistors and first and second inverters,
A gate of the first transistor is electrically connected to a first wiring;
One of a source and a drain of the first transistor is electrically connected to a second wiring;
A gate of the second transistor is electrically connected to the first wiring;
One of a source and a drain of the second transistor is electrically connected to a third wiring;
A gate of the third transistor is electrically connected to a fourth wiring;
One of a source and a drain of the third transistor is electrically connected to the other of the source and the drain of the first transistor;
A gate of the fourth transistor is electrically connected to the fourth wiring;
One of a source and a drain of the fourth transistor is electrically connected to the other of the source and the drain of the second transistor;
A first terminal of the first inverter is electrically connected to the other of the source and the drain of the third transistor;
A second terminal of the first inverter is electrically connected to one of a source and a drain of the fourth transistor;
A first terminal of the second inverter is electrically connected to the other of the source and the drain of the fourth transistor;
A second terminal of the second inverter is electrically connected to one of a source and a drain of the third transistor;
The first wiring has a function of transmitting a first signal,
The second wiring has a function of transmitting a second signal,
The third wiring has a function of transmitting a third signal,
The fourth wiring has a function of transmitting a fourth signal,
The first to fourth transistors are n-channel transistors in which a semiconductor layer includes an oxide semiconductor,
The first signal has a function capable of turning on the first transistor and applying the potential of the third signal to one of a source and a drain of the third transistor;
The first signal has a function of turning on the second transistor and applying the potential of the fourth signal to one of a source and a drain of the fourth transistor;
The second signal has a function of turning on the third transistor and supplying one potential of the source or drain of the third transistor to the first terminal of the first inverter.
The second signal has a function of making the third transistor non-conductive and holding one of the source and drain potentials of the third transistor at the first terminal of the first inverter. And
The second signal has a function of turning on the fourth transistor and applying one potential of a source or a drain of the fourth transistor to the first terminal of the second inverter;
The second signal has a function of bringing the fourth transistor into a non-conducting state and holding one potential of a source or a drain of the fourth transistor at a first terminal of the second inverter; A semiconductor device comprising: 2. The semiconductor device according to claim 1, wherein the transistors included in the first and second inverters have a semiconductor layer containing silicon. In claim 2,
A semiconductor device, wherein a channel region of a transistor included in the first or second inverter and a channel region of any one of the first to fourth transistors overlap with each other. A semiconductor device having first to eighth transistors,
A gate of the first transistor is electrically connected to a first wiring;
One of a source and a drain of the first transistor is electrically connected to a second wiring;
A gate of the second transistor is electrically connected to the first wiring;
One of a source and a drain of the second transistor is electrically connected to a third wiring;
A gate of the third transistor is electrically connected to a fourth wiring;
One of a source and a drain of the third transistor is electrically connected to the other of the source and the drain of the first transistor;
A gate of the fourth transistor is electrically connected to the fourth wiring;
One of a source and a drain of the fourth transistor is electrically connected to the other of the source and the drain of the second transistor;
A gate of the fifth transistor is electrically connected to the other of the source and the drain of the third transistor;
One of a source and a drain of the fifth transistor is electrically connected to a fifth wiring;
The other of the source and the drain of the fifth transistor is electrically connected to one of the source and the drain of the fourth transistor;
A gate of the sixth transistor is electrically connected to the other of the source and the drain of the third transistor;
One of a source and a drain of the sixth transistor is electrically connected to one of a source and a drain of the fourth transistor;
The other of the source and the drain of the sixth transistor is electrically connected to a sixth wiring;
A gate of the seventh transistor is electrically connected to the other of the source and the drain of the fourth transistor;
One of a source and a drain of the seventh transistor is electrically connected to the fifth wiring;
The other of the source and the drain of the seventh transistor is electrically connected to one of the source and the drain of the third transistor;
A gate of the eighth transistor is electrically connected to the other of the source and the drain of the fourth transistor;
One of a source and a drain of the eighth transistor is electrically connected to one of a source and a drain of the third transistor;
The other of the source and the drain of the sixth transistor is electrically connected to the sixth wiring;
The first wiring has a function of transmitting a first signal,
The second wiring has a function of transmitting a second signal,
The third wiring has a function of transmitting a third signal,
The fourth wiring has a function of transmitting a fourth signal,
The fifth wiring has a function of transmitting a first potential;
The sixth wiring has a function of transmitting a second potential,
The first, second, third, fourth, sixth, and eighth transistors are n-channel transistors in which a semiconductor layer includes an oxide semiconductor,
The fifth and seventh transistors are p-channel transistors,
The first signal has a function capable of turning on the first transistor and applying the potential of the third signal to one of a source and a drain of the third transistor;
The first signal has a function of turning on the second transistor and applying the potential of the fourth signal to one of a source and a drain of the fourth transistor;
The second signal has a function of bringing the third transistor into a conductive state and applying one of the source and drain potentials of the third transistor to the gates of the fifth and sixth transistors. And
The second signal has a function of setting the potential of one of the source and the drain of the third transistor to the gates of the fifth and sixth transistors by making the third transistor non-conductive. Have
The second signal has a function of turning on the fourth transistor and applying one of the source and drain potentials of the fourth transistor to the gates of the seventh and eighth transistors. And
The second signal is a function capable of holding the potential of one of the source and the drain of the fourth transistor at the gates of the seventh and eighth transistors by making the fourth transistor non-conductive. And a semiconductor device. In claim 4,
In the fifth and seventh transistors, a semiconductor layer includes silicon. In claim 5,
The channel region of the fifth or seventh transistor and the channel region of the first, second, third, fourth, sixth, or eighth transistor overlap each other. A semiconductor device comprising: A semiconductor device according to any one of claims 1 to 6;
A lead electrically connected to the semiconductor device;
An electronic component comprising: An electronic component according to claim 7,
A display device;
An electronic device comprising: