JP6752553B2 - 配線基板 - Google Patents

配線基板 Download PDF

Info

Publication number
JP6752553B2
JP6752553B2 JP2015091513A JP2015091513A JP6752553B2 JP 6752553 B2 JP6752553 B2 JP 6752553B2 JP 2015091513 A JP2015091513 A JP 2015091513A JP 2015091513 A JP2015091513 A JP 2015091513A JP 6752553 B2 JP6752553 B2 JP 6752553B2
Authority
JP
Japan
Prior art keywords
layer
wiring
insulating layer
wiring layer
insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2015091513A
Other languages
English (en)
Japanese (ja)
Other versions
JP2016207958A (ja
JP2016207958A5 (enExample
Inventor
小林　和弘
和弘 小林
淳史 佐藤
淳史 佐藤
泰彦 草間
泰彦 草間
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2015091513A priority Critical patent/JP6752553B2/ja
Priority to US15/138,469 priority patent/US9627309B2/en
Publication of JP2016207958A publication Critical patent/JP2016207958A/ja
Publication of JP2016207958A5 publication Critical patent/JP2016207958A5/ja
Application granted granted Critical
Publication of JP6752553B2 publication Critical patent/JP6752553B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H10W70/65—
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/186—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
    • H10P72/74—
    • H10W70/611—
    • H10W70/614—
    • H10W70/635—
    • H10W70/685—
    • H10W72/50—
    • H10W90/401—
    • H10W90/701—
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10015—Non-printed capacitor
    • H10P72/7424—
    • H10P72/744—
    • H10W72/01235—
    • H10W72/01255—
    • H10W72/019—
    • H10W72/072—
    • H10W72/07236—
    • H10W72/073—
    • H10W72/07337—
    • H10W72/07554—
    • H10W72/252—
    • H10W72/29—
    • H10W72/354—
    • H10W72/884—
    • H10W72/90—
    • H10W74/15—
    • H10W90/00—
    • H10W90/721—
    • H10W90/724—
    • H10W90/734—
    • H10W90/754—

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Geometry (AREA)
JP2015091513A 2015-04-28 2015-04-28 配線基板 Active JP6752553B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2015091513A JP6752553B2 (ja) 2015-04-28 2015-04-28 配線基板
US15/138,469 US9627309B2 (en) 2015-04-28 2016-04-26 Wiring substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2015091513A JP6752553B2 (ja) 2015-04-28 2015-04-28 配線基板

Publications (3)

Publication Number Publication Date
JP2016207958A JP2016207958A (ja) 2016-12-08
JP2016207958A5 JP2016207958A5 (enExample) 2018-02-01
JP6752553B2 true JP6752553B2 (ja) 2020-09-09

Family

ID=57204218

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2015091513A Active JP6752553B2 (ja) 2015-04-28 2015-04-28 配線基板

Country Status (2)

Country Link
US (1) US9627309B2 (enExample)
JP (1) JP6752553B2 (enExample)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6393566B2 (ja) * 2014-09-17 2018-09-19 新光電気工業株式会社 配線基板、半導体装置及び配線基板の製造方法
US9837484B2 (en) * 2015-05-27 2017-12-05 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming substrate including embedded component with symmetrical structure
JP6625491B2 (ja) * 2016-06-29 2019-12-25 新光電気工業株式会社 配線基板、半導体装置、配線基板の製造方法
WO2018079345A1 (ja) 2016-10-24 2018-05-03 株式会社ダイヘン 交流パルスアーク溶接制御方法
FR3060846B1 (fr) * 2016-12-19 2019-05-24 Institut Vedecom Procede d’integration de puces de puissance et de bus barres formant dissipateurs thermiques
US10727197B2 (en) * 2017-03-21 2020-07-28 Intel IP Corporation Embedded-bridge substrate connectors and methods of assembling same
KR102456321B1 (ko) * 2017-11-08 2022-10-19 삼성전기주식회사 인쇄회로기판 및 이를 포함하는 전자소자 패키지
EP3483921B1 (en) 2017-11-11 2026-01-07 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Embedding known-good component in known-good cavity of known-good component carrier material with pre-formed electric connection structure
JP7046639B2 (ja) 2018-02-21 2022-04-04 新光電気工業株式会社 配線基板及びその製造方法
JP7064349B2 (ja) 2018-02-27 2022-05-10 新光電気工業株式会社 配線基板及びその製造方法
EP3557608A1 (en) * 2018-04-19 2019-10-23 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Packaged integrated circuit with interposing functionality and method for manufacturing such a packaged integrated circuit
JP6997670B2 (ja) 2018-04-23 2022-01-17 新光電気工業株式会社 配線基板及びその製造方法
JP7210191B2 (ja) * 2018-08-30 2023-01-23 京セラ株式会社 電子素子実装用基板、電子装置、および電子モジュール
KR102163059B1 (ko) * 2018-09-07 2020-10-08 삼성전기주식회사 연결구조체 내장기판
US10804188B2 (en) 2018-09-07 2020-10-13 Intel Corporation Electronic device including a lateral trace
US20200161206A1 (en) * 2018-11-20 2020-05-21 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and semiconductor manufacturing process
JP7265877B2 (ja) * 2019-02-06 2023-04-27 新光電気工業株式会社 配線基板
JP7247046B2 (ja) 2019-07-29 2023-03-28 新光電気工業株式会社 配線基板及び配線基板の製造方法
US11101840B1 (en) * 2020-02-05 2021-08-24 Samsung Electro-Mechanics Co., Ltd. Chip radio frequency package and radio frequency module
US11183765B2 (en) 2020-02-05 2021-11-23 Samsung Electro-Mechanics Co., Ltd. Chip radio frequency package and radio frequency module
US11482480B2 (en) * 2020-03-19 2022-10-25 Advanced Semiconductor Engineering, Inc. Package substrate including an optically-cured dielecetric layer and method for manufacturing the package substrate
US11791281B2 (en) 2020-03-19 2023-10-17 Advanced Semiconductor Engineering, Inc. Package substrate and method for manufacturing the same
KR102854180B1 (ko) * 2020-07-27 2025-09-03 삼성전기주식회사 전자부품 내장기판
CN114793394B (zh) * 2021-01-25 2025-05-27 礼鼎半导体科技秦皇岛有限公司 封装电路结构及其制作方法
JP7538741B2 (ja) * 2021-02-26 2024-08-22 イビデン株式会社 部品内蔵配線基板、及び、部品内蔵配線基板の製造方法
KR20230060602A (ko) 2021-10-27 2023-05-08 삼성전자주식회사 패키지 기판 및 이를 포함하는 반도체 패키지
JP2024006576A (ja) * 2022-07-04 2024-01-17 新光電気工業株式会社 配線基板及びその製造方法
KR20240052376A (ko) * 2022-10-14 2024-04-23 삼성전기주식회사 인쇄 회로 기판 및 그 제조 방법

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4826248B2 (ja) * 2005-12-19 2011-11-30 Ｔｄｋ株式会社 Ｉｃ内蔵基板の製造方法
JP5395360B2 (ja) 2008-02-25 2014-01-22 新光電気工業株式会社 電子部品内蔵基板の製造方法
KR20110028951A (ko) * 2009-09-14 2011-03-22 삼성전기주식회사 인쇄회로기판 및 그의 제조방법
JP2013038374A (ja) * 2011-01-20 2013-02-21 Ibiden Co Ltd 配線板及びその製造方法
US8745860B2 (en) * 2011-03-11 2014-06-10 Ibiden Co., Ltd. Method for manufacturing printed wiring board
JP2012216575A (ja) * 2011-03-31 2012-11-08 Nec Toppan Circuit Solutions Inc 部品内蔵印刷配線板及びその製造方法
KR101420526B1 (ko) * 2012-11-29 2014-07-17 삼성전기주식회사 전자부품 내장기판 및 그 제조방법
JP2015005612A (ja) * 2013-06-20 2015-01-08 イビデン株式会社 パッケージ基板及びパッケージ基板の製造方法
JP2015035497A (ja) * 2013-08-09 2015-02-19 イビデン株式会社 電子部品内蔵配線板

Also Published As

Publication number Publication date
JP2016207958A (ja) 2016-12-08
US9627309B2 (en) 2017-04-18
US20160322295A1 (en) 2016-11-03

Similar Documents

Publication Publication Date Title
JP6752553B2 (ja) 配線基板
JP6462480B2 (ja) 配線基板及び配線基板の製造方法
JP6173781B2 (ja) 配線基板及び配線基板の製造方法
JP6550260B2 (ja) 配線基板及び配線基板の製造方法
KR102220757B1 (ko) 배선 기판 및 배선 기판의 제조 방법
US8872041B2 (en) Multilayer laminate package and method of manufacturing the same
JP6584939B2 (ja) 配線基板、半導体パッケージ、半導体装置、配線基板の製造方法及び半導体パッケージの製造方法
JP6152254B2 (ja) 半導体パッケージ、半導体装置及び半導体パッケージの製造方法
US8941016B2 (en) Laminated wiring board and manufacturing method for same
JP6158601B2 (ja) 配線基板及び配線基板の製造方法
JP6124513B2 (ja) 半導体装置及びその製造方法
US9935053B2 (en) Electronic component integrated substrate
JP7202785B2 (ja) 配線基板及び配線基板の製造方法
JP5547615B2 (ja) 配線基板、半導体装置及び配線基板の製造方法
JP2016063130A (ja) プリント配線板および半導体パッケージ
US9966331B2 (en) Wiring substrate and semiconductor device
JP7247046B2 (ja) 配線基板及び配線基板の製造方法
US10716208B1 (en) Wiring board
US10080292B2 (en) Wiring board
JP6626687B2 (ja) 配線基板、半導体装置及び配線基板の製造方法
JP2017017048A (ja) 配線基板、半導体装置及び配線基板の製造方法
JP6343058B2 (ja) 配線基板及び配線基板の製造方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20171218

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20171218

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20180808

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20180814

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20181005

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20190108

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20200501

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20200819

R150 Certificate of patent or registration of utility model

Ref document number: 6752553

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150