JP7064349B2 - 配線基板及びその製造方法 - Google Patents
配線基板及びその製造方法 Download PDFInfo
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- JP7064349B2 JP7064349B2 JP2018032840A JP2018032840A JP7064349B2 JP 7064349 B2 JP7064349 B2 JP 7064349B2 JP 2018032840 A JP2018032840 A JP 2018032840A JP 2018032840 A JP2018032840 A JP 2018032840A JP 7064349 B2 JP7064349 B2 JP 7064349B2
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- layer
- insulating layer
- wiring
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- cavity
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- H01L2225/06503—Stacked arrangements of devices
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
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Description
まず、第1の実施の形態に係る配線基板の構造について説明する。図1は、第1の実施の形態に係る配線基板を例示する図であり、図1(a)は断面図、図1(b)はキャビティ及び電子部品を示す部分平面図である。なお、図1(a)のキャビティ及び電子部品近傍の断面は、図1(b)のA-A線に沿う断面である。又、図1(b)において、電子部品30よりも上層(絶縁層17、配線層18、ソルダーレジスト層19、及び外部接続端子20)の図示は省略されている。
次に、第1の実施の形態に係る配線基板の製造方法について説明する。図2~図6は、第1の実施の形態に係る配線基板の製造工程を例示する図である。なお、ここでは、1つの配線基板を作製する工程の例を示すが、配線基板となる複数の部分を作製し、その後個片化して各配線基板とする工程としてもよい。
第1の実施の形態の変形例1では、第1の実施の形態とは形状の異なる電子部品を搭載する例を示す。なお、第1の実施の形態の変形例1において、既に説明した実施の形態と同一構成部品についての説明は省略する場合がある。
電子部品30Aにおいて、保護層33に形成された配線層32を露出する開口部33xが凹部である。電子部品30Aにおいて、領域E1は凹部の体積が相対的に小さく、領域E2は凹部の体積が相対的に大きい。
第1の実施の形態の変形例2では、第1の実施の形態とは平面形状の異なるキャビティを形成する例、及び1つのキャビティに複数の電子部品を搭載する例を示す。なお、第1の実施の形態の変形例2において、既に説明した実施の形態と同一構成部品についての説明は省略する場合がある。
第1の実施の形態の応用例では、第1の実施の形態に係る配線基板に半導体チップを搭載した半導体パッケージの例を示す。なお、第1の実施の形態の応用例において、既に説明した実施の形態と同一構成部品についての説明は省略する場合がある。
10 コア層
10a 一方の面
10b 他方の面
10x 貫通孔
11 貫通配線
12、14、16、18、22、24、26、28 配線層
13、15、17、23、25、27 絶縁層
13x、15x、17x、17y、23x、25x、27x ビアホール
14a、16a、18a、24a、26a、28a ビア配線
14b、16b、18b、24b、26b、28b 配線パターン
14c 電子部品搭載用パッド
15s、15t、15u、15z キャビティ
19、29 ソルダーレジスト層
19x、29x、33x 開口部
20 外部接続端子
30、30A、30B、30C 電子部品
31 本体
32 配線層
32a パッド
32b 配線パターン
33 保護層
34 接着層
100 半導体パッケージ
110 半導体チップ
120 電極パッド
130、150 バンプ
140 アンダーフィル樹脂
Claims (4)
- 第1絶縁層と、
前記第1絶縁層に形成されたキャビティと、
前記キャビティ内に搭載された電子部品と、
前記第1絶縁層上に、前記電子部品を被覆して形成された第2絶縁層と、を有し、
前記電子部品の前記第2絶縁層側の最外層には、所定の体積分布を有する凹部が形成されており、
平面視において、前記キャビティ内に、前記所定の体積分布に対応して前記凹部の底面の面積が異なる領域を備え、
平面視における前記電子部品の側面と前記キャビティの内壁面との隙間の広狭は、前記所定の体積分布に基づいて決定されており、
前記最外層は、前記凹部の体積が相対的に小さい領域と、前記凹部の体積が相対的に大きい領域と、を含み、
平面視において、前記凹部の体積が相対的に小さい領域の周辺に、前記凹部の体積が相対的に大きい領域の周辺よりも前記電子部品の側面と前記キャビティの内壁面との隙間が広い部分を有し、
前記第2絶縁層が前記凹部及び前記隙間に入り込んでいる配線基板。 - 前記最外層は配線層を含み、前記凹部は前記最外層において前記配線層が形成されていない部分である請求項1に記載の配線基板。
- 前記最外層は配線層を被覆する保護層であり、前記凹部は前記保護層に形成され前記配線層を露出する開口部である請求項1又は2に記載の配線基板。
- 第1絶縁層にキャビティを形成する工程と、
電子部品を前記キャビティ内に搭載する工程と、
前記第1絶縁層上に、前記電子部品を被覆する第2絶縁層を形成する工程と、を有し、
前記電子部品の前記第2絶縁層側の最外層には、所定の体積分布を有する凹部が形成されており、
平面視において、前記キャビティ内に、前記所定の体積分布に対応して前記凹部の底面の面積が異なる領域を備え、
平面視における前記電子部品の側面と前記キャビティの内壁面との隙間の広狭は、前記所定の体積分布に基づいて決定されており、
前記最外層は、前記凹部の体積が相対的に小さい領域と、前記凹部の体積が相対的に大きい領域と、を含み、
平面視において、前記凹部の体積が相対的に小さい領域の周辺に、前記凹部の体積が相対的に大きい領域の周辺よりも前記電子部品の側面と前記キャビティの内壁面との隙間が広い部分を有し、
前記第2絶縁層を形成する工程では、前記第1絶縁層上に前記第2絶縁層となる樹脂を前記電子部品を被覆するように配置し、前記樹脂を前記凹部及び前記隙間に入り込ませる配線基板の製造方法。
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