JP6751013B2 - 温度特性調整回路 - Google Patents
温度特性調整回路 Download PDFInfo
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- JP6751013B2 JP6751013B2 JP2016253453A JP2016253453A JP6751013B2 JP 6751013 B2 JP6751013 B2 JP 6751013B2 JP 2016253453 A JP2016253453 A JP 2016253453A JP 2016253453 A JP2016253453 A JP 2016253453A JP 6751013 B2 JP6751013 B2 JP 6751013B2
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- 238000002347 injection Methods 0.000 claims description 24
- 239000007924 injection Substances 0.000 claims description 24
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- 230000001681 protective effect Effects 0.000 description 6
- 238000006243 chemical reaction Methods 0.000 description 4
- 238000012790 confirmation Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 230000014759 maintenance of location Effects 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 230000014509 gene expression Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
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- 230000006870 function Effects 0.000 description 1
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- 238000012886 linear function Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
- G05F3/242—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
- G05F3/242—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage
- G05F3/245—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage producing a voltage or current as a predetermined function of the temperature
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
- H01L29/7883—Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0425—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a merged floating gate and select transistor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
- H01L27/0211—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique adapted for requirements of temperature
Description
図1に示すように、本実施形態による電流源に備えられる不揮発性記憶素子Mは、半導体基板に形成されたPウェル領域10と、Pウェル領域10上に形成されたフローティングゲート領域FGと、フローティングゲート領域FG上に形成されたコントロールゲート領域CGとを備えている。また、不揮発性記憶素子Mは、フローティングゲート領域FGの下方の両側の一方に形成されたドレイン領域Dと、フローティングゲート領域FGの下方の両側の他方に形成されたソース領域Sとを備えている。ドレイン領域Dおよびソース領域Sは、Pウェル領域10に形成されている。不揮発性記憶素子Mは、素子分離領域41,42によって、同一の半導体基板に形成された他の素子と素子分離されている。
スイッチSW2:接続状態(ショート状態)
スイッチSW3:接続状態(ショート状態)
スイッチSW4:開放状態(オープン状態)
スイッチSW5:任意(図17では低電圧Vss側)
スイッチSW2:開放状態(オープン状態)
スイッチSW3:開放状態(オープン状態)
スイッチSW4:接続状態(ショート状態)
スイッチSW5:パルス電圧Vpp側
スイッチSW2:開放状態(オープン状態)
スイッチSW3:接続状態(ショート状態)
スイッチSW4:開放状態(オープン状態)
スイッチSW5:任意(図19では低電圧Vss側)
スイッチSW2:開放状態(オープン状態)
スイッチSW3:開放状態(オープン状態)
スイッチSW4:接続状態(ショート状態)
スイッチSW5:低電圧供給端子Vss側
本発明の第2実施形態による温度特性調整回路について図22から図27を用いて説明する。本実施形態による不揮発性記憶素子は、図1に示す不揮発性記憶素子Mと同一の構造を有する不揮発性記憶素子Mwと、図22に示す不揮発性記憶素子Mrとを一組とし、不揮発性記憶素子Mwおよび不揮発性記憶素子Mrのそれぞれのフローティングゲート領域同士が接続され、不揮発性記憶素子Mwおよび不揮発性記憶素子Mrのそれぞれのコントロールゲート領域同士が接続された構成を有している。
スイッチSW2:接続状態(ショート状態)
スイッチSW3:接続状態(ショート状態)
スイッチSW4:開放状態(オープン状態)
スイッチSW5:任意(図24では低電圧Vss側)
スイッチSW2:開放状態(オープン状態)
スイッチSW3:開放状態(オープン状態)
スイッチSW4:接続状態(ショート状態)
スイッチSW5:パルス電圧Vpp側
スイッチSW2:開放状態(オープン状態)
スイッチSW3:接続状態(ショート状態)
スイッチSW4:開放状態(オープン状態)
スイッチSW5:任意(図24では低電圧Vss側)
スイッチSW2:開放状態(オープン状態)
スイッチSW3:開放状態(オープン状態)
スイッチSW4:接続状態(ショート状態)
スイッチSW5:低電圧供給端子Vss側
また、本実施形態による温度特性調整回路5は、不揮発性記憶素子Mwのフローティングゲート領域FGの電荷量を調整して閾値電圧を調整できるので、上記第1実施形態による温度特性調整回路3と同様の効果が得られる。
4 電流計
6 出力回路
8 出力端子
10 ウェル領域
11,13 N型領域
12,14 N+領域
20,70 絶縁体
21,71 電荷保持領域
22,72 ゲート絶縁膜
23、73 側壁酸化膜
24、74 上部絶縁膜
25,32 サイドウォール
41,42 素子分離領域
51,52,53 コンタクトプラグ
61 保護膜
211 電荷注入口
221 トンネル絶縁膜
A1 第一領域
A2 第二領域
B バックゲート
CG コントロールゲート領域
D ドレイン領域
FG フローティングゲート領域
G ゲート領域
M,Mr,Mw 不揮発性記憶素子
Q1,Q2 トランジスタ
R 抵抗
S ソース領域
Claims (4)
- コントロールゲート領域およびソース領域を有し、前記コントロールゲート領域と前記ソース領域との間にバイアスを印加して駆動される不揮発性記憶素子を有する電流源と、
前記電流源が出力する電流の電流量の温度依存性に由来する出力信号の温度依存性が前記不揮発性記憶素子によって調整され、かつ不揮発性記憶素子を有さない出力回路と
を備え、
前記不揮発性記憶素子は、電荷注入口を有し、
前記電荷注入口は、前記電流源が出力する電流の経路とは接していない領域に形成される
温度特性調整回路。 - 前記出力回路は、電圧の出力信号を出力する請求項1に記載の温度特性調整回路。
- 前記出力回路は、電流の出力信号を出力する請求項1に記載の温度特性調整回路。
- 前記電流源および前記出力回路に流れる電流値は100nA未満である請求項1から3までのいずれか一項に記載の温度特性調整回路。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016253453A JP6751013B2 (ja) | 2016-12-27 | 2016-12-27 | 温度特性調整回路 |
PCT/JP2017/036031 WO2018123188A1 (ja) | 2016-12-27 | 2017-10-03 | 温度特性調整回路 |
US16/473,811 US11094687B2 (en) | 2016-12-27 | 2017-10-03 | Temperature characteristic adjustment circuit |
EP17888976.2A EP3547069A4 (en) | 2016-12-27 | 2017-10-03 | TEMPERATURE CHARACTERISTIC SETTING CIRCUIT |
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JP2016253453A JP6751013B2 (ja) | 2016-12-27 | 2016-12-27 | 温度特性調整回路 |
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JP2018106509A JP2018106509A (ja) | 2018-07-05 |
JP6751013B2 true JP6751013B2 (ja) | 2020-09-02 |
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JP2016253453A Active JP6751013B2 (ja) | 2016-12-27 | 2016-12-27 | 温度特性調整回路 |
Country Status (4)
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US (1) | US11094687B2 (ja) |
EP (1) | EP3547069A4 (ja) |
JP (1) | JP6751013B2 (ja) |
WO (1) | WO2018123188A1 (ja) |
Families Citing this family (1)
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US10978125B1 (en) * | 2020-04-21 | 2021-04-13 | Namlab Ggmbh | Transistor with adjustable rectifying transfer characteristic |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0772996B2 (ja) * | 1987-01-31 | 1995-08-02 | 株式会社東芝 | 不揮発性半導体メモリ |
JPH05119859A (ja) * | 1991-10-24 | 1993-05-18 | Sony Corp | 基準電圧発生回路 |
US5930171A (en) * | 1995-05-22 | 1999-07-27 | Siemens Aktiengesellschaft | Constant-current source with an EEPROM cell |
TW368749B (en) * | 1995-09-11 | 1999-09-01 | Matsushita Electronics Corp | Semiconductor memory device and driving method thereof |
JP3954245B2 (ja) | 1999-07-22 | 2007-08-08 | 株式会社東芝 | 電圧発生回路 |
JP4020182B2 (ja) * | 2000-06-23 | 2007-12-12 | 株式会社リコー | 基準電圧発生回路及び電源装置 |
JP2002368107A (ja) * | 2001-06-07 | 2002-12-20 | Ricoh Co Ltd | 基準電圧発生回路とそれを用いた電源装置 |
JP2007294846A (ja) * | 2006-03-31 | 2007-11-08 | Ricoh Co Ltd | 基準電圧発生回路及びそれを用いた電源装置 |
JP5467849B2 (ja) * | 2008-12-22 | 2014-04-09 | セイコーインスツル株式会社 | 基準電圧回路及び半導体装置 |
US9437602B2 (en) * | 2011-12-02 | 2016-09-06 | Board Of Trustees Of Michigan State University | Temperature compensation method for high-density floating-gate memory |
JP6013851B2 (ja) * | 2012-09-27 | 2016-10-25 | エスアイアイ・セミコンダクタ株式会社 | 基準電圧発生装置 |
JP5886245B2 (ja) * | 2013-06-27 | 2016-03-16 | 旭化成エレクトロニクス株式会社 | 基準電圧発生回路及び基準電圧発生方法 |
JP6314002B2 (ja) * | 2014-03-07 | 2018-04-18 | 旭化成エレクトロニクス株式会社 | 切り替え回路およびモニタ回路 |
JP6506968B2 (ja) * | 2015-01-09 | 2019-04-24 | 旭化成エレクトロニクス株式会社 | 電圧検出器 |
US9837439B1 (en) * | 2016-08-12 | 2017-12-05 | Globalfoundries Inc. | Compensation of temperature effects in semiconductor device structures |
-
2016
- 2016-12-27 JP JP2016253453A patent/JP6751013B2/ja active Active
-
2017
- 2017-10-03 WO PCT/JP2017/036031 patent/WO2018123188A1/ja unknown
- 2017-10-03 US US16/473,811 patent/US11094687B2/en active Active
- 2017-10-03 EP EP17888976.2A patent/EP3547069A4/en active Pending
Also Published As
Publication number | Publication date |
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US11094687B2 (en) | 2021-08-17 |
JP2018106509A (ja) | 2018-07-05 |
EP3547069A1 (en) | 2019-10-02 |
EP3547069A4 (en) | 2019-12-25 |
US20200152618A1 (en) | 2020-05-14 |
WO2018123188A1 (ja) | 2018-07-05 |
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