JP6621708B2 - 半導体装置、半導体装置の製造方法 - Google Patents

半導体装置、半導体装置の製造方法 Download PDF

Info

Publication number
JP6621708B2
JP6621708B2 JP2016105603A JP2016105603A JP6621708B2 JP 6621708 B2 JP6621708 B2 JP 6621708B2 JP 2016105603 A JP2016105603 A JP 2016105603A JP 2016105603 A JP2016105603 A JP 2016105603A JP 6621708 B2 JP6621708 B2 JP 6621708B2
Authority
JP
Japan
Prior art keywords
wiring
shield
layer
shield body
sealing resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2016105603A
Other languages
English (en)
Japanese (ja)
Other versions
JP2017212377A5 (OSRAM
JP2017212377A (ja
Inventor
健 宮入
健 宮入
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2016105603A priority Critical patent/JP6621708B2/ja
Priority to US15/587,834 priority patent/US9991228B2/en
Publication of JP2017212377A publication Critical patent/JP2017212377A/ja
Publication of JP2017212377A5 publication Critical patent/JP2017212377A5/ja
Application granted granted Critical
Publication of JP6621708B2 publication Critical patent/JP6621708B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0655—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5225—Shielding layers formed together with wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, the devices being individual devices of subclass H10D or integrated devices of class H10
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H01L2224/02311—Additive methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/95001—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1432—Central processing unit [CPU]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/1435—Random access memory [RAM]
    • H01L2924/1436—Dynamic random-access memory [DRAM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/1435—Random access memory [RAM]
    • H01L2924/1437—Static random-access memory [SRAM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/1435—Random access memory [RAM]
    • H01L2924/1438—Flash memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Toxicology (AREA)
  • Electromagnetism (AREA)
  • Health & Medical Sciences (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
JP2016105603A 2016-05-26 2016-05-26 半導体装置、半導体装置の製造方法 Active JP6621708B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2016105603A JP6621708B2 (ja) 2016-05-26 2016-05-26 半導体装置、半導体装置の製造方法
US15/587,834 US9991228B2 (en) 2016-05-26 2017-05-05 Semiconductor device with electromagnetic shield

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2016105603A JP6621708B2 (ja) 2016-05-26 2016-05-26 半導体装置、半導体装置の製造方法

Publications (3)

Publication Number Publication Date
JP2017212377A JP2017212377A (ja) 2017-11-30
JP2017212377A5 JP2017212377A5 (OSRAM) 2019-03-07
JP6621708B2 true JP6621708B2 (ja) 2019-12-18

Family

ID=60418232

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016105603A Active JP6621708B2 (ja) 2016-05-26 2016-05-26 半導体装置、半導体装置の製造方法

Country Status (2)

Country Link
US (1) US9991228B2 (OSRAM)
JP (1) JP6621708B2 (OSRAM)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI566339B (zh) * 2014-11-11 2017-01-11 矽品精密工業股份有限公司 電子封裝件及其製法
CN107424974A (zh) * 2016-05-24 2017-12-01 胡迪群 具有埋入式噪声屏蔽墙的封装基板
US10804119B2 (en) 2017-03-15 2020-10-13 STATS ChipPAC Pte. Ltd. Method of forming SIP module over film layer
US10629542B2 (en) 2018-04-05 2020-04-21 Samsung Electro-Mechanics Co., Ltd. Electronic device module
KR20190129650A (ko) 2018-05-10 2019-11-20 삼성전기주식회사 전자 소자 모듈 및 그 제조 방법
US10790238B2 (en) 2018-05-10 2020-09-29 Samsung Electro-Mechanics Co., Ltd. Electronic device module and method of manufacturing the same
KR102592329B1 (ko) 2018-06-26 2023-10-20 삼성전자주식회사 반도체 패키지 제조 방법
US10629518B2 (en) * 2018-08-29 2020-04-21 Nxp Usa, Inc. Internally-shielded microelectronic packages and methods for the fabrication thereof
US10755979B2 (en) * 2018-10-31 2020-08-25 Ningbo Semiconductor International Corporation Wafer-level packaging methods using a photolithographic bonding material
US11071196B2 (en) 2019-04-05 2021-07-20 Samsung Electro-Mechanics Co., Ltd. Electronic device module and method of manufacturing electronic device module
WO2020250425A1 (ja) * 2019-06-14 2020-12-17 株式会社 東芝 半導体装置
US11362041B2 (en) * 2019-12-19 2022-06-14 Amkor Technology Japan, Inc. Semiconductor devices including shielding layer and methods of manufacturing semiconductor devices
WO2021131776A1 (ja) * 2019-12-27 2021-07-01 株式会社村田製作所 モジュール
JP2021125525A (ja) 2020-02-04 2021-08-30 キオクシア株式会社 半導体パッケージおよびその製造方法
US11626337B2 (en) * 2020-05-19 2023-04-11 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor devices and methods of manufacturing semiconductor devices
CN112701089A (zh) * 2020-09-10 2021-04-23 成都芯源系统有限公司 集成电路封装结构、集成电路封装单元及相关制造方法
CN112908984A (zh) * 2021-01-18 2021-06-04 上海先方半导体有限公司 一种带有散热片的ssd堆叠封装结构及其制作方法
EP4040483A3 (en) * 2021-02-04 2022-10-26 Murata Manufacturing Co., Ltd. Electronic component with internal shielding
US11869848B2 (en) * 2021-08-11 2024-01-09 STATS ChipPAC Pte. Ltd. Semiconductor device and method of stacking devices using support frame
CN114206090B (zh) * 2021-11-30 2024-04-16 四川天邑康和通信股份有限公司 一种能够有效解决pon/全光网关发热和屏蔽信号互绕的方法
TWI840976B (zh) * 2022-09-29 2024-05-01 海華科技股份有限公司 電磁屏蔽封裝結構與其製造方法、及電子組件

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006100302A (ja) * 2004-09-28 2006-04-13 Sharp Corp 高周波モジュールおよびその製造方法
JP4489575B2 (ja) 2004-12-17 2010-06-23 新光電気工業株式会社 半導体装置及びその製造方法
JP2006294701A (ja) * 2005-04-06 2006-10-26 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
DE602006012571D1 (de) * 2005-04-21 2010-04-15 St Microelectronics Sa Vorrichtung zum Schutz einer elektronischen Schaltung
JP4816647B2 (ja) * 2005-11-28 2011-11-16 株式会社村田製作所 回路モジュールの製造方法および回路モジュール
JP4650244B2 (ja) * 2005-12-02 2011-03-16 株式会社村田製作所 回路モジュールおよびその製造方法
US7626247B2 (en) * 2005-12-22 2009-12-01 Atmel Corporation Electronic package with integral electromagnetic radiation shield and methods related thereto
WO2008136251A1 (ja) * 2007-05-02 2008-11-13 Murata Manufacturing Co., Ltd. 部品内蔵モジュール及びその製造方法
JP2009218484A (ja) * 2008-03-12 2009-09-24 Tdk Corp 電子モジュール、および電子モジュールの製造方法
KR101711045B1 (ko) * 2010-12-02 2017-03-02 삼성전자 주식회사 적층 패키지 구조물
US8835226B2 (en) * 2011-02-25 2014-09-16 Rf Micro Devices, Inc. Connection using conductive vias
JP5861260B2 (ja) * 2011-03-10 2016-02-16 日本電気株式会社 半導体装置の製造方法及び半導体装置
KR20120131530A (ko) * 2011-05-25 2012-12-05 삼성전자주식회사 반도체 장치 및 그 제조 방법
KR20140023112A (ko) * 2012-08-17 2014-02-26 삼성전자주식회사 반도체 패키지를 포함하는 전자 장치 및 그 제조 방법
JP5767268B2 (ja) * 2013-04-02 2015-08-19 太陽誘電株式会社 回路モジュール及びその製造方法
WO2015194435A1 (ja) * 2014-06-20 2015-12-23 株式会社村田製作所 回路モジュール及びその製造方法
US9570406B2 (en) * 2015-06-01 2017-02-14 Qorvo Us, Inc. Wafer level fan-out with electromagnetic shielding
US10043761B2 (en) * 2015-10-19 2018-08-07 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof

Also Published As

Publication number Publication date
US9991228B2 (en) 2018-06-05
US20170345793A1 (en) 2017-11-30
JP2017212377A (ja) 2017-11-30

Similar Documents

Publication Publication Date Title
JP6621708B2 (ja) 半導体装置、半導体装置の製造方法
JP6752553B2 (ja) 配線基板
CN101785106B (zh) 包括半导体组件的半导体装置及其制造方法
JP5188426B2 (ja) 半導体装置及びその製造方法、電子装置
JP6133549B2 (ja) 配線基板及び配線基板の製造方法
JP6408540B2 (ja) 無線モジュール及び無線モジュールの製造方法
TWI694612B (zh) 半導體模組
JP5372579B2 (ja) 半導体装置及びその製造方法、並びに電子装置
TW201312713A (zh) 半導體裝置、垂直堆疊有該半導體裝置之半導體模組構造及其製造方法
JP5547615B2 (ja) 配線基板、半導体装置及び配線基板の製造方法
JP2013243345A5 (OSRAM)
JP2008226945A (ja) 半導体装置およびその製造方法
KR20100044084A (ko) 인쇄 배선 보드 및 반도체 패키지와 이들의 제조 방법
JP2017212376A (ja) 半導体装置、半導体装置の製造方法
JP2016063130A (ja) プリント配線板および半導体パッケージ
US20190013263A1 (en) Wiring board and semiconductor package
JP6625491B2 (ja) 配線基板、半導体装置、配線基板の製造方法
JP2017143096A (ja) 配線基板、半導体装置及び配線基板の製造方法
JP7265877B2 (ja) 配線基板
US10080292B2 (en) Wiring board
JP2009260165A (ja) 半導体装置
KR102235811B1 (ko) 반도체 장치, 반도체 적층모듈구조, 적층모듈구조 및 이들의 제조방법
JP2005150344A (ja) 半導体装置およびその製造方法
JP2017162989A (ja) 電子部品内蔵基板およびその製造方法
JP5257518B2 (ja) 基板製造方法および樹脂基板

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20190121

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20190121

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20190919

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20191105

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20191120

R150 Certificate of patent or registration of utility model

Ref document number: 6621708

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150