JP6598890B2 - ファン−アウト半導体パッケージモジュール - Google Patents
ファン−アウト半導体パッケージモジュール Download PDFInfo
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- JP6598890B2 JP6598890B2 JP2018017867A JP2018017867A JP6598890B2 JP 6598890 B2 JP6598890 B2 JP 6598890B2 JP 2018017867 A JP2018017867 A JP 2018017867A JP 2018017867 A JP2018017867 A JP 2018017867A JP 6598890 B2 JP6598890 B2 JP 6598890B2
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Classifications
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
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- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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- H01L2924/30—Technical effects
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- H01L2924/3025—Electromagnetic shielding
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- H01L2924/30—Technical effects
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- H01L2924/30—Technical effects
- H01L2924/37—Effects of the manufacturing process
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- Computer Hardware Design (AREA)
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- Geometry (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
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KR20170086350 | 2017-07-07 | ||
KR10-2017-0086350 | 2017-07-07 | ||
KR10-2017-0136769 | 2017-10-20 | ||
KR1020170136769A KR102081086B1 (ko) | 2017-07-07 | 2017-10-20 | 팬-아웃 반도체 패키지 모듈 |
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KR102596759B1 (ko) * | 2019-03-18 | 2023-11-02 | 삼성전자주식회사 | 반도체 패키지 |
KR102574415B1 (ko) * | 2019-04-04 | 2023-09-04 | 삼성전기주식회사 | 안테나 모듈 |
KR102584960B1 (ko) * | 2019-04-12 | 2023-10-05 | 삼성전기주식회사 | 반도체 패키지 |
TWI766164B (zh) * | 2019-05-28 | 2022-06-01 | 力成科技股份有限公司 | 封裝結構 |
KR102572413B1 (ko) * | 2019-08-28 | 2023-08-30 | 양쯔 메모리 테크놀로지스 씨오., 엘티디. | 3차원 메모리 장치 및 그 제조 방법 |
US11948891B2 (en) | 2020-04-03 | 2024-04-02 | Nepes Co., Ltd. | Semiconductor package and manufacturing method thereof |
WO2022064704A1 (ja) * | 2020-09-28 | 2022-03-31 | 昭和電工マテリアルズ株式会社 | 表面実装型モジュール、及び、回路基板の製造方法 |
WO2022064698A1 (ja) * | 2020-09-28 | 2022-03-31 | 昭和電工マテリアルズ株式会社 | 電子部品モジュールの製造方法、電子回路基板の製造方法、及び、部品内蔵基板の製造方法 |
TWI793618B (zh) * | 2021-05-26 | 2023-02-21 | 威盛電子股份有限公司 | 電子封裝體及其製作方法 |
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US8890628B2 (en) * | 2012-08-31 | 2014-11-18 | Intel Corporation | Ultra slim RF package for ultrabooks and smart phones |
JP2014072279A (ja) * | 2012-09-28 | 2014-04-21 | Dainippon Printing Co Ltd | 部品内蔵配線基板の製造方法 |
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US10418298B2 (en) * | 2013-09-24 | 2019-09-17 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming dual fan-out semiconductor package |
US9754897B2 (en) * | 2014-06-02 | 2017-09-05 | STATS ChipPAC, Pte. Ltd. | Semiconductor device and method of forming electromagnetic (EM) shielding for LC circuits |
KR20160132751A (ko) * | 2015-05-11 | 2016-11-21 | 삼성전기주식회사 | 전자부품 패키지 및 그 제조방법 |
US10199337B2 (en) * | 2015-05-11 | 2019-02-05 | Samsung Electro-Mechanics Co., Ltd. | Electronic component package and method of manufacturing the same |
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US10566289B2 (en) * | 2015-10-13 | 2020-02-18 | Samsung Electronics Co., Ltd. | Fan-out semiconductor package and manufacturing method thereof |
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CN109216335A (zh) | 2019-01-15 |
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