JP6584939B2 - 配線基板、半導体パッケージ、半導体装置、配線基板の製造方法及び半導体パッケージの製造方法 - Google Patents

配線基板、半導体パッケージ、半導体装置、配線基板の製造方法及び半導体パッケージの製造方法 Download PDF

Info

Publication number
JP6584939B2
JP6584939B2 JP2015241424A JP2015241424A JP6584939B2 JP 6584939 B2 JP6584939 B2 JP 6584939B2 JP 2015241424 A JP2015241424 A JP 2015241424A JP 2015241424 A JP2015241424 A JP 2015241424A JP 6584939 B2 JP6584939 B2 JP 6584939B2
Authority
JP
Japan
Prior art keywords
layer
wiring
insulating layer
wiring layer
insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2015241424A
Other languages
English (en)
Japanese (ja)
Other versions
JP2017108019A (ja
JP2017108019A5 (enExample
Inventor
渉 金田
渉 金田
清水　規良
規良 清水
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2015241424A priority Critical patent/JP6584939B2/ja
Priority to US15/372,913 priority patent/US9780043B2/en
Publication of JP2017108019A publication Critical patent/JP2017108019A/ja
Publication of JP2017108019A5 publication Critical patent/JP2017108019A5/ja
Application granted granted Critical
Publication of JP6584939B2 publication Critical patent/JP6584939B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/121—Arrangements for protection of devices protecting against mechanical damage
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H10W70/614—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together the multiple chips being integrally enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/129—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed forming a chip-scale package [CSP]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/095—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers of vias therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07351—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting
    • H10W72/07354—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting changes in dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/231—Shapes
    • H10W72/232—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/341—Dispositions of die-attach connectors, e.g. layouts
    • H10W72/347—Dispositions of multiple die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/351—Materials of die-attach connectors
    • H10W72/353—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics
    • H10W72/354—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics comprising polymers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/877—Bump connectors and die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/142—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations exposing the passive side of the semiconductor body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
JP2015241424A 2015-12-10 2015-12-10 配線基板、半導体パッケージ、半導体装置、配線基板の製造方法及び半導体パッケージの製造方法 Active JP6584939B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2015241424A JP6584939B2 (ja) 2015-12-10 2015-12-10 配線基板、半導体パッケージ、半導体装置、配線基板の製造方法及び半導体パッケージの製造方法
US15/372,913 US9780043B2 (en) 2015-12-10 2016-12-08 Wiring board, semiconductor package, and semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2015241424A JP6584939B2 (ja) 2015-12-10 2015-12-10 配線基板、半導体パッケージ、半導体装置、配線基板の製造方法及び半導体パッケージの製造方法

Publications (3)

Publication Number Publication Date
JP2017108019A JP2017108019A (ja) 2017-06-15
JP2017108019A5 JP2017108019A5 (enExample) 2018-11-08
JP6584939B2 true JP6584939B2 (ja) 2019-10-02

Family

ID=59020190

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2015241424A Active JP6584939B2 (ja) 2015-12-10 2015-12-10 配線基板、半導体パッケージ、半導体装置、配線基板の製造方法及び半導体パッケージの製造方法

Country Status (2)

Country Link
US (1) US9780043B2 (enExample)
JP (1) JP6584939B2 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11715680B2 (en) 2020-12-17 2023-08-01 Samsung Electro-Mechanics Co., Ltd. Printed circuit board

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9818736B1 (en) * 2017-03-03 2017-11-14 Tdk Corporation Method for producing semiconductor package
KR102069659B1 (ko) 2017-08-31 2020-01-23 해성디에스 주식회사 반도체 패키지 기판 제조방법 및 이를 이용하여 제조된 반도체 패키지 기판
TWI642334B (zh) 2017-10-25 2018-11-21 欣興電子股份有限公司 電路板及其製造方法
TWI642333B (zh) * 2017-10-25 2018-11-21 欣興電子股份有限公司 電路板及其製造方法
US10314171B1 (en) * 2017-12-29 2019-06-04 Intel Corporation Package assembly with hermetic cavity
JP7289620B2 (ja) * 2018-09-18 2023-06-12 新光電気工業株式会社 配線基板、積層型配線基板、半導体装置
TWI690253B (zh) * 2018-11-06 2020-04-01 鈺橋半導體股份有限公司 具有應力調節件之互連基板、其覆晶組體及其製作方法
JP2020161732A (ja) * 2019-03-27 2020-10-01 イビデン株式会社 配線基板
US11462501B2 (en) * 2019-10-25 2022-10-04 Shinko Electric Industries Co., Ltd. Interconnect substrate and method of making the same
JP2021150567A (ja) 2020-03-23 2021-09-27 キオクシア株式会社 半導体装置及びその製造方法
KR102852782B1 (ko) 2020-07-10 2025-08-29 삼성전자주식회사 반도체 패키지
JP7661664B2 (ja) * 2021-08-20 2025-04-15 新光電気工業株式会社 配線基板及びその製造方法
JP7694883B2 (ja) * 2021-08-30 2025-06-18 新光電気工業株式会社 配線基板、半導体装置及び配線基板の製造方法
US11961808B2 (en) * 2021-10-14 2024-04-16 Advanced Semiconductor Engineering, Inc. Electronic package structure with reinforcement element
US12183683B2 (en) * 2021-10-14 2024-12-31 Advanced Semiconductor Engineering, Inc. Electronic package structure
CN114062076A (zh) * 2021-11-04 2022-02-18 九江德福科技股份有限公司 一种用于铜箔晶体分析的样品制备方法
CN115831765A (zh) * 2022-12-30 2023-03-21 珠海越亚半导体股份有限公司 一种嵌埋封装散热结构及其制作方法以及半导体
CN116190248A (zh) * 2023-02-07 2023-05-30 珠海越亚半导体股份有限公司 一种嵌埋封装散热结构及其制作方法以及半导体

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003197849A (ja) * 2001-10-18 2003-07-11 Matsushita Electric Ind Co Ltd 部品内蔵モジュールとその製造方法
JP2003163459A (ja) * 2001-11-26 2003-06-06 Sony Corp 高周波回路ブロック体及びその製造方法、高周波モジュール装置及びその製造方法。
JP4863076B2 (ja) * 2006-12-28 2012-01-25 凸版印刷株式会社 配線基板及びその製造方法
US8895440B2 (en) * 2010-08-06 2014-11-25 Stats Chippac, Ltd. Semiconductor die and method of forming Fo-WLCSP vertical interconnect using TSV and TMV
JP5941735B2 (ja) * 2012-04-10 2016-06-29 新光電気工業株式会社 配線基板の製造方法及び配線基板
KR20140086531A (ko) * 2012-12-28 2014-07-08 삼성전기주식회사 패키지 기판 및 그 제조방법, 그리고 패키지 온 패키지 기판
JP5662551B1 (ja) 2013-12-20 2015-01-28 新光電気工業株式会社 配線基板、半導体装置及び配線基板の製造方法
US9768090B2 (en) * 2014-02-14 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate design for semiconductor packages and method of forming same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11715680B2 (en) 2020-12-17 2023-08-01 Samsung Electro-Mechanics Co., Ltd. Printed circuit board

Also Published As

Publication number Publication date
JP2017108019A (ja) 2017-06-15
US9780043B2 (en) 2017-10-03
US20170170130A1 (en) 2017-06-15

Similar Documents

Publication Publication Date Title
JP6584939B2 (ja) 配線基板、半導体パッケージ、半導体装置、配線基板の製造方法及び半導体パッケージの製造方法
JP6375121B2 (ja) 配線基板、半導体装置及び配線基板の製造方法
JP5662551B1 (ja) 配線基板、半導体装置及び配線基板の製造方法
JP6158676B2 (ja) 配線基板、半導体装置及び配線基板の製造方法
JP6324876B2 (ja) 配線基板、半導体装置及び配線基板の製造方法
JP6298722B2 (ja) 配線基板、半導体装置及び配線基板の製造方法
US10892216B2 (en) Wiring substrate and semiconductor device
JP6661232B2 (ja) 配線基板、半導体装置、配線基板の製造方法及び半導体装置の製造方法
US9520352B2 (en) Wiring board and semiconductor device
US11430725B2 (en) Wiring board and method of manufacturing the same
JP6375159B2 (ja) 配線基板、半導体パッケージ
US9627308B2 (en) Wiring substrate
JP6594264B2 (ja) 配線基板及び半導体装置、並びにそれらの製造方法
JP7202785B2 (ja) 配線基板及び配線基板の製造方法
JP6550260B2 (ja) 配線基板及び配線基板の製造方法
JP2022016495A (ja) 配線基板、半導体装置、配線基板の製造方法及び半導体装置の製造方法
KR20150004749A (ko) 배선 기판 및 그 제조 방법, 반도체 패키지
JP6612189B2 (ja) 配線基板、半導体装置、および、配線基板の製造方法
JP2017050313A (ja) プリント配線板及びプリント配線板の製造方法
JP2016111297A (ja) 配線基板、半導体装置及び配線基板の製造方法
JP6626687B2 (ja) 配線基板、半導体装置及び配線基板の製造方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20180927

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20180927

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20190516

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20190625

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20190809

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20190820

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20190904

R150 Certificate of patent or registration of utility model

Ref document number: 6584939

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150