JP6542775B2 - 双方向デバイス製造のためのシステムおよび方法 - Google Patents

双方向デバイス製造のためのシステムおよび方法 Download PDF

Info

Publication number
JP6542775B2
JP6542775B2 JP2016538542A JP2016538542A JP6542775B2 JP 6542775 B2 JP6542775 B2 JP 6542775B2 JP 2016538542 A JP2016538542 A JP 2016538542A JP 2016538542 A JP2016538542 A JP 2016538542A JP 6542775 B2 JP6542775 B2 JP 6542775B2
Authority
JP
Japan
Prior art keywords
wafer
handle wafer
handle
temperature
introducing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2016538542A
Other languages
English (en)
Japanese (ja)
Other versions
JP2017509136A5 (OSRAM
JP2017509136A (ja
Inventor
リチャード エー. ブランチャード
リチャード エー. ブランチャード
ウィリアム シー. アレクサンダー
ウィリアム シー. アレクサンダー
Original Assignee
アイディール パワー インコーポレイテッド
アイディール パワー インコーポレイテッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US14/313,960 external-priority patent/US9029909B2/en
Application filed by アイディール パワー インコーポレイテッド, アイディール パワー インコーポレイテッド filed Critical アイディール パワー インコーポレイテッド
Publication of JP2017509136A publication Critical patent/JP2017509136A/ja
Publication of JP2017509136A5 publication Critical patent/JP2017509136A5/ja
Application granted granted Critical
Publication of JP6542775B2 publication Critical patent/JP6542775B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411Insulated-gate bipolar transistors [IGBT]
    • H10D12/441Vertical IGBTs
    • H10D12/461Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00Bipolar junction transistors [BJT]
    • H10D10/01Manufacture or treatment
    • H10D10/051Manufacture or treatment of vertical BJTs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00Bipolar junction transistors [BJT]
    • H10D10/40Vertical BJTs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01Manufacture or treatment
    • H10D12/031Manufacture or treatment of IGBTs
    • H10D12/032Manufacture or treatment of IGBTs of vertical IGBTs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01Manufacture or treatment
    • H10D12/031Manufacture or treatment of IGBTs
    • H10D12/032Manufacture or treatment of IGBTs of vertical IGBTs
    • H10D12/038Manufacture or treatment of IGBTs of vertical IGBTs having a recessed gate, e.g. trench-gate IGBTs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00Three-dimensional [3D] integrated devices
    • H10D88/101Three-dimensional [3D] integrated devices comprising components on opposite major surfaces of semiconductor substrates
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D18/00Thyristors
    • H10D18/01Manufacture or treatment
    • H10D18/021Manufacture or treatment of bidirectional devices, e.g. triacs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D18/00Thyristors
    • H10D18/80Bidirectional devices, e.g. triacs 
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/60Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
    • H10D84/641Combinations of only vertical BJTs

Landscapes

  • Bipolar Transistors (AREA)
  • Led Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
JP2016538542A 2013-12-11 2014-12-10 双方向デバイス製造のためのシステムおよび方法 Active JP6542775B2 (ja)

Applications Claiming Priority (11)

Application Number Priority Date Filing Date Title
US201361914491P 2013-12-11 2013-12-11
US61/914,491 2013-12-11
US201461924884P 2014-01-08 2014-01-08
US61/924,884 2014-01-08
US201461928644P 2014-01-17 2014-01-17
US61/928,644 2014-01-17
US201461929874P 2014-01-21 2014-01-21
US61/929,874 2014-01-21
US14/313,960 US9029909B2 (en) 2013-06-24 2014-06-24 Systems, circuits, devices, and methods with bidirectional bipolar transistors
US14/313,960 2014-06-24
PCT/US2014/069611 WO2015089227A1 (en) 2013-12-11 2014-12-10 Systems and methods for bidirectional device fabrication

Publications (3)

Publication Number Publication Date
JP2017509136A JP2017509136A (ja) 2017-03-30
JP2017509136A5 JP2017509136A5 (OSRAM) 2018-01-11
JP6542775B2 true JP6542775B2 (ja) 2019-07-10

Family

ID=53371816

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016538542A Active JP6542775B2 (ja) 2013-12-11 2014-12-10 双方向デバイス製造のためのシステムおよび方法

Country Status (5)

Country Link
EP (1) EP3055884B8 (OSRAM)
JP (1) JP6542775B2 (OSRAM)
CN (1) CN106062958B (OSRAM)
GB (1) GB2531485B (OSRAM)
WO (1) WO2015089227A1 (OSRAM)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109872979A (zh) * 2019-02-14 2019-06-11 南通通富微电子有限公司 一种扇出型封装器件
US20250380436A1 (en) * 2024-06-11 2025-12-11 Ideal Power Inc. Methods of manufacturing bipolar junction devices

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5112761A (en) * 1990-01-10 1992-05-12 Microunity Systems Engineering Bicmos process utilizing planarization technique
GB2269938B (en) 1990-01-10 1994-09-07 Microunity Systems Eng Method of forming self-aligned contacts in a semi-conductor process
JP3352840B2 (ja) * 1994-03-14 2002-12-03 株式会社東芝 逆並列接続型双方向性半導体スイッチ
JP2003158131A (ja) * 2001-09-04 2003-05-30 Sanken Electric Co Ltd 半導体素子の製造方法
JP2004119498A (ja) * 2002-09-24 2004-04-15 Fuji Electric Device Technology Co Ltd 半導体装置の製造方法
US7064069B2 (en) * 2003-10-21 2006-06-20 Micron Technology, Inc. Substrate thinning including planarization
DE102004005384B4 (de) 2004-02-03 2006-10-26 De Doncker, Rik W., Prof. Dr. ir. Bidirektionales, MOS-gesteuertes Halbleiterbauelement, Verfahren zu seinem Betreiben, Verfahren zu seiner Herstellung und seine Verwendung
JP4791704B2 (ja) * 2004-04-28 2011-10-12 三菱電機株式会社 逆導通型半導体素子とその製造方法
US7354809B2 (en) * 2006-02-13 2008-04-08 Wisconsin Alumi Research Foundation Method for double-sided processing of thin film transistors
EP2025051B1 (en) 2006-06-06 2014-12-31 Ideal Power Inc. Universal power converter
DE102007058952A1 (de) 2007-09-24 2009-04-09 Osram Opto Semiconductors Gmbh Optoelektronisches Bauelement
US8093133B2 (en) 2008-04-04 2012-01-10 Semiconductor Components Industries, Llc Transient voltage suppressor and methods
US8163624B2 (en) * 2008-07-30 2012-04-24 Bowman Ronald R Discrete semiconductor device and method of forming sealed trench junction termination
KR20120130158A (ko) 2009-06-29 2012-11-29 아이디얼 파워 컨버터스, 인코포레이티드 에너지 전송 리액턴스를 단락시키는 크로바 스위치를 이용한 전력 전송 장치, 방법, 및 시스템
BR112012003612A2 (pt) 2009-08-17 2017-05-23 Ideal Power Converters Inc conversão de força com pseudofase acrescentada
EP2317553B1 (en) * 2009-10-28 2012-12-26 STMicroelectronics Srl Double-sided semiconductor structure and method for manufacturing the same
JP5379767B2 (ja) * 2010-09-02 2013-12-25 PVG Solutions株式会社 太陽電池セルおよびその製造方法
US9159825B2 (en) * 2010-10-12 2015-10-13 Silanna Semiconductor U.S.A., Inc. Double-sided vertical semiconductor device with thinned substrate
WO2012075172A2 (en) 2010-11-30 2012-06-07 Ideal Power Converters Inc. Photovoltaic array systems, methods, and devices and improved diagnostics and monitoring
CN102172826B (zh) * 2010-12-29 2012-11-28 杭州东华链条集团有限公司 一种正时链条的装配方法及装配装置
US20120279567A1 (en) 2011-02-18 2012-11-08 Ideal Power Converters Inc. Solar Energy System with Automatic Dehumidification of Electronics
US8531858B2 (en) 2011-02-18 2013-09-10 Ideal Power, Inc. Power conversion with current sensing coupled through saturating element
KR20130091200A (ko) * 2012-02-07 2013-08-16 삼성전자주식회사 트랜지스터 및 그 제조방법
EP2901483B1 (en) * 2013-06-24 2016-09-07 Ideal Power Inc. Systems, circuits, devices, and methods with bidirectional bipolar transistors

Also Published As

Publication number Publication date
GB2531485A (en) 2016-04-20
CN106062958B (zh) 2019-11-19
WO2015089227A1 (en) 2015-06-18
EP3055884A4 (en) 2016-12-07
GB2531485A8 (en) 2016-06-29
EP3055884B8 (en) 2023-04-26
EP3055884A1 (en) 2016-08-17
GB2531485B (en) 2016-06-22
EP3055884B1 (en) 2023-03-22
CN106062958A (zh) 2016-10-26
GB201602488D0 (en) 2016-03-30
JP2017509136A (ja) 2017-03-30

Similar Documents

Publication Publication Date Title
US9818615B2 (en) Systems and methods for bidirectional device fabrication
US11637016B2 (en) Systems and methods for bidirectional device fabrication
JP5621334B2 (ja) 半導体装置および半導体装置の製造方法
US20030153125A1 (en) Semiconductor device having element isolation structure
JP5761354B2 (ja) 半導体装置および半導体装置の製造方法
TW201243965A (en) Methods of forming bonded semiconductor structures, and semiconductor structures formed by such methods
CN105977230A (zh) 半导体装置
TW201826486A (zh) 基板之兩側上的ic結構及形成方法
JP2012182238A (ja) 半導体装置
CN110911499A (zh) 一种玻封电压调整二极管、管芯及其制造方法
JP6542775B2 (ja) 双方向デバイス製造のためのシステムおよび方法
JP4665429B2 (ja) 半導体素子の製造方法
WO2018151066A1 (ja) 積層半導体集積回路装置
CN107004578B (zh) 用于制造包括薄半导体晶圆的半导体器件的方法
JP2012182239A (ja) 半導体装置の製造方法
JP4724355B2 (ja) 半導体装置
TW201729339A (zh) 絕緣體上半導體型基板
JPH04123456A (ja) 半導体装置及びその製造方法
JP2017509136A5 (OSRAM)
JP2007266347A (ja) 半導体装置の製造方法
JPH02148821A (ja) 接着半導体基板
JP2012160738A (ja) 逆阻止型半導体素子の製造方法
KR101490350B1 (ko) 전력용 반도체 장치 및 제조방법
JPH0974202A (ja) 半導体装置及びその製造方法
JP2005217012A (ja) 半導体装置及びその製造方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20171124

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20171124

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20190115

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20190415

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20190514

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20190613

R150 Certificate of patent or registration of utility model

Ref document number: 6542775

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250