JP6497286B2 - 半導体モジュール - Google Patents
半導体モジュール Download PDFInfo
- Publication number
- JP6497286B2 JP6497286B2 JP2015185802A JP2015185802A JP6497286B2 JP 6497286 B2 JP6497286 B2 JP 6497286B2 JP 2015185802 A JP2015185802 A JP 2015185802A JP 2015185802 A JP2015185802 A JP 2015185802A JP 6497286 B2 JP6497286 B2 JP 6497286B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- substrate
- semiconductor
- pattern
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/074—Stacked arrangements of non-apertured devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/003—Constructional details, e.g. physical layout, assembly, wiring or busbar connections
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
- H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
- H02M7/53871—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current
- H02M7/53875—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current with analogue control of three-phase output
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0605—Shape
- H01L2224/06051—Bonding areas having different shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
- H01L2224/081—Disposition
- H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/08151—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/08221—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/08225—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/08238—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bonding area connecting to a bonding area protruding from the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
- H01L2924/15333—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a land array, e.g. LGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19106—Disposition of discrete passive components in a mirrored arrangement on two different side of a common die mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Inverter Devices (AREA)
Description
本発明の第1実施形態について説明する。ここでは、本実施形態にかかる半導体モジュール1を、車両用の三相交流モータなどの駆動を行うインバータ回路に適用した例について説明する。
本発明の第2実施形態について説明する。本実施形態は、第1実施形態に対してコンデンサ40の数を変更したものであり、その他に関しては第1実施形態と同様であるため、第1実施形態と異なる部分についてのみ説明する。
本発明の第3実施形態について説明する。本実施形態は、第1実施形態に対してコンデンサ40の配置と、基板10、第1パターン20および第2パターン30の構成とを変更したものであり、その他に関しては第1実施形態と同様であるため、第1実施形態と異なる部分についてのみ説明する。
本発明の第4実施形態について説明する。本実施形態は、第3実施形態に対してコンデンサ40の構成を変更したものであり、その他に関しては第3実施形態と同様であるため、第1実施形態と異なる部分についてのみ説明する。
本発明の第5実施形態について説明する。本実施形態は、第1実施形態に対して放熱板を追加したものであり、その他に関しては第1実施形態と同様であるため、第1実施形態と異なる部分についてのみ説明する。
なお、本発明は上記した実施形態に限定されるものではなく、特許請求の範囲に記載した範囲内において適宜変更が可能である。
12 ビア
13 ビア
20 第1パターン
30 第2パターン
40 コンデンサ
50 第1半導体素子
60 第2半導体素子
Claims (14)
- 絶縁層(11)を備えるとともに、前記絶縁層の表面と裏面とを接続する接続部(12、13)が形成された基板(10)と、
前記基板の表面に形成された配線パターンである第1パターン(20)と、
前記基板の裏面に形成された配線パターンである第2パターン(30)と、
前記基板の表面側に配置されるとともに、横型構造の第1スイッチング素子(51、71、91)を備える第1半導体素子(50、70、90)と、
前記基板の裏面側に配置されるとともに、横型構造の第2スイッチング素子(61、81、101)を備える第2半導体素子(60、80、100)と、
コンデンサ(40)と、を備え、
前記第1スイッチング素子は、第1ドレイン電極(51d)および第1ソース電極(51f)を備え、
前記第2スイッチング素子は、第2ドレイン電極(61d)および第2ソース電極(61f)を備え、
前記第1パターン、前記第2パターン、および前記接続部は、前記第1半導体素子、前記第2半導体素子、および前記コンデンサを電気的に接続するループ経路(Pa1)を構成し、
前記第1ソース電極は前記第2ドレイン電極に接続され、
前記第1ドレイン電極は前記コンデンサを通して前記第2ソース電極に接続され、
前記ループ経路において、前記第1パターンおよび前記第1半導体素子が構成する経路と、前記第2パターンおよび前記第2半導体素子が構成する経路とは、前記基板を挟んで対向しており、かつ、互いに逆の向きに電流を流し、
前記ループ経路は、前記第1パターン、前記第2パターン、前記接続部、前記第1半導体素子、前記第2半導体素子、前記コンデンサのみを通る経路とされており、
前記基板は、前記絶縁層を複数備え、複数の前記絶縁層が配線層(14)を介して積層された多層基板とされ、
前記絶縁層および前記配線層により、前記第1半導体素子および前記第2半導体素子を制御するための制御回路(5)が構成されており、
前記基板のうち前記第1半導体素子および前記第2半導体素子が配置される部分の前記配線層の数は、前記制御回路を構成する部分の前記配線層の数以下とされていることを特徴とする半導体モジュール。 - 絶縁層(11)を備えるとともに、前記絶縁層の表面と裏面とを接続する接続部(12、13)が形成された基板(10)と、
前記基板の表面に形成された配線パターンである第1パターン(20)と、
前記基板の裏面に形成された配線パターンである第2パターン(30)と、
前記基板の表面側に配置されるとともに、横型構造の第1スイッチング素子(51、71、91)を備える第1半導体素子(50、70、90)と、
前記基板の裏面側に配置されるとともに、横型構造の第2スイッチング素子(61、81、101)を備える第2半導体素子(60、80、100)と、
コンデンサ(40)と、
前記コンデンサに対して直列に接続された抵抗体(15)と、を備え、
前記第1スイッチング素子は、第1ドレイン電極(51d)および第1ソース電極(51f)を備え、
前記第2スイッチング素子は、第2ドレイン電極(61d)および第2ソース電極(61f)を備え、
前記第1パターン、前記第2パターン、および前記接続部は、前記第1半導体素子、前記第2半導体素子、および前記コンデンサを電気的に接続するループ経路(Pa1)を構成し、
前記第1ソース電極は前記第2ドレイン電極に接続され、
前記第1ドレイン電極は前記コンデンサを通して前記第2ソース電極に接続され、
前記ループ経路において、前記第1パターンおよび前記第1半導体素子が構成する経路と、前記第2パターンおよび前記第2半導体素子が構成する経路とは、前記基板を挟んで対向しており、かつ、互いに逆の向きに電流を流し、
前記ループ経路は、前記第1パターン、前記第2パターン、前記接続部、前記第1半導体素子、前記第2半導体素子、前記コンデンサ、前記抵抗体のみを通る経路とされており、
前記基板は、前記絶縁層を複数備え、複数の前記絶縁層が配線層(14)を介して積層された多層基板とされ、
前記絶縁層および前記配線層により、前記第1半導体素子および前記第2半導体素子を制御するための制御回路(5)が構成されており、
前記基板のうち前記第1半導体素子および前記第2半導体素子が配置される部分の前記配線層の数は、前記制御回路を構成する部分の前記配線層の数以下とされていることを特徴とする半導体モジュール。 - 前記第1半導体素子および前記第2半導体素子は、前記基板を挟んで対向するように配置されていることを特徴とする請求項1または2に記載の半導体モジュール。
- 前記コンデンサを複数備え、
複数の前記コンデンサは、前記ループ経路において直列に接続されていることを特徴とする請求項1ないし3のいずれか1つに記載の半導体モジュール。 - 前記コンデンサは、前記基板の表面に平行な一方向から見て少なくとも一部が前記基板と重なるように配置されており、かつ、2つの電極のうちの一方が前記第1パターンと接続され、他方が前記第2パターンと接続されていることを特徴とする請求項1ないし4のいずれか1つに記載の半導体モジュール。
- 前記絶縁層を挟んで対向させられた前記第1パターンと前記第2パターンとによって前記コンデンサが構成されていることを特徴とする請求項1ないし5のいずれか1つに記載の半導体モジュール。
- 前記第1半導体素子を冷却する導電性の第1放熱板(110)と、
前記第2半導体素子を冷却する導電性の第2放熱板(120)と、を備えることを特徴とする請求項1ないし6のいずれか1つに記載の半導体モジュール。 - 前記第1スイッチング素子は、第1基板(51a)と、前記第1基板の表面に形成された第1積層体(51b)とを備え、
前記第1ドレイン電極および前記第1ソース電極は、前記第1積層体の表面に形成され、
前記第1放熱板は、前記第1パターンおよび前記第1基板と接続されていることを特徴とする請求項7に記載の半導体モジュール。 - 前記第2スイッチング素子は、第2基板(61a)と、前記第2基板の表面に形成された第2積層体(61b)とを備え、
前記第2ドレイン電極および前記第2ソース電極は、前記第2積層体の表面に形成され、
前記第2放熱板は、前記第2パターンおよび前記第2基板と接続されていることを特徴とする請求項7または8に記載の半導体モジュール。 - 前記第1半導体素子または前記第2半導体素子を制御するための制御端子(141、142、143、144)を備え、
前記制御端子は、前記ループ経路を流れる電流の方向に対して垂直に延設されていることを特徴とする請求項1ないし9のいずれか1つに記載の半導体モジュール。 - 前記基板のうち前記第1半導体素子および前記第2半導体素子が配置される部分は、1つの前記絶縁層の表面に前記第1パターンが形成され、裏面に前記第2パターンが形成された構造とされていることを特徴とする請求項1ないし10のいずれか1つに記載の半導体モジュール。
- 前記第1半導体素子は、前記第1スイッチング素子を複数備え、
前記第2半導体素子は、前記第2スイッチング素子を複数備えることを特徴とする請求項1ないし11のいずれか1つに記載の半導体モジュール。 - 前記第1半導体素子は、前記第1スイッチング素子と並列に接続された第1整流素子(52、72、92)を備え、
前記第2半導体素子は、前記第2スイッチング素子と並列に接続された第2整流素子(62、82、102)を備えることを特徴とする請求項1ないし12のいずれか1つに記載の半導体モジュール。 - 前記第1半導体素子および前記第2半導体素子をそれぞれ複数備え、
前記ループ経路は、複数の前記第1半導体素子および複数の前記第2半導体素子により複数構成され、
前記ループ経路を含む回路が複数構成され、
前記ループ経路を含む回路は、前記第1半導体素子および前記第2半導体素子に電力を供給する電源(2)に対してそれぞれ並列に接続されていることを特徴とする請求項1ないし13のいずれか1つに記載の半導体モジュール。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2015185802A JP6497286B2 (ja) | 2015-09-18 | 2015-09-18 | 半導体モジュール |
PCT/JP2016/074729 WO2017047345A1 (ja) | 2015-09-18 | 2016-08-25 | 半導体モジュール |
US15/748,210 US10283488B2 (en) | 2015-09-18 | 2016-08-25 | Semiconductor module |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2015185802A JP6497286B2 (ja) | 2015-09-18 | 2015-09-18 | 半導体モジュール |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2017059778A JP2017059778A (ja) | 2017-03-23 |
JP6497286B2 true JP6497286B2 (ja) | 2019-04-10 |
Family
ID=58288822
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2015185802A Active JP6497286B2 (ja) | 2015-09-18 | 2015-09-18 | 半導体モジュール |
Country Status (3)
Country | Link |
---|---|
US (1) | US10283488B2 (ja) |
JP (1) | JP6497286B2 (ja) |
WO (1) | WO2017047345A1 (ja) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102015223599A1 (de) * | 2015-11-27 | 2017-06-01 | Robert Bosch Gmbh | Leistungsmodul für einen Elektromotor |
JP6972686B2 (ja) * | 2017-06-15 | 2021-11-24 | 株式会社ジェイテクト | 半導体装置 |
WO2018235484A1 (ja) * | 2017-06-21 | 2018-12-27 | 住友電気工業株式会社 | 電子回路装置 |
US11107761B2 (en) | 2018-02-06 | 2021-08-31 | Denso Corporation | Semiconductor device |
JP2019186403A (ja) * | 2018-04-11 | 2019-10-24 | トヨタ自動車株式会社 | 半導体装置 |
JP7091954B2 (ja) * | 2018-09-06 | 2022-06-28 | 株式会社デンソー | 電子装置 |
WO2020059880A1 (ja) * | 2018-09-21 | 2020-03-26 | 国立大学法人東北大学 | 交流電圧出力システム、電力系統制御システム、電力系統、直流送電システム、発電システム及びバッテリシステム |
JP7215194B2 (ja) * | 2019-01-30 | 2023-01-31 | 富士電機株式会社 | スナバ装置および電力変換装置 |
DE102021214906A1 (de) | 2021-10-14 | 2023-04-20 | Vitesco Technologies Germany Gmbh | Elektronische Baugruppe |
WO2023175675A1 (ja) * | 2022-03-14 | 2023-09-21 | 三菱電機株式会社 | パワーモジュール半導体パッケージおよび半導体装置 |
WO2023243418A1 (ja) * | 2022-06-15 | 2023-12-21 | ローム株式会社 | 半導体装置 |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0359513A3 (en) | 1988-09-14 | 1990-12-19 | Hitachi, Ltd. | Semiconductor chip carrier and method of making it |
JP2776909B2 (ja) * | 1988-09-14 | 1998-07-16 | 株式会社日立製作所 | キヤリア基板 |
JPH07273276A (ja) * | 1994-03-28 | 1995-10-20 | Nissan Motor Co Ltd | パワー素子とスナバ素子の接続構造及びその実装構造 |
JP2002026251A (ja) * | 2000-07-11 | 2002-01-25 | Toshiba Corp | 半導体装置 |
JP3723869B2 (ja) * | 2001-03-30 | 2005-12-07 | 株式会社日立製作所 | 半導体装置 |
JP4016384B2 (ja) * | 2002-06-17 | 2007-12-05 | 株式会社安川電機 | パワーモジュールおよびこれを用いたモータ制御装置 |
JP4424918B2 (ja) * | 2003-03-24 | 2010-03-03 | 東芝エレベータ株式会社 | 電力変換装置 |
JP2006073655A (ja) * | 2004-08-31 | 2006-03-16 | Toshiba Corp | 半導体モジュール |
JP5103927B2 (ja) * | 2007-02-12 | 2012-12-19 | 株式会社デンソー | 電力変換装置 |
JP5287359B2 (ja) * | 2009-03-04 | 2013-09-11 | 株式会社デンソー | 半導体モジュール |
JP5253430B2 (ja) * | 2009-03-23 | 2013-07-31 | 株式会社豊田中央研究所 | パワーモジュール |
JP5581724B2 (ja) | 2010-02-22 | 2014-09-03 | ダイキン工業株式会社 | 電力変換装置 |
JP5655339B2 (ja) * | 2010-03-26 | 2015-01-21 | サンケン電気株式会社 | 半導体装置 |
JP5259016B2 (ja) * | 2010-05-21 | 2013-08-07 | 三菱電機株式会社 | パワー半導体モジュール |
EP2811642A4 (en) * | 2012-01-31 | 2015-10-07 | Yaskawa Denki Seisakusho Kk | ELECTRIC POWER CONVERTING DEVICE AND METHOD FOR MANUFACTURING ELECTRIC POWER CONVERTING DEVICE |
JP2014038982A (ja) * | 2012-08-20 | 2014-02-27 | Ihi Corp | 半導体パワーモジュール |
JP6386746B2 (ja) * | 2014-02-26 | 2018-09-05 | 株式会社ジェイデバイス | 半導体装置 |
JP6179476B2 (ja) * | 2014-07-31 | 2017-08-16 | 株式会社デンソー | 駆動装置、および、これを用いた電動パワーステアリング装置 |
-
2015
- 2015-09-18 JP JP2015185802A patent/JP6497286B2/ja active Active
-
2016
- 2016-08-25 US US15/748,210 patent/US10283488B2/en active Active
- 2016-08-25 WO PCT/JP2016/074729 patent/WO2017047345A1/ja active Application Filing
Also Published As
Publication number | Publication date |
---|---|
US10283488B2 (en) | 2019-05-07 |
US20180226383A1 (en) | 2018-08-09 |
WO2017047345A1 (ja) | 2017-03-23 |
JP2017059778A (ja) | 2017-03-23 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6497286B2 (ja) | 半導体モジュール | |
JP6188902B2 (ja) | 電力用半導体モジュール及び電力変換装置 | |
JP6865838B2 (ja) | 半導体モジュール及び電力変換装置 | |
JP5447453B2 (ja) | スイッチングモジュール | |
JP5798412B2 (ja) | 半導体モジュール | |
JP5259016B2 (ja) | パワー半導体モジュール | |
JP4973059B2 (ja) | 半導体装置及び電力変換装置 | |
JP5218541B2 (ja) | スイッチングモジュール | |
KR101998424B1 (ko) | 반도체 모듈 | |
JP6709810B2 (ja) | 低誘導性ハーフブリッジ装置 | |
JP6096614B2 (ja) | パワー半導体モジュールおよびそれを用いた電力変換装置 | |
JP2015211524A (ja) | 半導体モジュール | |
JP6256419B2 (ja) | 半導体チップおよびそれを用いた半導体モジュール | |
JP6318563B2 (ja) | バスバー、およびそれを用いた電力変換装置 | |
JP2009272482A (ja) | 半導体装置 | |
JP6206338B2 (ja) | スイッチングモジュール | |
JP2019029457A (ja) | 半導体モジュール | |
JP2019110228A (ja) | 電力変換装置 | |
JP2021177519A (ja) | 半導体装置 | |
JP4356434B2 (ja) | 3レベルインバータ回路 | |
JP2022050887A (ja) | 半導体装置 | |
JP2015053410A (ja) | 半導体モジュール | |
JP5171199B2 (ja) | パワーモジュール | |
US11251162B2 (en) | Semiconductor device with reduced thermal resistance | |
JP5737622B2 (ja) | 直流電源装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20171002 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20180424 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20180620 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20180925 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20181113 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20190212 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20190225 |
|
R151 | Written notification of patent or utility model registration |
Ref document number: 6497286 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R151 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |