JP6410538B2 - 半導体集積回路、半導体集積回路を備えた装置、半導体集積回路におけるクロックの制御方法、並びにプログラム。 - Google Patents
半導体集積回路、半導体集積回路を備えた装置、半導体集積回路におけるクロックの制御方法、並びにプログラム。 Download PDFInfo
- Publication number
- JP6410538B2 JP6410538B2 JP2014190390A JP2014190390A JP6410538B2 JP 6410538 B2 JP6410538 B2 JP 6410538B2 JP 2014190390 A JP2014190390 A JP 2014190390A JP 2014190390 A JP2014190390 A JP 2014190390A JP 6410538 B2 JP6410538 B2 JP 6410538B2
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- clock
- clock signal
- output
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00286—Phase shifter, i.e. the delay between the output and input pulse is dependent on the frequency, and such that a phase difference is obtained independent of the frequency
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Power Sources (AREA)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2014190390A JP6410538B2 (ja) | 2014-09-18 | 2014-09-18 | 半導体集積回路、半導体集積回路を備えた装置、半導体集積回路におけるクロックの制御方法、並びにプログラム。 |
| US14/853,676 US9419599B2 (en) | 2014-09-18 | 2015-09-14 | Semiconductor integrated circuit, apparatus including semiconductor integrated circuit, and method for controlling clock signal in semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2014190390A JP6410538B2 (ja) | 2014-09-18 | 2014-09-18 | 半導体集積回路、半導体集積回路を備えた装置、半導体集積回路におけるクロックの制御方法、並びにプログラム。 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2016062355A JP2016062355A (ja) | 2016-04-25 |
| JP2016062355A5 JP2016062355A5 (https=) | 2017-10-26 |
| JP6410538B2 true JP6410538B2 (ja) | 2018-10-24 |
Family
ID=55526719
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2014190390A Expired - Fee Related JP6410538B2 (ja) | 2014-09-18 | 2014-09-18 | 半導体集積回路、半導体集積回路を備えた装置、半導体集積回路におけるクロックの制御方法、並びにプログラム。 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US9419599B2 (https=) |
| JP (1) | JP6410538B2 (https=) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US12587003B2 (en) * | 2021-06-30 | 2026-03-24 | Autonetworks Technologies, Ltd. | On-board device |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6681244B2 (ja) * | 2016-03-30 | 2020-04-15 | キヤノン株式会社 | 画像処理装置、その制御方法、及びプログラム |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6194932B1 (en) * | 1997-10-20 | 2001-02-27 | Fujitsu Limited | Integrated circuit device |
| US5939911A (en) * | 1998-03-05 | 1999-08-17 | Motorola, Inc. | Frequency prescaler method and apparatus responsive to low input drive levels |
| JP4190662B2 (ja) * | 1999-06-18 | 2008-12-03 | エルピーダメモリ株式会社 | 半導体装置及びタイミング制御回路 |
| JP2002351571A (ja) * | 2001-05-25 | 2002-12-06 | Yaskawa Electric Corp | クロック供給停止回路 |
| JP4111932B2 (ja) * | 2004-05-21 | 2008-07-02 | 富士通株式会社 | クロック分周器とそのトリガ信号発生回路 |
| KR100674910B1 (ko) * | 2004-07-06 | 2007-01-26 | 삼성전자주식회사 | 글리치를 유발하지 않는 클럭 스위칭 회로 |
| US7088156B2 (en) * | 2004-08-31 | 2006-08-08 | Micron Technology, Inc. | Delay-locked loop having a pre-shift phase detector |
| KR100903365B1 (ko) | 2007-11-02 | 2009-06-23 | 주식회사 하이닉스반도체 | 반도체 메모리 장치 |
| JP2013008133A (ja) * | 2011-06-23 | 2013-01-10 | Yokogawa Electric Corp | マイコンのクロック制御回路 |
| JP6429549B2 (ja) * | 2014-09-18 | 2018-11-28 | キヤノン株式会社 | 半導体集積回路、半導体集積回路を備えた装置、半導体集積回路におけるクロックの制御方法、並びにプログラム。 |
-
2014
- 2014-09-18 JP JP2014190390A patent/JP6410538B2/ja not_active Expired - Fee Related
-
2015
- 2015-09-14 US US14/853,676 patent/US9419599B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US12587003B2 (en) * | 2021-06-30 | 2026-03-24 | Autonetworks Technologies, Ltd. | On-board device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2016062355A (ja) | 2016-04-25 |
| US20160087617A1 (en) | 2016-03-24 |
| US9419599B2 (en) | 2016-08-16 |
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