JP6343122B2 - 半導体装置の作製方法 - Google Patents

半導体装置の作製方法 Download PDF

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Publication number
JP6343122B2
JP6343122B2 JP2013080152A JP2013080152A JP6343122B2 JP 6343122 B2 JP6343122 B2 JP 6343122B2 JP 2013080152 A JP2013080152 A JP 2013080152A JP 2013080152 A JP2013080152 A JP 2013080152A JP 6343122 B2 JP6343122 B2 JP 6343122B2
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Prior art keywords
wiring
insulating layer
layer
oxygen
oxide
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Expired - Fee Related
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Japanese (ja)
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JP2013236066A (ja
JP2013236066A5 (enExample
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山崎 舜平
舜平 山崎
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority to JP2013080152A priority Critical patent/JP6343122B2/ja
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Publication of JP2013236066A5 publication Critical patent/JP2013236066A5/ja
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60Protection against electrostatic charges or discharges, e.g. Faraday shields
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441Interconnections, e.g. scanning lines
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441Interconnections, e.g. scanning lines
    • H10D86/443Interconnections, e.g. scanning lines adapted for preventing breakage, peeling or short circuiting
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Thin Film Transistor (AREA)
  • Electroluminescent Light Sources (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2013080152A 2012-04-13 2013-04-08 半導体装置の作製方法 Expired - Fee Related JP6343122B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2013080152A JP6343122B2 (ja) 2012-04-13 2013-04-08 半導体装置の作製方法

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2012092351 2012-04-13
JP2012092351 2012-04-13
JP2013080152A JP6343122B2 (ja) 2012-04-13 2013-04-08 半導体装置の作製方法

Related Child Applications (1)

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JP2018043860A Division JP6480619B2 (ja) 2012-04-13 2018-03-12 半導体装置

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JP2013236066A JP2013236066A (ja) 2013-11-21
JP2013236066A5 JP2013236066A5 (enExample) 2016-03-10
JP6343122B2 true JP6343122B2 (ja) 2018-06-13

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JP2018043860A Expired - Fee Related JP6480619B2 (ja) 2012-04-13 2018-03-12 半導体装置

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US (2) US9166054B2 (enExample)
JP (2) JP6343122B2 (enExample)
KR (1) KR102034900B1 (enExample)

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CN103441119B (zh) * 2013-07-05 2016-03-30 京东方科技集团股份有限公司 一种制造esd器件的方法、esd器件和显示面板
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KR102099881B1 (ko) 2013-09-03 2020-05-15 삼성전자 주식회사 반도체 소자 및 그 제조 방법
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JP6444714B2 (ja) * 2013-12-20 2018-12-26 株式会社半導体エネルギー研究所 半導体装置の作製方法
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JP2019161182A (ja) * 2018-03-16 2019-09-19 株式会社リコー 電界効果型トランジスタ及びその製造方法、表示素子、表示装置、システム
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Publication number Publication date
US9166054B2 (en) 2015-10-20
US20160043112A1 (en) 2016-02-11
JP2018101807A (ja) 2018-06-28
JP2013236066A (ja) 2013-11-21
KR20130116016A (ko) 2013-10-22
KR102034900B1 (ko) 2019-10-21
US10153307B2 (en) 2018-12-11
JP6480619B2 (ja) 2019-03-13
US20130270562A1 (en) 2013-10-17

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