JP6316609B2 - 配線基板及び半導体装置と配線基板の製造方法及び半導体装置の製造方法 - Google Patents

配線基板及び半導体装置と配線基板の製造方法及び半導体装置の製造方法 Download PDF

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Publication number
JP6316609B2
JP6316609B2 JP2014019980A JP2014019980A JP6316609B2 JP 6316609 B2 JP6316609 B2 JP 6316609B2 JP 2014019980 A JP2014019980 A JP 2014019980A JP 2014019980 A JP2014019980 A JP 2014019980A JP 6316609 B2 JP6316609 B2 JP 6316609B2
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Japan
Prior art keywords
insulating layer
layer
electrode pad
wiring
stacked
Prior art date
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Application number
JP2014019980A
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English (en)
Japanese (ja)
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JP2015149325A5 (enExample
JP2015149325A (ja
Inventor
大井　淳
淳 大井
栗原　孝
孝 栗原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2014019980A priority Critical patent/JP6316609B2/ja
Priority to US14/561,540 priority patent/US9622347B2/en
Publication of JP2015149325A publication Critical patent/JP2015149325A/ja
Publication of JP2015149325A5 publication Critical patent/JP2015149325A5/ja
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/113—Via provided in pad; Pad over filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4661—Adding a circuit layer by direct wet plating, e.g. electroless plating; insulating materials adapted therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09472—Recessed pad for surface mounting; Recessed electrode of component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/096—Vertically aligned vias, holes or stacked vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/654—Top-view layouts
    • H10W70/655—Fan-out layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2014019980A 2014-02-05 2014-02-05 配線基板及び半導体装置と配線基板の製造方法及び半導体装置の製造方法 Active JP6316609B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2014019980A JP6316609B2 (ja) 2014-02-05 2014-02-05 配線基板及び半導体装置と配線基板の製造方法及び半導体装置の製造方法
US14/561,540 US9622347B2 (en) 2014-02-05 2014-12-05 Wiring substrate, semiconductor device, method of manufacturing wiring substrate, and method of manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2014019980A JP6316609B2 (ja) 2014-02-05 2014-02-05 配線基板及び半導体装置と配線基板の製造方法及び半導体装置の製造方法

Publications (3)

Publication Number Publication Date
JP2015149325A JP2015149325A (ja) 2015-08-20
JP2015149325A5 JP2015149325A5 (enExample) 2016-10-27
JP6316609B2 true JP6316609B2 (ja) 2018-04-25

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JP2014019980A Active JP6316609B2 (ja) 2014-02-05 2014-02-05 配線基板及び半導体装置と配線基板の製造方法及び半導体装置の製造方法

Country Status (2)

Country Link
US (1) US9622347B2 (enExample)
JP (1) JP6316609B2 (enExample)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI578472B (zh) * 2014-11-27 2017-04-11 矽品精密工業股份有限公司 封裝基板、半導體封裝件及其製法
JP2016134409A (ja) * 2015-01-16 2016-07-25 イビデン株式会社 プリント配線板
KR102472945B1 (ko) * 2015-04-23 2022-12-01 삼성전기주식회사 인쇄회로기판, 반도체 패키지 및 그 제조방법
JP2017139316A (ja) 2016-02-03 2017-08-10 ソニー株式会社 半導体装置および製造方法、並びに電子機器
JP6729044B2 (ja) * 2016-06-20 2020-07-22 大日本印刷株式会社 配線基板およびその製造方法、ならびに半導体装置の製造方法
CN111954388B (zh) * 2019-05-17 2022-03-15 欣兴电子股份有限公司 线路板及其制作方法
TWI701979B (zh) * 2019-05-17 2020-08-11 欣興電子股份有限公司 線路板及其製作方法
KR102867266B1 (ko) * 2020-10-20 2025-10-01 삼성전자주식회사 모듈 기판 및 이를 포함하는 반도체 모듈
JP7646495B2 (ja) 2021-08-17 2025-03-17 キオクシア株式会社 半導体装置およびその製造方法
US20250038056A1 (en) * 2023-07-25 2025-01-30 Wolfspeed, Inc. Submounts with Stud Protrusions for Semiconductor Packages

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000068643A (ja) * 1998-08-18 2000-03-03 Hitachi Ltd 絶縁層表面の粗化方法並びに配線基板及びその製造方法
JP4127442B2 (ja) 1999-02-22 2008-07-30 イビデン株式会社 多層ビルドアップ配線板及びその製造方法
KR100855529B1 (ko) 1998-09-03 2008-09-01 이비덴 가부시키가이샤 다층프린트배선판 및 그 제조방법
JP2002217240A (ja) * 2001-01-19 2002-08-02 Nec Tohoku Ltd フリップチップ実装構造及び配線方法
JP4198566B2 (ja) * 2003-09-29 2008-12-17 新光電気工業株式会社 電子部品内蔵基板の製造方法
JP2006073593A (ja) * 2004-08-31 2006-03-16 Toshiba Corp 配線基板とそれを用いた半導体装置
JP2008112987A (ja) 2006-10-04 2008-05-15 Ngk Spark Plug Co Ltd 配線基板
US8319111B2 (en) 2006-10-04 2012-11-27 Ngk Spark Plug Co., Ltd. Wiring board having wiring laminate portion with via conductors embedded in resin insulating layers
WO2008053833A1 (fr) * 2006-11-03 2008-05-08 Ibiden Co., Ltd. Tableau de câblage imprimé multicouche
KR100850243B1 (ko) * 2007-07-26 2008-08-04 삼성전기주식회사 인쇄회로기판 및 그 제조방법
JP5150518B2 (ja) * 2008-03-25 2013-02-20 パナソニック株式会社 半導体装置および多層配線基板ならびにそれらの製造方法
JP2009277916A (ja) 2008-05-15 2009-11-26 Shinko Electric Ind Co Ltd 配線基板及びその製造方法並びに半導体パッケージ
US8528200B2 (en) * 2009-12-18 2013-09-10 Ibiden Co., Ltd. Printed wiring board and method for manufacturing printed wiring board

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Publication number Publication date
US9622347B2 (en) 2017-04-11
JP2015149325A (ja) 2015-08-20
US20150223330A1 (en) 2015-08-06

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