JP6304700B2 - 半導体パッケージ、モジュールおよび電気機器 - Google Patents

半導体パッケージ、モジュールおよび電気機器 Download PDF

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Publication number
JP6304700B2
JP6304700B2 JP2017018254A JP2017018254A JP6304700B2 JP 6304700 B2 JP6304700 B2 JP 6304700B2 JP 2017018254 A JP2017018254 A JP 2017018254A JP 2017018254 A JP2017018254 A JP 2017018254A JP 6304700 B2 JP6304700 B2 JP 6304700B2
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Prior art keywords
electrode
semiconductor layer
parallel
electrode pad
semiconductor
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JP2017018254A
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English (en)
Japanese (ja)
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JP2018056538A (ja
Inventor
弘治 河合
弘治 河合
八木　修一
修一 八木
祥子 越後谷
祥子 越後谷
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Powdec KK
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Powdec KK
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Priority to PCT/JP2017/034411 priority Critical patent/WO2018056426A1/ja
Priority to CN201780026378.0A priority patent/CN109075148B/zh
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Publication of JP6304700B2 publication Critical patent/JP6304700B2/ja
Publication of JP2018056538A publication Critical patent/JP2018056538A/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Metal Substrates For Printed Circuits (AREA)
  • Structure Of Printed Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Led Devices (AREA)
  • Led Device Packages (AREA)
JP2017018254A 2016-09-26 2017-02-03 半導体パッケージ、モジュールおよび電気機器 Active JP6304700B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/JP2017/034411 WO2018056426A1 (ja) 2016-09-26 2017-09-25 半導体パッケージ、モジュールおよび電気機器
CN201780026378.0A CN109075148B (zh) 2016-09-26 2017-09-25 半导体封装体、安装有半导体封装体的模块及电气设备

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2016186741 2016-09-26
JP2016186741 2016-09-26

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2018031547A Division JP6744610B2 (ja) 2016-09-26 2018-02-26 半導体パッケージ、モジュールおよび電気機器

Publications (2)

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JP6304700B2 true JP6304700B2 (ja) 2018-04-04
JP2018056538A JP2018056538A (ja) 2018-04-05

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JP2017018254A Active JP6304700B2 (ja) 2016-09-26 2017-02-03 半導体パッケージ、モジュールおよび電気機器
JP2018031547A Active JP6744610B2 (ja) 2016-09-26 2018-02-26 半導体パッケージ、モジュールおよび電気機器

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JP2018031547A Active JP6744610B2 (ja) 2016-09-26 2018-02-26 半導体パッケージ、モジュールおよび電気機器

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JP (2) JP6304700B2 (enrdf_load_stackoverflow)
CN (1) CN109075148B (enrdf_load_stackoverflow)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115656298A (zh) * 2022-10-25 2023-01-31 电子科技大学 一种基于oect的人工神经突触及其制备方法

Families Citing this family (11)

* Cited by examiner, † Cited by third party
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US10912195B2 (en) * 2019-01-02 2021-02-02 The Boeing Company Multi-embedded radio frequency board and mobile device including the same
CN110113877B (zh) * 2019-06-06 2021-11-05 景旺电子科技(龙川)有限公司 一种激光切割法制作金属基线路板的方法
WO2021002225A1 (ja) * 2019-07-01 2021-01-07 ローム株式会社 半導体装置
JP7088132B2 (ja) * 2019-07-10 2022-06-21 株式会社デンソー 半導体装置及び電子装置
JP7298467B2 (ja) * 2019-12-17 2023-06-27 三菱電機株式会社 半導体モジュールおよび半導体装置
WO2022055248A1 (ko) * 2020-09-08 2022-03-17 한양대학교에리카산학협력단 열전 복합체 및 그 제조방법, 그리고 열전 복합체를 포함하는 열전 소자 및 반도체 소자
KR102597072B1 (ko) * 2020-09-08 2023-11-01 한양대학교 에리카산학협력단 이성분계 산화물 2deg 및 2dhg 열전 소자 기반 능동 냉각 장치 및 그 제조방법
JP7337034B2 (ja) * 2020-09-15 2023-09-01 三菱電機株式会社 半導体パッケージおよび半導体装置
CN112687740B (zh) * 2020-12-30 2022-06-21 江苏大学 一种AlGaN/GaN高电子迁移率晶体管及制造方法
JP7571743B2 (ja) * 2022-02-04 2024-10-23 株式会社デンソー 半導体装置
WO2025033552A1 (ja) * 2023-08-10 2025-02-13 京セラ株式会社 回路及び半導体素子

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JPH06821Y2 (ja) * 1987-12-25 1994-01-05 シチズン時計株式会社 半導体装置の実装構造
JP2001168123A (ja) * 1999-12-09 2001-06-22 Seiko Epson Corp 半導体装置及びその製造方法、半導体装置の製造装置、回路基板並びに電子機器
JP2001358259A (ja) * 2000-06-15 2001-12-26 Seiko Epson Corp 半導体パッケージ
JP2003338519A (ja) * 2002-05-21 2003-11-28 Renesas Technology Corp 半導体装置及びその製造方法
JP3918681B2 (ja) * 2002-08-09 2007-05-23 カシオ計算機株式会社 半導体装置
JP4386239B2 (ja) * 2003-03-12 2009-12-16 株式会社ルネサステクノロジ 半導体装置及びその製造方法
JP2006049682A (ja) * 2004-08-06 2006-02-16 Toshiba Corp 半導体装置及びその製造方法
JP4549171B2 (ja) * 2004-08-31 2010-09-22 三洋電機株式会社 混成集積回路装置
JP2009081293A (ja) * 2007-09-26 2009-04-16 Oki Semiconductor Co Ltd 半導体チップ、及び複数の半導体チップが搭載された半導体装置
TWI402017B (zh) * 2008-07-23 2013-07-11 Nec Corp 半導體裝置及其製造方法
JP2010050286A (ja) * 2008-08-21 2010-03-04 Toshiba Corp 半導体装置
JP2010283265A (ja) * 2009-06-08 2010-12-16 Mitsubishi Electric Corp 電気回路用気密パッケージ及び電気回路用気密パッケージの製造方法
JP5155989B2 (ja) * 2009-11-30 2013-03-06 旭化成エレクトロニクス株式会社 半導体装置及びその製造方法
JP2014143326A (ja) * 2013-01-24 2014-08-07 Transphorm Japan Inc 半導体装置、半導体装置の製造方法、リード、及びリードの製造方法
JP2015142077A (ja) * 2014-01-30 2015-08-03 株式会社東芝 半導体装置
JP5828435B1 (ja) * 2015-02-03 2015-12-09 株式会社パウデック 半導体素子、電気機器、双方向電界効果トランジスタおよび実装構造体
JP2016171197A (ja) * 2015-03-12 2016-09-23 株式会社東芝 半導体装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115656298A (zh) * 2022-10-25 2023-01-31 电子科技大学 一种基于oect的人工神经突触及其制备方法

Also Published As

Publication number Publication date
CN109075148B (zh) 2019-08-16
CN109075148A (zh) 2018-12-21
JP6744610B2 (ja) 2020-08-19
JP2018093221A (ja) 2018-06-14
JP2018056538A (ja) 2018-04-05

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