JP6219558B2 - 3dフラッシュ構造用のエッチングプロセス - Google Patents
3dフラッシュ構造用のエッチングプロセス Download PDFInfo
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- JP6219558B2 JP6219558B2 JP2012194636A JP2012194636A JP6219558B2 JP 6219558 B2 JP6219558 B2 JP 6219558B2 JP 2012194636 A JP2012194636 A JP 2012194636A JP 2012194636 A JP2012194636 A JP 2012194636A JP 6219558 B2 JP6219558 B2 JP 6219558B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
- H01J37/32082—Radio frequency generated discharge
- H01J37/321—Radio frequency generated discharge the radio frequency energy being inductively coupled to the plasma
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/32798—Further details of plasma apparatus not provided for in groups H01J37/3244 - H01J37/32788; special provisions for cleaning or maintenance of the apparatus
- H01J37/32816—Pressure
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
- H01L21/30612—Etching of AIIIBV compounds
- H01L21/30621—Vapour phase etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
- H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/10—Integrated device layouts
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
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- Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Plasma & Fusion (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Analytical Chemistry (AREA)
- Inorganic Chemistry (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/226,087 | 2011-09-06 | ||
| US13/226,087 US8598040B2 (en) | 2011-09-06 | 2011-09-06 | ETCH process for 3D flash structures |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2013080909A JP2013080909A (ja) | 2013-05-02 |
| JP2013080909A5 JP2013080909A5 (enExample) | 2015-11-19 |
| JP6219558B2 true JP6219558B2 (ja) | 2017-10-25 |
Family
ID=47753488
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2012194636A Active JP6219558B2 (ja) | 2011-09-06 | 2012-09-05 | 3dフラッシュ構造用のエッチングプロセス |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US8598040B2 (enExample) |
| JP (1) | JP6219558B2 (enExample) |
| KR (1) | KR101979957B1 (enExample) |
| CN (1) | CN102983052B (enExample) |
| SG (1) | SG188723A1 (enExample) |
| TW (1) | TWI559393B (enExample) |
Families Citing this family (46)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102034556B1 (ko) * | 2012-02-09 | 2019-10-21 | 도쿄엘렉트론가부시키가이샤 | 플라즈마 처리 방법 |
| US9299574B2 (en) * | 2013-01-25 | 2016-03-29 | Applied Materials, Inc. | Silicon dioxide-polysilicon multi-layered stack etching with plasma etch chamber employing non-corrosive etchants |
| US9129911B2 (en) | 2013-01-31 | 2015-09-08 | Applied Materials, Inc. | Boron-doped carbon-based hardmask etch processing |
| US20140342570A1 (en) * | 2013-05-16 | 2014-11-20 | Applied Materials, Inc. | Etch process having adaptive control with etch depth of pressure and power |
| JP6211947B2 (ja) | 2013-07-31 | 2017-10-11 | 東京エレクトロン株式会社 | 半導体装置の製造方法 |
| JP6140575B2 (ja) * | 2013-08-26 | 2017-05-31 | 東京エレクトロン株式会社 | 半導体装置の製造方法 |
| US9018103B2 (en) * | 2013-09-26 | 2015-04-28 | Lam Research Corporation | High aspect ratio etch with combination mask |
| JP6267953B2 (ja) | 2013-12-19 | 2018-01-24 | 東京エレクトロン株式会社 | 半導体装置の製造方法 |
| CN104793289B (zh) * | 2014-01-21 | 2019-05-10 | 吉林师范大学 | 有机聚合物等离子刻蚀工艺误差对器件影响的补偿方法 |
| JP6277004B2 (ja) | 2014-01-31 | 2018-02-07 | 株式会社日立ハイテクノロジーズ | ドライエッチング方法 |
| JP6230930B2 (ja) * | 2014-02-17 | 2017-11-15 | 東京エレクトロン株式会社 | 半導体装置の製造方法 |
| JP6289996B2 (ja) * | 2014-05-14 | 2018-03-07 | 東京エレクトロン株式会社 | 被エッチング層をエッチングする方法 |
| CN105336570A (zh) * | 2014-07-14 | 2016-02-17 | 北京北方微电子基地设备工艺研究中心有限责任公司 | 基片刻蚀方法 |
| US20160020119A1 (en) * | 2014-07-16 | 2016-01-21 | Macronix International Co., Ltd. | Method of Controlling Recess Depth and Bottom ECD in Over-Etching |
| US9449821B2 (en) * | 2014-07-17 | 2016-09-20 | Macronix International Co., Ltd. | Composite hard mask etching profile for preventing pattern collapse in high-aspect-ratio trenches |
| JP6423643B2 (ja) * | 2014-08-08 | 2018-11-14 | 東京エレクトロン株式会社 | 多層膜をエッチングする方法 |
| JP6454492B2 (ja) * | 2014-08-08 | 2019-01-16 | 東京エレクトロン株式会社 | 多層膜をエッチングする方法 |
| CN105374737B (zh) * | 2014-08-25 | 2019-02-26 | 中微半导体设备(上海)有限公司 | 抑制刻蚀过程中孔底部出现缺口的方法、孔的形成方法 |
| JP6328524B2 (ja) * | 2014-08-29 | 2018-05-23 | 東京エレクトロン株式会社 | エッチング方法 |
| JP6339961B2 (ja) | 2015-03-31 | 2018-06-06 | 東京エレクトロン株式会社 | エッチング方法 |
| JP6339963B2 (ja) * | 2015-04-06 | 2018-06-06 | 東京エレクトロン株式会社 | エッチング方法 |
| JP6498022B2 (ja) * | 2015-04-22 | 2019-04-10 | 東京エレクトロン株式会社 | エッチング処理方法 |
| US9613824B2 (en) | 2015-05-14 | 2017-04-04 | Tokyo Electron Limited | Etching method |
| JP6494424B2 (ja) * | 2015-05-29 | 2019-04-03 | 東京エレクトロン株式会社 | エッチング方法 |
| JP6541439B2 (ja) * | 2015-05-29 | 2019-07-10 | 東京エレクトロン株式会社 | エッチング方法 |
| KR20170002764A (ko) | 2015-06-29 | 2017-01-09 | 삼성전자주식회사 | 반도체 소자의 제조 방법 |
| US9613979B2 (en) | 2015-07-16 | 2017-04-04 | Kabushiki Kaisha Toshiba | Semiconductor memory device and method of manufacturing the same |
| JP6557588B2 (ja) * | 2015-12-04 | 2019-08-07 | 株式会社日立ハイテクノロジーズ | ドライエッチング方法 |
| US9997374B2 (en) * | 2015-12-18 | 2018-06-12 | Tokyo Electron Limited | Etching method |
| GB201608926D0 (en) * | 2016-05-20 | 2016-07-06 | Spts Technologies Ltd | Method for plasma etching a workpiece |
| JP6604911B2 (ja) * | 2016-06-23 | 2019-11-13 | 東京エレクトロン株式会社 | エッチング処理方法 |
| US9997366B2 (en) * | 2016-10-19 | 2018-06-12 | Lam Research Corporation | Silicon oxide silicon nitride stack ion-assisted etch |
| JP6945388B2 (ja) | 2017-08-23 | 2021-10-06 | 東京エレクトロン株式会社 | エッチング方法及びエッチング処理装置 |
| JP6883495B2 (ja) | 2017-09-04 | 2021-06-09 | 東京エレクトロン株式会社 | エッチング方法 |
| US10002746B1 (en) * | 2017-09-13 | 2018-06-19 | Lam Research Corporation | Multi regime plasma wafer processing to increase directionality of ions |
| US10847374B2 (en) * | 2017-10-31 | 2020-11-24 | Lam Research Corporation | Method for etching features in a stack |
| JP2019096666A (ja) * | 2017-11-20 | 2019-06-20 | 東京エレクトロン株式会社 | エッチング方法及びこれを用いた窪みパターンの埋め込み方法 |
| KR102762670B1 (ko) * | 2017-11-30 | 2025-02-04 | 램 리써치 코포레이션 | 실리콘 옥사이드 실리콘 나이트라이드 스택 계단 단차 (stair step) 에칭 |
| US11702751B2 (en) | 2019-08-15 | 2023-07-18 | Applied Materials, Inc. | Non-conformal high selectivity film for etch critical dimension control |
| JP7403314B2 (ja) * | 2019-12-26 | 2023-12-22 | 東京エレクトロン株式会社 | エッチング方法及びエッチング装置 |
| CN111154490A (zh) * | 2020-01-02 | 2020-05-15 | 长江存储科技有限责任公司 | 刻蚀气体、刻蚀方法及3d存储器件制造方法 |
| JP7639013B2 (ja) * | 2020-02-13 | 2025-03-04 | ラム リサーチ コーポレーション | 無限選択性を有する高アスペクト比エッチング |
| JP2023514831A (ja) | 2020-02-19 | 2023-04-11 | ラム リサーチ コーポレーション | グラフェン集積化 |
| US11688609B2 (en) * | 2020-05-29 | 2023-06-27 | Tokyo Electron Limited | Etching method and plasma processing apparatus |
| JP7675033B2 (ja) | 2022-01-27 | 2025-05-12 | 東京エレクトロン株式会社 | エッチング方法及びプラズマ処理装置 |
| JP7641923B2 (ja) | 2022-01-27 | 2025-03-07 | 東京エレクトロン株式会社 | エッチング方法及びプラズマ処理装置 |
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| WO1999016125A1 (de) * | 1997-09-24 | 1999-04-01 | Infineon Technologies Ag | Verfahren zur ausbildung einer grabenstruktur in einem siliziumsubstrat |
| US6312616B1 (en) * | 1998-12-03 | 2001-11-06 | Applied Materials, Inc. | Plasma etching of polysilicon using fluorinated gas mixtures |
| US6303513B1 (en) * | 1999-06-07 | 2001-10-16 | Applied Materials, Inc. | Method for controlling a profile of a structure formed on a substrate |
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- 2012-09-05 KR KR1020120098350A patent/KR101979957B1/ko active Active
- 2012-09-05 TW TW101132348A patent/TWI559393B/zh active
- 2012-09-05 JP JP2012194636A patent/JP6219558B2/ja active Active
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|---|---|
| TWI559393B (zh) | 2016-11-21 |
| US20130059450A1 (en) | 2013-03-07 |
| JP2013080909A (ja) | 2013-05-02 |
| US8598040B2 (en) | 2013-12-03 |
| KR101979957B1 (ko) | 2019-05-17 |
| KR20130026996A (ko) | 2013-03-14 |
| CN102983052B (zh) | 2015-09-02 |
| CN102983052A (zh) | 2013-03-20 |
| SG188723A1 (en) | 2013-04-30 |
| TW201330088A (zh) | 2013-07-16 |
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