JP6159563B2 - 少なくとも1つのパワー半導体コンポーネント用の基板を製造するための方法 - Google Patents
少なくとも1つのパワー半導体コンポーネント用の基板を製造するための方法 Download PDFInfo
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- JP6159563B2 JP6159563B2 JP2013088232A JP2013088232A JP6159563B2 JP 6159563 B2 JP6159563 B2 JP 6159563B2 JP 2013088232 A JP2013088232 A JP 2013088232A JP 2013088232 A JP2013088232 A JP 2013088232A JP 6159563 B2 JP6159563 B2 JP 6159563B2
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
- H01L23/49844—Geometry or layout for devices being provided for in H01L29/00
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- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Geometry (AREA)
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- Manufacturing Of Printed Wiring (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102012206758.2 | 2012-04-25 | ||
DE102012206758A DE102012206758B3 (de) | 2012-04-25 | 2012-04-25 | Verfahren zur Herstellung eines Substrats und ein Leistungshalbleitermodul mit einem Substrat für mindestens ein Leitungshalbleiterbauelement |
Publications (2)
Publication Number | Publication Date |
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JP2013229603A JP2013229603A (ja) | 2013-11-07 |
JP6159563B2 true JP6159563B2 (ja) | 2017-07-05 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2013088232A Expired - Fee Related JP6159563B2 (ja) | 2012-04-25 | 2013-04-19 | 少なくとも1つのパワー半導体コンポーネント用の基板を製造するための方法 |
Country Status (4)
Country | Link |
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JP (1) | JP6159563B2 (de) |
KR (1) | KR20130120385A (de) |
CN (1) | CN103377950B (de) |
DE (1) | DE102012206758B3 (de) |
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US9397017B2 (en) * | 2014-11-06 | 2016-07-19 | Semiconductor Components Industries, Llc | Substrate structures and methods of manufacture |
US11437304B2 (en) | 2014-11-06 | 2022-09-06 | Semiconductor Components Industries, Llc | Substrate structures and methods of manufacture |
US9408301B2 (en) | 2014-11-06 | 2016-08-02 | Semiconductor Components Industries, Llc | Substrate structures and methods of manufacture |
WO2023234590A1 (ko) * | 2022-05-31 | 2023-12-07 | 주식회사 아모그린텍 | 세라믹 기판 및 그 제조방법 |
KR20230173334A (ko) * | 2022-06-17 | 2023-12-27 | 주식회사 아모그린텍 | 세라믹 기판 및 그 제조방법 |
DE102022206295B3 (de) | 2022-06-23 | 2023-11-09 | Zf Friedrichshafen Ag | Verfahren zum bilden eines halbleitermoduls und halbleitermodul |
KR20240020380A (ko) * | 2022-08-08 | 2024-02-15 | 주식회사 아모그린텍 | 세라믹 기판 및 그 제조방법 |
KR20240038268A (ko) * | 2022-09-16 | 2024-03-25 | 주식회사 아모그린텍 | 히트싱크 일체형 파워모듈용 기판 및 그 제조방법 |
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JP2664409B2 (ja) * | 1988-04-18 | 1997-10-15 | 三洋電機株式会社 | 混成集積回路の製造方法 |
US5160578A (en) * | 1990-04-23 | 1992-11-03 | Phillips Petroleum Company | Separating of fibers from a fiber-containing solid sample |
US5160579A (en) * | 1991-06-05 | 1992-11-03 | Macdermid, Incorporated | Process for manufacturing printed circuit employing selective provision of solderable coating |
US5928768A (en) * | 1995-03-20 | 1999-07-27 | Kabushiki Kaisha Toshiba | Silicon nitride circuit board |
CA2255441C (en) * | 1997-12-08 | 2003-08-05 | Hiroki Sekiya | Package for semiconductor power device and method for assembling the same |
EP1187521A1 (de) * | 2000-09-09 | 2002-03-13 | AB Mikroelektronik Gesellschaft m.b.H. | Verfahren zur Herstellung einer Trägerplatte für elektronische Bauteile |
US6319750B1 (en) * | 2000-11-14 | 2001-11-20 | Siliconware Precision Industries Co., Ltd. | Layout method for thin and fine ball grid array package substrate with plating bus |
DE10154316A1 (de) * | 2001-11-07 | 2003-05-15 | Juergen Schulz-Harder | Verfahren zur selektiven Oberflächenbehandlung von plattenförmigen Werkstücken |
JP4765110B2 (ja) * | 2005-03-31 | 2011-09-07 | Dowaメタルテック株式会社 | 金属−セラミックス接合基板およびその製造方法 |
JP2006310796A (ja) * | 2005-04-01 | 2006-11-09 | Ngk Spark Plug Co Ltd | 多数個取り用配線基板 |
CN100588308C (zh) * | 2007-01-24 | 2010-02-03 | 南京汉德森科技股份有限公司 | 高热导率陶瓷基印刷电路板及其制作方法 |
US7838978B2 (en) * | 2007-09-19 | 2010-11-23 | Infineon Technologies Ag | Semiconductor device |
CN101754584B (zh) * | 2008-12-12 | 2012-01-25 | 清华大学 | 制备导电线路的方法 |
CN101593655B (zh) * | 2009-07-17 | 2011-11-23 | 威海新佳电子有限公司 | 一种pdp功率集成模块及其制作方法 |
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