JP6159563B2 - Method for manufacturing a substrate for at least one power semiconductor component - Google Patents

Description

The present invention relates to a method for manufacturing a substrate for at least one power semiconductor component .

  For example, power semiconductor components such as IGBTs (Insulated Gate Bipolar Transistors), MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), thyristors, or diodes are specifically used to rectify and invert voltages and currents, for example. In general, a plurality of power semiconductor components, for example to realize a converter, are electrically connected to each other. In this case, the power semiconductor component is typically placed on a substrate, which is typically connected directly or indirectly to a heat sink.

  The power semiconductor component is usually placed on and connected to a substrate for the purpose of manufacturing a power semiconductor module. In this case, the substrate can be present, for example, in the form of a DCB substrate. In this case, the substrate has a structured conductive metal layer, which forms a conductor track because of its structure. The power semiconductor components are connected to one another via conductor tracks such that a load current having a high current strength flows through the power semiconductor components and also through the conductor tracks of the conductive metal layer.

  In order to produce a DCB substrate, joining a metal plate of uniform thickness onto an insulating material body, usually made of ceramic, and subsequently etching the conductor track structure from the metal plate is known in the art. It is a traditional practice. Since the load current must flow through the conductor track, the conductor track must have a high current capacity, so the metal plate must be thick and the conductor track must be even wider. . In this case, the load current flows from, for example, the power semiconductor module to a load such as an electric motor connected to the power semiconductor module.

  In practice, integrated circuits that can exist, for example, in the form of microchips, are used today, for example, to realize drive electronics for driving power semiconductor components. Because of their small dimensions, integrated circuits require narrow conductor tracks that can connect them. In this case, in general, only a current having a low current intensity flows through the conductor track for the integrated circuit, so that the conductor track for the integrated circuit is narrow and can be manufactured with a small thickness.

  However, for example, due to the relatively large thickness of the metal plate in a conventional DCB substrate in the art, it is not possible to produce narrow conductor tracks as required for integrated circuits by corresponding microstructuring of the metal plate. Impossible. Because, due to the relatively large thickness of the metal plate required to achieve the required current capacity for the load current of the power semiconductor, the acid also becomes conductive during the etching of narrow conductor tracks for integrated circuits. This is because the material is etched laterally under the coating resist covering the intended location for the track to occur, thus destroying the narrow conductor track.

  Therefore, the prior art usually provides a circuit board that is separate from the substrate on which the power semiconductor component is disposed, for example, an integrated circuit for realizing drive electronics for driving the power semiconductor component is disposed on the circuit board. Is done. This has the disadvantage that a conductive connection (eg wire connection) must be provided between the substrate and the circuit board, which includes a corresponding substrate with power semiconductor components, and an integrated circuit It adversely affects the reliability of the power semiconductor module including the corresponding circuit board and complicates the manufacture of the power semiconductor module.

  It is an object of the present invention to provide a substrate having at least one conductor track capable of transmitting a load current and a conductor track capable of connection to an integrated circuit.

The object is a method for manufacturing a substrate for at least one power semiconductor component comprising the following method steps:
a) providing a non-conductive insulating material body;
b) Structured conductive having a first region (22a) having a narrow conductor track (21) and a second region (22b) having at least one wide conductor track (20a, 20b). Applying a first metallization layer (2a) on the first side (15a) of the insulating material body (1);
c) electrolytically depositing a first metal layer on at least one broad conductor track;
Achieved by a method comprising:

  Furthermore, the object is a substrate for at least one power semiconductor component, wherein the substrate is a non-conductive insulating material body and a structured second body disposed on a first side of the insulating material body. One metallization layer, the first metallization layer has first and second regions, the first region has narrow conductor tracks, and the second region is at least 1 The first metal layer is achieved by a substrate having two wide conductor tracks and disposed on at least one wide conductor track.

  The present invention allows the use of a common substrate for at least one power semiconductor component and at least one integrated circuit. Thus, with the present invention, it is no longer necessary to provide a separate circuit board for at least one integrated circuit. Therefore, the manufacture of the power semiconductor module is simplified by the present invention, and at the same time the reliability of the power semiconductor module is improved.

  Advantageous embodiments of the method occur in the same way as advantageous embodiments of the substrate and vice versa.

  Advantageous embodiments of the invention result from the dependent claims.

Between method steps b) and c),
A non-conductive resist layer is applied to the narrow conductor tracks and after method step c)
It can be seen that it is advantageous if the non-conductive resist layer is removed.

  By applying a non-conductive resist layer to narrow conductor tracks, it is possible in a simple manner to prevent electrolytic deposition of the first metal layer on the narrow conductor tracks.

The following subsequent method steps:
It can be seen that it is advantageous if the step of electrolytically depositing a second metal layer on the narrow conductor track and / or the first metal layer is carried out.

  The second metal layer preferably serves as a protective layer for the first metal layer and / or as an adhesive connection layer for tight connection such as, for example, sintering or soldering connection.

  It can be seen that it is advantageous if at least one wide conductor track has a width of at least 3000 μm. This is because the current capacity of the conductor track increases as the width of at least one wide conductor track increases.

  Furthermore, it can be seen that it is advantageous if the narrow conductor track has a width of 100 μm to 1000 μm. This is because in that case all commonly used integrated circuits can be connected to narrow conductor tracks.

  Furthermore, it can be seen that it is advantageous if the first metallization layer has a thickness of 1 μm to 30 μm. This is because in that case the excellent mechanical stability of the first metallization layer is guaranteed.

  Furthermore, it can be seen that it is advantageous if the first metallization layer comprises silver and / or copper. This is because it achieves high electrical and thermal conductivity of the first metallization layer.

  Furthermore, it can be seen that it is advantageous if the first metal layer has a thickness of 100 μm to 500 μm. This is because a high current capacity can be obtained in that case.

Furthermore, method step c)
-Applying a second metallization layer to the second side of the insulating material body, further comprising the second side being disposed on the opposite side of the first side of the insulating material body;
Method step d)
It proves advantageous if it further comprises electrolytically depositing a third metal layer on the second metallization layer.

  The third metal layer preferably serves to connect the substrate to a plate or heat sink.

  Furthermore, the first metallization layer has a connection conductor track, the second region has at least one first and one second wide conductor track, and the connection conductor track has a first metal. Connected to a first wide conductor track through a first number of conductive first connecting webs formed from the metallization layer, the first wide conductor track formed from the first metallization layer Connected to a second wide conductor track via a second number of conductive second connecting webs, wherein each number of connecting webs and / or each width of the connecting webs has a respective wide width. It can be seen that it is advantageous if it depends on the distance between the conductor track and the connecting conductor track and increases as the distance increases. This measure ensures a substantially uniform thickness of the first metal layer on the first and second wide conductor tracks.

  Further, the first metallization layer has connecting conductor tracks, the second region has at least one first and one second wide conductor track, and the connecting conductor tracks have first and second connections. At approximately the same distance from the two wide conductor tracks, the connecting track being connected to the first wide conductor track via the first connecting web formed from the first metallization layer, and the first It can be seen that it is advantageous when connected to a second wide conductor track via a second connecting web formed from a metallization layer. This measure ensures a substantially uniform thickness of the first metal layer on the first and second wide conductor tracks.

  Furthermore, it turns out that it is advantageous when the first metal layer is made of copper. This is because copper has a high electrical conductivity.

  Furthermore, the method connects at least one power semiconductor component to the first metal layer or on the first metal layer when the second metal layer is disposed on the first metal layer. Connecting to a disposed second metal layer, and connecting at least one integrated circuit to a narrow conductor track, or narrow conductor track when the second metal layer is disposed on a narrow conductor track And connecting to a second metal layer disposed thereon is advantageous. This is because the power semiconductor module can be manufactured by a simple method in this way.

  Furthermore, it can be seen that it is advantageous if the respective connection process is achieved by adhesion, in particular by sintering or soldering connections. This is because tight connections, such as, for example, sintering or soldering connections, constitute conventional connections in the case of power semiconductor modules.

  Further, when at least one power semiconductor component is disposed on the substrate and conductively connected to the first metal layer, and at least one integrated circuit is disposed on the substrate and conductively connected to the narrow conductor track. It turns out to be advantageous. This results in a particularly reliable power semiconductor module.

  Illustrative embodiments of the invention are shown in the drawings and are described in more detail below.

Fig. 2 shows a substrate blank in the form of a schematic cross section after the method steps according to the invention have been carried out. The substrate blank is shown in schematic cross-section after further method steps have been performed. The substrate blank is shown in schematic cross-section after further method steps have been performed. Fig. 3 shows in schematic cross-section a substrate according to the invention after further method steps have been carried out. The substrate blank after the method steps according to the invention have been carried out is shown in schematic form from above the substrate blank. A further embodiment of the substrate blank after the method steps have been carried out is shown in schematic form from above the substrate blank. A further embodiment of the substrate blank after the method steps have been carried out is shown in schematic form from above the substrate blank. Fig. 2 shows a further embodiment of a substrate according to the invention in the form of a schematic cross section after further method steps have been carried out. 1 shows a power semiconductor module according to the invention in the form of a schematic sectional view. A further power semiconductor module according to the invention is shown in the form of a schematic sectional view.

  The first method step includes providing a non-conductive insulating material body 1. FIG. 1 shows the substrate blank 7a in the form of a schematic cross-section after further method steps according to the invention have been carried out. FIG. 5 shows a schematic diagram related to FIG. 1 from above the substrate blank 7a. The method steps include applying a structured conductive first metallization layer 2a on the first side surface 15a of the insulating material body 1, wherein the first metallization layer 2a comprises a first metallization layer 2a. And the second region, the first region 22a has a narrow conductor track 21 and the second region 22b has at least one wide conductor track. In the context of the exemplary embodiment, the second region 22b has a first broad conductor track 20a and a second broad conductor track 20b. Only one narrow conductor track is provided with reference numerals in FIGS. 1 and 5 for clarity. Narrow conductor tracks are shown only in the illustration of FIG. 5, but of course that it is possible to proceed out of the first region 22a, for example into the second region 22b. Please note that. Furthermore, it should be noted at this point that a wide conductor track is likewise shown only in the illustration of FIG. 5, but of course can proceed out of the second region 22b.

  The wide conductor tracks preferably have a width b of at least 3000 μm, in particular a width of at least 4000 μm. The narrow conductor track preferably has a width of 100 μm to 1000 μm, in particular 100 μm to 300 μm.

In the context of the exemplary embodiment, this method step also includes applying a second metallization layer 2b to the second side 15b of the insulating material body 1 by electrolysis, said second side Is disposed on the opposite side of the first side surface 15 a of the insulating material body 1. Thus, the insulating material body 1 is disposed between the first and second metallized layers 2a and 2b. The insulating material body 1 can be made of ceramic such as Al ₂ O ₃ or AlN, for example, and preferably has a thickness of 300 μm to 1000 μm. The metallization layers 2a and 2b can consist essentially of, for example, copper and / or silver, or copper alloys and / or silver alloys. The first metallization layer 2a has a structure embodied according to the intended course of narrow conductor tracks and wide conductor tracks. Thus, in the context of the exemplary embodiment, the first metallization layer 2a has, for example, interruptions 4 and 4 ′ that delimit the conductor tracks from each other. The second metallization layer 2b is preferably not structured, but can also be embodied in a structured manner as well.

  The first and second metallization layers 2a and 2b preferably have a thickness of 1 μm to 30 μm, but the first and second metallization layers 2a and 2b can have different thicknesses.

  The process of applying the first and second metallization layers to the first and second sides of the insulating material body 1 is preferably accomplished by the following procedure. That is, first, a metallized paste containing copper and / or silver-containing particles and a solvent is applied to the first and second side surfaces 15a and 15b of the insulating material body 1 at a position where the metallized layer is intended to exist. Applied and then the metallized paste is dried, for example at 180 ° C. and then heated in a furnace, preferably in vacuum, preferably to about 1000 ° C. Is preferred.

  It should be noted at this point that FIGS. 1-10 are schematic and in particular that the layer thicknesses are not shown to scale.

  FIG. 2 shows the substrate blank 7a in the form of a schematic cross-section after further method steps have been performed which are performed in the context of the exemplary embodiment. The method steps include applying the non-conductive resist layer 3 to the narrow conductor track 21. The resist layer 3 preferably has a thickness of 5 μm to 300 μm.

  FIG. 3 shows the substrate blank 7a in the form of a schematic cross section after further method steps have been carried out. In the method step, the first metal layer 5 is electrodeposited on at least one wide conductor track, ie in the context of the exemplary embodiment, on the first and second wide conductor tracks 20a, 20b. It is included. Furthermore, in the context of the exemplary embodiment, a third metal layer 6 is electrodeposited on the second metallization layer 2b. For this purpose, the substrate blank 7a is immersed in a container filled with an electroplating solution, and the first and second metallized layers 2a and 2b are conductively connected to the cathode of the voltage source, and the electroplating solution The arranged electrode is conductively connected to the anode of the voltage source, current begins to flow, and the first metal layer 5 is deposited on the wide conductor tracks 20a, 20b, and the third metal layer 6 is It is made to deposit on the 2nd metallization layer 2b. The resist layer 3 prevents electrolytic deposition of the first metal layer on the narrow conductor track 21. Alternatively, the application of the resist layer 3 is omitted, and only a wide conductor track and, if present, an additional second metallization layer 2b is conductively connected to the cathode of the voltage source so that it is applied onto the narrow conductor track 21. It is also possible to prevent electrolytic deposition of the first metal layer. In this case, in the context of the exemplary embodiment, the electroplating solution contains copper ions so that the first and third metal layers 5 and 6 are made of copper in the exemplary embodiment.

  The first and third metal layers 5 and 6 preferably have a thickness of 100 μm to 500 μm. The thicknesses of the first and third metal layers 5 and 6 are not necessarily the same. In the exemplary embodiment, since the thickness of the third metal layer 6 is less than the thickness of the first metal layer 5, in the exemplary embodiment, during the electrolytic deposition, the third metal layer 6 is When the assumed thickness is achieved, the electrical connection of the second metallization layer 2b to the voltage source is interrupted and only the first metal layer 5 is assumed during further electrolytic deposition. Allow to grow until thickness is achieved.

  However, still other methods for achieving different deposition heights are also possible. Thus, for example, after the third metal layer 6 has achieved the assumed thickness, also interrupting electrolytic deposition, applying a non-conductive resist to the third metal layer 6, and then It is possible to continue the electrodeposition until the first metal layer 5 achieves the assumed height h, and the third metal layer 6 is due to the resist applied to the third metal layer 6. In this case, no further growth.

  The first metal layer 5 arranged on the wide conductor tracks 20a and 20b reinforces the conductor tracks 20a and 20b and thus can transmit the load current and accordingly the load current with high current strength can pass through. Bring conductor tracks. A conductor track capable of transmitting a load current is given reference numeral 25 in FIG. In this case, the conductor track 25 capable of transmitting the load current includes the conductor track 20a and the first metal layer 5 disposed on the conductor track 20a.

  During the electrolytic deposition of the first metal layer onto the broad conductor track, it is advantageous if the broad conductor tracks are connected to each other via the first metallization layer during the electrolytic deposition. This is because, in that case, during the electrolytic deposition, it is not necessary to conductively connect each wide conductor track to the cathode of the voltage source via wires respectively assigned to the wide conductor tracks.

  Therefore, preferably, as shown in FIG. 6, the first metallization layer 2a has a connection conductor track 8, and the connection conductor track 8 in FIG. 6 is formed from the first metallization layer 2a. Connected to a first wide conductor track 20a via a first number of conductive first connecting webs 9, the first wide conductor track 20a being formed from the first metallization layer 2a, Via a second number of conductive second connecting webs 9 ', it is connected to a second wide conductor track 20b, the respective number of connecting webs and / or the respective width c of connecting webs 9 being respectively Depending on the distance between the wide conductor tracks and the connecting conductor tracks 8 and increases as the distance a increases. In the exemplary embodiment, the first number is “1”, the second number is “2”, and all connecting webs 9 have a uniform width c.

  As an alternative to that, as shown in FIG. 7, it is possible for the connecting conductor track 8 to be at approximately the same distance a, in particular the same distance a, from the first and second wide conductor tracks 20a and 20b, The connection conductor track 8 is connected to the first wide conductor track 20a via the first connection web 9 formed from the first metallization layer 2a and formed from the first metallization layer 2a. It is connected to a second wide conductor track 20b via a second connection web 9 '. The first and second connecting webs 9 and 9 'have approximately the same length, in particular the same length.

  The advantageous embodiment of the invention shown in FIGS. 6 and 7 allows a substantially uniform thickness of the first metal layer 5 on the first and second broad conductor tracks 20a and 20b during the electrolytic deposition. become.

  The connecting conductor track and / or connecting web is coated with a non-conductive resist prior to the electrolytic deposition of the first metal layer, and the first metal layer is connected to the connecting conductor track and / or connecting web during the electrodeposition. It is preferable not to deposit on the top.

  The resist layer 3 applied to the narrow conductor tracks 21 in the context of the exemplary embodiment is removed again after the electrolytic deposition of the first metal layer in the exemplary embodiment. FIG. 4 shows the substrate 7 according to the invention after this step has been carried out.

  In the context of the exemplary embodiment, as shown subsequently in FIG. 8, the second metal layer 10 is on the narrow conductor track 21 and the first metal layer 5 and also on the third metal layer 6. Electrodeposited. The second metal layer 10 is preferably made of silver. The second metal layer 10 preferably serves as a protective layer for the first and third metal layers and also for the narrow conductor track 21 and / or as an adhesive connection layer for sintering or soldering connections. The second metal layer 10 preferably has a thickness of 0.1 μm to 10 μm. It should be particularly noted at this point that the second metal layer 10 does not necessarily have to be applied to the first metal layer 5, to the narrow conductor track 21 or to the third metal layer 6.

  Furthermore, when the second metal layer 10 is intended to be electrodeposited only on, for example, the narrow conductor track 21, the first and third metal layers 5 and 6 are the second metal layer 10. It should be noted at this point that the second metal layer 10 can be electrodeposited only on the narrow conductor tracks 21 by coating with an electrically insulating resist prior to the electrodeposition of the first electrode.

  Furthermore, when the second metal layer 10 is intended to be electrodeposited only on the first metal layer 5, for example, the narrow conductor tracks 21 and the third metal layer 6 Note that the second metal layer 10 can be electrodeposited only on the first metal layer 5 by coating with an electrically insulating resist prior to the electrodeposition of the layer 10.

  Elements that are not intended to be coated with the second metal layer 10 are in each case coated with an electrically insulating resist before the electrolytic deposition of the second metal layer 10.

  FIG. 8 shows the substrate 7 after electrolytic deposition of the second metal layer 10.

  Subsequently, the connecting web is preferably removed from the insulating material body 1, for example by mechanical removal of the connecting web. If the connection web was not coated with an electrically insulating resist prior to the electrolytic deposition of the first metal layer 5 and the deposition of the second metal layer 10 (which is done if necessary), the connection web is connected Including a first metal layer 5 disposed on the web, and optionally including a second metal layer 10 disposed on the first metal layer 5 of the connection web, for example of the connection web Removed by mechanical removal.

  In order to manufacture the power semiconductor module 26 according to the invention, subsequently, a further method step shown in FIG. 9 includes connecting at least one power semiconductor component to the first metal layer 5 or a second metal. If the layer 10 is arranged on the first metal layer 5 as in the exemplary embodiment according to FIG. 9, it connects to the second metal layer 10 arranged on the first metal layer 5. Step and connecting at least one integrated circuit 17 to a narrow conductor track or, if the second metal layer 10 is present on a narrow conductor track 21 as in the exemplary embodiment, the narrow conductor track Connecting to the second metal layer 10 disposed on 21. In the context of the exemplary embodiment, a first power semiconductor component 18 embodied as an IGBT as an example, and a second power semiconductor component 19 embodied as a diode as an example are in the second metal layer 10. Connected. In this case, the connection of at least one power semiconductor component is achieved in the first partial method step, and the connection of the integrated circuit 17 is achieved in the second partial method step. In this case, the first partial method step can be achieved before the second partial method step, simultaneously with the second partial method step, or after the second partial method step.

  In the context of the exemplary embodiment, in this case according to FIG. 9, a first power semiconductor component 18 and a second power semiconductor component 19 together with a second metal layer 10 disposed on the first metal layer 5. Are connected to each other by a sintered or soldered connection such that the sintered or soldered layer 14 is disposed between the power semiconductor components 18 and 19 and the first metal layer 5. Further, in the context of the exemplary embodiment, the integrated circuit 17 together with the second metal layer 10 disposed on the narrow conductor track has a sintered or soldered layer 14 ′ that is integrated with the integrated circuit 17 and the second metal layer 10. Are connected to each other via connection pins 16 by sintering or soldering connections. In this case, each sintered layer is preferably at least substantially composed of silver, and each soldering layer is preferably at least substantially composed of tin.

  FIG. 10 illustrates a further exemplary embodiment of the present invention. This embodiment substantially corresponds to the exemplary embodiment of the present invention according to FIG. 9, but in contrast to the exemplary embodiment according to FIG. 9, in the exemplary embodiment according to FIG. The layer 5 is not coated with the second metal layer 10 and the first power semiconductor component 18 and the second power semiconductor component 19 are connected to the first metal layer 5, for example by sintering or soldering. Like that.

  In the exemplary embodiment according to FIGS. 9 and 10, the power semiconductor components 18 and 19 are disposed on the substrate 7 and conductively connected to the first metal layer 5, and the integrated circuit 17 is disposed on the substrate 7. And conductively connected to the conductor track 21. In this case, the respective conductive connection is via the sintered or soldering layer 14 and, if present, via the second metal layer 10 and at least one further metal layer is the second metal. If it is possibly further arranged on the layer 10, it is further achieved via the at least one further metal layer.

  As mentioned above, at least one further metal layer can be further arranged on the second metal layer 10, in this case within the spirit of the invention at least one power semiconductor component and / or at least one integration. It should be understood that connecting the circuit to at least one further metal layer means connecting at least one power semiconductor component and / or at least one integrated circuit to the second metal layer. Please note that at the time.

  Furthermore, in particular in the case of a sintered connection, as part of the process of connecting the two elements to be connected to each other, the two elements to be connected can be provided with respective adhesive connection layers. The adhesive connection layer can, for example, consist at least substantially of silver on the sides of the elements intended to be connected to each other. It should be noted at this point that in this case each element to be connected does not necessarily have to be provided with an adhesive connection layer by electrolytic deposition.

  It should be noted at this point that identical elements in the figures have been given the same reference numerals.

DESCRIPTION OF SYMBOLS 1 Nonelectroconductive insulating material body 2a 1st metallization layer 2b 2nd metallization layer 3 Nonelectroconductive resist layer 4, 4 'Interrupting part 5 1st metal layer 6 3rd metal layer 7 Substrate 7a Substrate blank DESCRIPTION OF SYMBOLS 8 Connection conductor track 9 1st connection web 9 '2nd connection web 10 2nd metal layer 14, 14' Sintering or soldering layer 15a 1st side surface 15b 2nd side surface 16 Connection pin 17 Integrated circuit 18 1st power semiconductor component 19 2nd power semiconductor component 20a 1st wide conductor track 20b 2nd wide conductor track 21 narrow conductor track 22a first area 22b second area 25 conductor track 26 power semiconductor module a distance b, b 'width c width

Claims (14)

A method for manufacturing a substrate (7) for at least one power semiconductor component (18, 19) comprising the following method steps:
a) providing a non-conductive insulating material body (1) made of ceramic ;
b) Structured conductive having a first region (22a) having a narrow conductor track (21) and a second region (22b) having at least one wide conductor track (20a, 20b). Applying a first metallization layer (2a) on the first side (15a) of the insulating material body (1);
c) electrolytically depositing a first metal layer (5) on said at least one wide conductor track (20a, 20b);
A method configured with. Between method step b) and method step c),
After applying a non-conductive resist layer (3) to the narrow conductor track (21) and after method step c)
-Removing said non-conductive resist layer (3);
The method of claim 1, wherein: The following method steps:
Method according to claim 1 or 2, comprising the step of electrolytically depositing a second metal layer (10) on the narrow conductor track (21) and / or the first metal layer (5).   4. A method according to any one of the preceding claims, characterized in that the at least one wide conductor track (20a) has a width (b) of at least 3000 [mu] m.   5. The method according to claim 1, characterized in that the narrow conductor track (21) has a width (b ′) of 100 μm to 1000 μm. 6. The method according to any one of claims 1 to 5, characterized in that the first metallization layer ( 2a ) has a thickness of 1 [mu] m to 30 [mu] m. The method according to any one of claims 1 to 6, characterized in that the first metallization layer ( 2a ) comprises silver and / or copper.   8. A method according to any one of the preceding claims, characterized in that the first metal layer (5) has a thickness of 100 [mu] m to 500 [mu] m. Method step b) additionally
- the insulating material body (1) second metallization layer to the second side (15b) of which is disposed opposite said first side of said insulating material body (1) (15a) with (2b) Including applying,
Method step c) additionally comprises:
Method according to any one of claims 1 to 8, characterized in that it comprises electrolytically depositing a third metal layer (6) on the second metallization layer (2b).   The first metallization layer (2a) has connecting conductor tracks (8) and the second region (22b) has at least one first and one second wide conductor track (20a, 20b). The connecting conductor track (8) through a first number of conductive first connecting webs (9) formed from the first metallization layer (2a). Of the conductive second connecting web (9 ') formed from the first metallization layer (2a). Connected to the second wide conductor track (20b) via a second number, each number of the connecting webs (9, 9 ') and / or each of the connecting webs (9, 9') The width (c) is greater than the respective wide conductor track (20a 20b) depending on the distance (a) between the connecting conductor track (8) and increasing as the distance (a) increases. The method described in 1. The first metallization layer (2a) has connecting conductor tracks (8) and the second region (22b) has at least one first and one second wide conductor track (20a, 20b). The connecting conductor track (8) is at substantially the same distance (a) from the first and second wide conductor tracks (20a, 20b), and the connecting conductor track (8) Connected to the first wide conductor track (20a) via a first connection web (9) formed from one metallization layer (2a) and from the first metallization layer (2a) 10. Method according to any one of the preceding claims, characterized in that it is connected to the second broad conductor track (20b) via a formed second connecting web (9 '). .   12. A method according to any one of the preceding claims, characterized in that the first metal layer (5) consists of copper. A method for manufacturing a power semiconductor module (26), for manufacturing a substrate (7) for at least one power semiconductor component (18, 19) according to any one of the preceding claims. The following additional method steps including:
e) connecting the at least one power semiconductor component (18, 19) to the first metal layer (5) or a second metal layer (10) on the first metal layer (5); Is connected to the second metal layer (10) disposed on the first metal layer (5), and at least one integrated circuit (17) is connected to the narrow conductor track (21). ) Or when the second metal layer (10) is disposed on the narrow conductor track (21), the second metal layer (10) disposed on the narrow conductor track (21). And connecting to the method. The method for manufacturing a power semiconductor module according to claim 13, wherein each connecting step is achieved by close contact, in particular by sintering or soldering connections.

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