CN103377950A - Substrate and method of producing substrate for at least one power semiconductor component - Google Patents

Substrate and method of producing substrate for at least one power semiconductor component Download PDF

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Publication number
CN103377950A
CN103377950A CN2013101484337A CN201310148433A CN103377950A CN 103377950 A CN103377950 A CN 103377950A CN 2013101484337 A CN2013101484337 A CN 2013101484337A CN 201310148433 A CN201310148433 A CN 201310148433A CN 103377950 A CN103377950 A CN 103377950A
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Prior art keywords
conductor tracks
metal layer
substrate
power semiconductor
wide
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CN2013101484337A
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CN103377950B (en
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库尔特-格奥尔格·贝森德费
海科·布拉姆尔
娜蒂娅·埃德纳
克里斯蒂安·约布尔
哈拉尔德·科波拉
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Semikron GmbH and Co KG
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Semikron GmbH and Co KG
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  • Ceramic Engineering (AREA)
  • Structure Of Printed Boards (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

The invention relates to a substrate and a method of producing a substrate for at least one power semiconductor component. The method involves the steps of a) providing electrically non-conductive insulating portion (1); b) applying a patterned electrically conductive first metallization layer (2a) on a first side (15a) of the non-conductive insulating portion (1), wherein the first metallization layer comprises a first and second regions (22a, 22b); the first region (22a) is provided with narrow conductive tracks (21) and the second region (22b) is provided with at least one wide conductive track (20a, 20b); and c) electrodepositing a first metal layer (5) on the at least one wide conductive track (20a, 20b). The invention also provides a substrate (7). The substrate is provided with at least one conductor track (25) capable of bearing the load current; and a conductor track (21) capable of being connected with an integrated circuit.

Description

Substrate and for the manufacture of the method for the substrate of at least one power semiconductor
Technical field
The present invention relates to a kind of method and a kind of therewith relevant substrate of the substrate for the manufacture of at least one power semiconductor.In addition, the present invention relates to a kind of therewith relevant substrate.
Background technology
Power semiconductor, for example as IGBT(Insulated Gate Bipolar Transistor, insulated gate bipolar transistor), MOSFETs(Metal Oxide Semiconductor Field Effect Transistor, mos field effect transistor), thyristor or diode, especially also for example be used for voltage and current is carried out rectification and inversion, wherein, generally a plurality of power semiconductors are electrically connected to each other, for example are used for realizing current transformer.At this, power semiconductor generally is arranged in the substrate, and this substrate is general direct or indirectly be connected with cooling body.
Power semiconductor is arranged in the substrate in order to make power semiconductor modular usually, and is connected with substrate.At this, substrate can exist with the form of DCB substrate.At this, substrate has the metal level of structurized conduction, and this metal level has conductor tracks owing to its structure consists of.Power semiconductor is connected to each other by conductor tracks, thereby so that flow through the conductor tracks that the load current of this power semiconductor also flows through conductive metal layer, wherein, load current has very high current strength.
In order to make the DCB substrate, the sheet metal that usually will unify technically thickness is bonded on the insulating material body, and this insulating material body is comprised of pottery usually, and and then etches conductor track structure from metallic plate.Because load current must flow through the conductor tracks with very high current capacity, so sheet metal must be very thick and additionally conductor tracks must be very wide.At this, load current for example flow to the load that is connected with power semiconductor modular from power semiconductor modular, as for example motor.
Especially for example use now following integrated circuit in order to realize be used to the electronic device of controlling of controlling power semiconductor, this integrated circuit for example can exist with the form of microchip.Integrated circuit needs very narrow conductor tracks owing to its specification is very little, integrated circuit can be connected with this very narrow conductor tracks.At this, generally have the electric current of very little current strength only and flow through conductor tracks for integrated circuit, thereby the conductor tracks that is used for integrated circuit may be embodied to very narrow and has very little thickness.
But, because the relatively large thickness of sheet metal, for example can not produce image set by the corresponding meticulous structuring of sheet metal in the technically common DSB substrate and become the required such very narrow conductor tracks of circuit, this is (this thickness need in order to realize for the needed current capacity of the load current of power semiconductor) because because the relatively large thickness of sheet metal, when etching was used for the very narrow conductor tracks of integrated circuit, therefore the material (this coating varnish is covered with the position that form conductor tracks) that acid also can etching coating varnish downside also damaged very narrow conductor tracks.
Therefore, in the prior art, the circuit board that separates with the substrate that is furnished with power semiconductor on it is arranged on the integrated circuit that for example is used for realizing controlling electronic device usually, and this is controlled electronic device and is used for controlling power semiconductor.This has following shortcoming, namely, conduction must be set between substrate and circuit board be connected (for example lead-in wire connection), this reliability to following power semiconductor modular has a negative impact, this power semiconductor modular has with the respective substrates of power semiconductor with the related circuit plate of integrated circuit, and so that the manufacturing cost of power semiconductor modular is high.
Summary of the invention
Task of the present invention is, a kind of substrate is provided, and this substrate not only has the conductor tracks of at least one energy carry load electric current but also has the conductor tracks that can be connected with integrated circuit.
This task solves by a kind of method of the substrate for the manufacture of at least one power semiconductor, and the method has following method step:
A) provide nonconducting insulating material body;
B) the first metal layer of structurized conduction is executed cloth on the first side of insulating material body, wherein, the first metal layer has the first and second zones, and wherein, the first area has narrow conductor tracks, and second area has at least one wide conductor tracks; And
C) at least one wide conductor tracks substrates the first metal layer.
In addition, this task solves by the substrate that is used at least one power semiconductor, wherein, substrate has nonconducting insulating material body and is arranged on the first side of this insulating material body, structurized the first metal layer, wherein, the first metal layer has the first and second zones, wherein, the first area has narrow conductor tracks, and second area has at least one wide conductor tracks, wherein, be furnished with the first metal layer at least one wide conductor tracks.
By the present invention, common substrate can be used at least one power semiconductor and at least one integrated circuit.Therefore, by the present invention, it no longer is essential providing independent circuit board to be used at least one integrated circuit.Therefore, the manufacturing of power semiconductor modular is simplified by the present invention, and has improved simultaneously the reliability of power semiconductor modular.
The advantageous make of the tool of this method be similar to substrate the advantageous make of tool learn that vice versa.
The advantageous make of tool of the present invention is drawn by dependent claims.
Having shown that tool is advantageous is, at method step b) and c) between:
-nonconducting enamelled coating is applied on the narrow conductor tracks, and at method step c) afterwards,
-nonconducting enamelled coating is removed.
By nonconducting enamelled coating is applied on the narrow conductor tracks, can prevent that the first metal layer is at narrow conductor tracks substrates with simple mode and method.
Shown that tool is advantageous to be to carry out following method step subsequently:
-at narrow conductor tracks and/or the first metal layer substrates the second metal level.
The second metal level preferably serves as for the protective layer of the first metal layer and/or serves as the attached articulamentum that increases of connection for material sealed (stoffschl ü ssig) (for example connect as sintering or melting welding connects).
Having shown that tool is advantageous is, at least one wide conductor tracks has the width of at least 3000 μ m, and this is because along with the increase of the width of at least one wide conductor tracks, the current capacity of conductor tracks also increases.
In addition, shown that tool is advantageous and be that narrow conductor tracks has the width of 100 μ m to 1000 μ m, this is because all integrated circuits commonly used can be connected with narrow conductor tracks.
In addition, shown that tool is advantageous and be that the first metal layer has the thickness of 1 μ m to 30 μ m, this is because guaranteed so the good mechanical stability of the first metal layer.
In addition, shown that tool is advantageous and be that the first metal layer comprises silver and/or copper, this is because realized thus very high conductive capability and the capacity of heat transmission of the first metal layer.
In addition, shown that tool is advantageous and be that the first metal layer has the thickness of 100 μ m to 500 μ m, this is because realized so very high current capacity.
In addition, shown that tool is advantageous and be, at method step b) in additionally,
-the second metal layer is applied on the second side that the insulating material body and the first side this insulating material body arrange opposed to each other;
And at method step c) in additionally,
-at the second metal layer substrates the 3rd metal level.
The 3rd metal level is preferred for substrate is connected with circuit board or cooling body.
In addition, having shown that tool is advantageous is, the first metal layer has the bonding conductor track, wherein, second area has at least one first wide conductor tracks and at least one second wide conductor tracks, wherein, the conduction of bonding conductor track by the first quantity, the first brace that is formed by the first metal layer is connected with the first wide conductor tracks, and the conduction of the first wide conductor tracks by the second quantity, the second brace that is formed by the first metal layer is connected with the second wide conductor tracks, wherein, the width separately of the quantity separately of brace and/or brace depends on separately wide conductor tracks and the spacing of bonding conductor track and increase along with the increase of spacing.By these measures, guaranteed the basically unified thickness of the first metal layer on the first and second wide conductor tracks.
In addition, having shown that tool is advantageous is, the first metal layer has the bonding conductor track, wherein, second area has at least one first wide conductor tracks and at least one second wide conductor tracks, wherein, the bonding conductor track has substantially the same spacing with respect to the first and second wide conductor tracks, wherein, the bonding conductor track is connected with the first wide conductor tracks by the first brace that is formed by the first metal layer, and is connected with the second wide conductor tracks by the second brace that is formed by the first metal layer.By these measures, guaranteed the basically unified thickness of the first metal layer on the first and second wide conductor tracks.
In addition, shown that tool is advantageous and be that the first metal layer is comprised of copper, this is because copper has very high conductive capability.
In addition, having shown that tool is advantageous is, at least one power semiconductor is connected with the first metal layer or be furnished with at the first metal layer in the situation of the second metal level be arranged in the first metal layer on the second metal level be connected, and at least one integrated circuit is connected with narrow conductor tracks or be furnished with at narrow conductor tracks in the situation of the second metal level be arranged in narrow conductor tracks on the second metal level be connected because can make power semiconductor modular with simple mode and method like this.
In addition, having shown that tool is advantageous is, connecting material separately in locking manner, especially connect by means of sintering or melting welding connects to carry out, because the sealed connection of material, for example connect as sintering or the melting welding connection, represent the common connection in the power semiconductor modular.
In addition, shown that tool is advantageous and be that at least one power semiconductor is arranged in the substrate and with the first metal layer conduction and is connected, and at least one integrated circuit is arranged in the substrate and conduct electricity with narrow conductor tracks and to be connected.Obtain thus especially reliably power semiconductor modular.
Description of drawings
Embodiments of the invention are shown in the drawings and following it is described in detail.Wherein:
Fig. 1 illustrates enforcement steps of a method in accordance with the invention substrate blank afterwards with the form of schematic cross sectional view;
Fig. 2 illustrates enforcement other method step substrate blank afterwards with the form of schematic cross sectional view;
Fig. 3 illustrates enforcement other method step substrate blank afterwards with the form of schematic cross sectional view;
Fig. 4 illustrates enforcement other method step afterwards according to substrate of the present invention with the form of schematic cross sectional view;
Fig. 5 illustrates enforcement steps of a method in accordance with the invention substrate blank afterwards with the form of the schematic plan of substrate blank;
Fig. 6 illustrates the another kind of make of methods ﹠﹠ steps of implementation substrate blank afterwards with the form of the schematic plan of substrate blank;
Fig. 7 illustrates the another kind of make of methods ﹠﹠ steps of implementation substrate blank afterwards with the form of the schematic plan of substrate blank;
Fig. 8 illustrates the another kind of make of implementing after the other method step according to substrate of the present invention with the form of schematic cross sectional view;
Fig. 9 illustrates according to power semiconductor modular of the present invention with the form of schematic cross sectional view; And
Figure 10 illustrates another according to power semiconductor modular of the present invention with the form of schematic cross sectional view.
Embodiment
In the first method step, provide nonconducting insulating material body 1.Form with schematic cross sectional view in Fig. 1 illustrates another steps of a method in accordance with the invention of enforcement substrate blank 7a afterwards.Substrate blank 7a shown in Figure 5 attaches troops to a unit in the schematic plan of Fig. 1.In the method step, the first metal layer 2a of structurized conduction is executed cloth on the first side 15a of insulating material body 1, wherein, the first metal layer 2a has the first and second zones, wherein, first area 22a has narrow conductor tracks 21, and second area 22b has at least one wide conductor tracks.In the scope of present embodiment, second area 22b has the first wide conductor tracks 20a and the second wide conductor tracks 20b.In Fig. 1 and Fig. 5, for general view, only a narrow conductor tracks is provided with Reference numeral.Here need to prove, narrow conductor tracks only schematically is shown, and narrow conductor tracks can stretch out from the 22a of first area and for example can stretch among the second area 22b obviously in Fig. 5.In addition, here need to prove, wide conductor tracks equally only schematically is shown, and wide conductor tracks can stretch out from second area 22b obviously in Fig. 5.
Wide conductor tracks preferably has the width of at least 3000 μ m, especially has the width of at least 4000 μ m.Narrow conductor tracks preferably has the width of 100 μ m to 1000 μ m, especially has the width of 100 μ m to 300 μ m.
In the scope of present embodiment, in the method step, also the second metal layer 2b electricity is applied on the second side 15b that insulating material body 1 and the first side 15a this insulating material body 1 arrange opposed to each other.Like this, insulating material body 1 is arranged between the first metal layer 2a and the second metal layer 2b.Insulating material body 1 for example can be formed and preferably be had by pottery (for example as aluminium oxide or AIN) thickness of 300 μ m to 1000 μ m.Metal layer 2a and 2b for example can be comprised of copper and/or silver or be comprised of copper alloy and/or silver alloy basically.The first metal layer 2a has the structure corresponding to the distribution of the having a mind to ground structure of narrow conductor tracks and wide conductor tracks.Therefore, in the scope of present embodiment, the first metal layer 2a for example has discontinuities 4 and 4 ', and this discontinuities is spaced with conductor tracks.The second metal layer 2b is preferably non-structured, but also can be structured enforcement equally.
The first and second metal layer 2a, 2b preferably have the thickness of 1 μ m to 30 μ m, and wherein, the first and second metal layer 2a, 2b can have different thickness.
Preferably the first and second metal layers are applied on the first and second sides of insulating material body 1, method is: the metallization lotion that at first will for example comprise cupric and/or silver-colored particulate and solvent covers on the first and second side 15a and 15b that are added to insulating material body 1 at the position that should have metal layer, and then the lotion that for example under 180 ℃, will metallize oven dry, then in stove (preferably in a vacuum) preferably at about 1000 ℃ of lower heating of metal lotions and such roasting metallization lotion.
Need to prove that here Fig. 1 to Figure 10 is indicative icon, and especially, in the mode that conforms with size layer thickness is not shown.
Form with schematic cross sectional view in Fig. 2 illustrates another method step of implementing of enforcement substrate blank 7a afterwards in the scope of present embodiment.In the method step, nonconducting enamelled coating 3 is applied on the narrow conductor tracks 21.Enamelled coating 3 preferably has the thickness of 5 μ m to 300 μ m.
Form with schematic cross sectional view in Fig. 3 illustrates enforcement other method step substrate blank 7a afterwards.In the method step, the first metal layer 5 that is to say in the scope of present embodiment at the first and second wide conductor tracks 20a and 20b substrates at least one wide conductor tracks substrates.In addition, in the scope of present embodiment, the 3rd metal level 6 is at the second metal layer 2b substrates.For this reason, substrate blank 7a immersion is equipped with in the container of electroplate liquid, and the first and second metal layer 2a, 2b are connected with the negative pole conduction of voltage source, and the electrode that is arranged in the electroplate liquid is connected with the positive pole conduction of voltage source, thereby so that electric current begins to flow and the 3rd metal level 6 deposits on the second metal layer 2b so that the first metal layer 5 deposits to wide conductor tracks 20a and 20b is upper.Enamelled coating 3 has stoped the first metal layer electro-deposition to narrow conductor tracks 21.Alternatively, also can abandon executing cloth enamelled coating 3, and only make wide conductor tracks and the second metal layer 2b is connected with the negative pole conduction of voltage source, thereby prevent that the first metal layer electro-deposition is to narrow conductor tracks 21.At this, in the scope of present embodiment, electroplate liquid comprises copper ion, thereby the first and the 3rd metal level 5 and 6 is comprised of copper in the present embodiment.
The first and the 3rd metal level 5 and 6 preferably has the thickness of 100 μ m to 500 μ m.First with the 3rd metal level 5 and 6 thickness needn't be identical.Because in the present embodiment, the thickness of the 3rd metal level 6 is less than the thickness of the first metal layer 5, so in the present embodiment, when carrying out electro-deposition, when the 3rd metal level 6 reaches set thickness, with the electrical connection disconnection of the second metal layer 2b to voltage source, thereby the first metal layer 5 is increased, until this first metal layer reaches set thickness.
But, also can utilize additive method to obtain different deposit thickness, therefore can be for example after the 3rd metal level 6 reaches set thickness, interrupt electro-deposition and execute the nonconducting lacquer of cloth at the 3rd metal level 6, and next proceed electro-deposition until the first metal layer 5 reaches set height h, wherein, owing to be applied to the lacquer on the 3rd metal level 6, no longer increase at this 3rd metal level 6.
The first metal layer 5 that is arranged on wide conductor tracks 20a and the 20b has been reinforced conductor tracks 20a and 20b, thus form can the carry load electric current conductor tracks, the load current with corresponding large current strength can flow through this conductor tracks.In Fig. 3, the conductor tracks of energy carry load electric current is provided with Reference numeral 25.At this, the conductor tracks 25 of energy carry load electric current is comprised of with the first metal layer 5 that is arranged on this conductor tracks 20a conductor tracks 20a.
When the first metal layer during at wide conductor tracks substrates, tool is advantageous to be, wide conductor tracks is connected to each other by the first metal layer when electro-deposition, and this is because be not that each wide conductor tracks must be connected with the negative pole conduction of voltage source in the electric lead of wide conductor tracks by attaching troops to a unit respectively when electro-deposition.
Therefore, preferably, as shown in Figure 6, the first metal layer 2a has bonding conductor track 8, wherein, bonding conductor track 8 conduction by the first quantity in Fig. 6, the first brace 9 that is formed by the first metal layer 2a is connected with the first wide conductor tracks 20a, and the conduction of the first wide conductor tracks 20a by the second quantity, the second brace 9 ' that is formed by the first metal layer 2a is connected with the second wide conductor tracks 20b, wherein, the respective width c of the respective numbers of brace and/or brace depends on separately wide conductor tracks and the spacing a of bonding conductor track 8 and increase along with the increase of spacing a.In the situation of present embodiment, the first quantity is " 1 " and the second quantity is " 2 ", and wherein, all braces 9 all have unified width c.
To this alternatively, as shown in Figure 7, bonding conductor track 8 can have the especially identical spacing of substantially the same spacing a(a) with 20b with respect to the first and second wide conductor tracks 20a, wherein, bonding conductor track 8 is connected with the first wide conductor tracks 20a by the first brace 9 that is formed by the first metal layer 2a, and is connected with the second wide conductor tracks 20b by the second brace 9 ' that is formed by the first metal layer 2a.The first and second braces 9 and 9 ' have substantially the same length, especially have identical length.
Of the present invention when the advantageous make of the tool shown in Fig. 6 and Fig. 7 can be in electro-deposition at the basically unified thickness of the first and second wide conductor tracks 20a and 20b deposition the first metal layer 5.
Bonding conductor track and/or brace preferably just utilized nonconducting lacquer to cover before the electro-deposition the first metal layer, thereby when electro-deposition, did not have the first metal layer deposition at bonding conductor track and/or brace.
In the present embodiment, after the electro-deposition the first metal layer, again remove the enamelled coating 3 that in the scope of present embodiment, is applied on the narrow conductor tracks 21.Fig. 4 illustrate implement after this step according to substrate 7 of the present invention.
In the scope of present embodiment, and then as shown in Figure 8 with 10 electro-deposition of the second metal level to narrow conductor tracks 21 and electro-deposition to the first metal layer 5 and on electro-deposition to the three metal levels 6.The second metal level 10 preferably is comprised of silver.The second metal level 10 preferably serves as the protective layer of the first and the 3rd metal level and the protective layer of narrow conductor tracks 21, and/or serves as the attached articulamentum that increases that sintering connects or melting welding connects.The second metal level 10 preferably has the thickness of 0.1 μ m to 10 μ m.Here need to prove, and nonessential the second metal level 10 is applied on the first metal layer 5, narrow conductor tracks 21 or the 3rd metal level 6.
In addition, here need to prove, if for example should be only at narrow conductor tracks 21 substrates the second metal level 10, before electro-deposition the second metal level 10, just can cover with the lacquer of electric insulation the first and the 3rd metal level 5 and 6 so, thereby so that only at narrow conductor tracks 21 substrates the second metal level 10.
In addition, here need to prove, if for example should be only at the first metal layer 5 substrates the second metal level 10, before electro-deposition the second metal level 10, just can cover with the lacquer of electric insulation narrow conductor tracks 21 and the 3rd metal level 6 so, thereby so that only at the first metal layer 5 substrates the second metal level 10.
Before electro-deposition the second metal level 10, utilize respectively the lacquer of electric insulation to cover following element, this element should not come coating with the second metal level 10.
Fig. 8 illustrates the substrate 7 after electro-deposition the second metal level 10.
And then, preferably brace is removed from insulating material body 1, for example removed the brace mode by machinery.If brace did not cover with insullac before electro-deposition the first metal layer 5 and in case of necessity electro-deposition the second metal level 10, so for example remove the brace mode by machinery and remove brace, comprise removing being arranged in the first metal layer 5 on the brace and being arranged in case of necessity the second metal level 10 on the first metal layer 5 of brace.
In order to make according to power semiconductor modular 26 of the present invention, and then in the other method step (as shown in Figure 9), at least one power semiconductor is connected with the first metal layer 5 or (as according among the embodiment of Fig. 9) be furnished with at the first metal layer 5 in the situation of the second metal level 10 be arranged in the first metal layer 5 on the second metal level 10 be connected, and at least one integrated circuit 17 is connected with narrow conductor tracks 21 or (as in the present embodiment) be furnished with at narrow conductor tracks 21 in the situation of the second metal level 10 be arranged in narrow conductor tracks 21 on the second metal level 10 be connected.In the scope of present embodiment, the first power semiconductor 18 that for example is configured to IGBT be connected the second power semiconductor 19 that is configured to diode and be connected with the second metal level 10.At this, first method that is connected to of at least one power semiconductor is middle the realization step by step, and the step by step middle realization of second method that is connected to of integrated circuit 17.At this, the first method can be carried out before step by step in the second method step by step, carries out simultaneously step by step with the second method or carries out after step by step in the second method.
At this, in the scope of present embodiment, according to Fig. 9, the first power semiconductor 18 be connected that power semiconductor 19 is connected by means of sintering with the second metal level 10 on being arranged in the first metal layer 5 or melting welding connects and is connected to each other, thereby power semiconductor 18,19 and the first metal layer 5 between be furnished with sinter layer or melting welding layer 14.In addition, in the scope of present embodiment, integrated circuit 17 is connected by means of sintering with the second metal level 10 on being arranged in narrow conductor tracks by its adapter pin 16 or melting welding connects and is connected to each other, thereby is furnished with sinter layer or melting welding layer 14 ' between integrated circuit 17 and the second metal level 10.At this, sinter layer separately preferably is comprised of silver at least basically, and melting welding layer separately is comprised of tin at least basically.
Another embodiment of the present invention shown in Figure 10, this embodiment is basically corresponding to the embodiment of the present invention according to Fig. 9, wherein, be different from and according to the embodiment of Fig. 9 be, the first metal layer 5 does not come coating with the second metal level 10 in according to the embodiment of Figure 10, thereby so that the first power semiconductor 18 be connected power semiconductor 19 and for example connect by means of melting welding connection or sintering and be connected with the first metal layer 5.
In the embodiment according to Fig. 9 and Figure 10, power semiconductor 18 is arranged in the substrate 7 and is connected with the first metal layer 5 conductions with being connected, and integrated circuit 17 is arranged in the substrate 7 and conduct electricity with narrow conductor tracks 21 and to be connected.At this, conduction separately connects is undertaken by sinter layer or melting welding layer 14, and also additionally undertaken by the second metal level 10 if present, and additionally at least one other metal level carries out by this if possible also additionally to be furnished with the words of at least one other metal level at the second metal level 10.
Here need to prove, as described previously, on the second metal level 10, can also additionally be furnished with at least one other metal level, wherein, on meaning of the present invention, with at least one power semiconductor and/or at least one integrated circuit be interpreted as being connected of at least one power semiconductor and/or at least one integrated circuit and the second metal level being connected of at least one other metal level.
In addition, here need to prove, especially in the situation that sintering connects, coupling assembling as two difference element to be connected, these two elements to be connected this element should side connected to one another on can be provided with separately the attached articulamentum that increases, this increases attached articulamentum and for example can at least basically be comprised of silver.At this, element to be connected separately is not necessarily need to set by means of electro-deposition to increase attached articulamentum.
Need to prove that here identical element is provided with identical Reference numeral in the accompanying drawings.

Claims (16)

1. method for the manufacture of the substrate (7) of at least one power semiconductor (18,19), described method has following method step:
A) provide nonconducting insulating material body (1);
B) first metal layer (2a) of structurized conduction is executed cloth on first side (15a) of described insulating material body (1), wherein, described the first metal layer (2a) has the first and second zones (22a, 22b), wherein, described first area (22a) has narrow conductor tracks (21), and described second area (22b) has at least one wide conductor tracks (20a, 20b); And
C) at described at least one wide conductor tracks (20a, 20b) substrates the first metal layer (5).
2. method according to claim 1 is characterized in that, at method step b) and c) between:
-nonconducting enamelled coating (3) is applied on the described narrow conductor tracks (21), and at method step c) afterwards,
-described nonconducting enamelled coating (3) is removed.
3. according to the described method of one of aforementioned claim, described method has following method step subsequently:
-at described narrow conductor tracks (21) and/or described the first metal layer (5) substrates the second metal level (10).
4. according to the described method of one of aforementioned claim, it is characterized in that described at least one wide conductor tracks (20a) has the width (b) of at least 3000 μ m.
5. according to the described method of one of aforementioned claim, it is characterized in that described narrow conductor tracks (21) has the width (b ') of 100 μ m to 1000 μ m.
6. according to the described method of one of aforementioned claim, it is characterized in that described the first metal layer (5) has the thickness of 1 μ m to 30 μ m.
7. according to the described method of one of aforementioned claim, it is characterized in that described the first metal layer (5) comprises silver and/or copper.
8. according to the described method of one of aforementioned claim, it is characterized in that described the first metal layer (5) has the thickness of 100 μ m to 500 μ m.
9. according to the described method of one of aforementioned claim, it is characterized in that, at method step b) in additionally,
-the second metal layer (2b) is applied on the second side (15b) that described insulating material body (1) and the first side (15a) described insulating material body (1) arrange opposed to each other;
And at method step c) in additionally,
-at described the second metal layer (2b) substrates the 3rd metal level (6).
10. according to the described method of one of aforementioned claim, it is characterized in that, described the first metal layer (2a) has bonding conductor track (8), wherein, described second area (22b) has at least one first wide conductor tracks and at least one second wide conductor tracks (20a, 20b), wherein, the conduction of described bonding conductor track (8) by the first quantity, the first brace (9) that is formed by described the first metal layer (2a) is connected with the described first wide conductor tracks (20a), and the conduction of the described first wide conductor tracks (20a) by the second quantity, the second brace (9 ') that is formed by described the first metal layer (2a) is connected with the described second wide conductor tracks (20b), wherein, described brace (9,9 ') quantity separately and/or described brace (9,9 ') width separately (c) depends on wide conductor tracks (20a separately, 20b) increase with the spacing (a) of described bonding conductor track (8) and along with the increase of spacing (a).
11. according to claim 1 to one of 9 described methods, it is characterized in that, described the first metal layer (2a) has bonding conductor track (8), wherein, described second area (22b) has at least one first wide conductor tracks and at least one second wide conductor tracks (20a, 20b), wherein, described bonding conductor track (8) is with respect to the first and second wide conductor tracks (20a, 20b) has substantially the same spacing (a), wherein, described bonding conductor track (8) is connected with the described first wide conductor tracks (20a) by the first brace (9) that is formed by described the first metal layer (2a), and is connected with the described second wide conductor tracks (20b) by the second brace (9 ') that is formed by described the first metal layer (2a).
12., it is characterized in that described the first metal layer (5) is comprised of copper according to the described method of one of aforementioned claim.
13. method for the manufacture of power semiconductor modular (26), wherein, described method comprises that described method for the manufacture of power semiconductor modular (26) also comprises following method step according to the method for the described substrate (7) for the manufacture of at least one power semiconductor (18,19) of one of aforementioned claim:
E) described at least one power semiconductor (18,19) is connected with described the first metal layer (5) or be furnished with at described the first metal layer (5) in the situation of the second metal level (10) be arranged in described the first metal layer (5) on the second metal level (10) be connected, and at least one integrated circuit (17) is connected with described narrow conductor tracks (21) or be furnished with at described narrow conductor tracks (21) in the situation of the second metal level (10) be arranged in described narrow conductor tracks (21) on the second metal level (10) be connected.
14. the method for the manufacture of power semiconductor modular according to claim 13, wherein, connecting material separately in locking manner, especially connect by means of sintering or melting welding connects to carry out.
15. one kind is used at least one power semiconductor (18,19) substrate, wherein, described substrate (7) has nonconducting insulating material body (1) and is arranged on first side (15a) of described insulating material body (1), structurized the first metal layer (2a), wherein, described the first metal layer (2a) has the first and second zone (22a, 22b), wherein, described first area (22a) has narrow conductor tracks (21), and described second area has at least one wide conductor tracks (22a, 22b), wherein, at described at least one wide conductor tracks (22a, be furnished with the first metal layer (2a) 22b).
16. power semiconductor modular with substrate according to claim 15, wherein, it is upper and is connected with described the first metal layer (5) conduction that at least one power semiconductor (10a, 10b) is arranged in described substrate (7), and at least one integrated circuit (17) is arranged in the described substrate and conduct electricity with described narrow conductor tracks (21) and to be connected.
CN201310148433.7A 2012-04-25 2013-04-25 Substrate and the method for manufacturing the substrate of at least one power semiconductor Expired - Fee Related CN103377950B (en)

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DE102012206758.2 2012-04-25

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