JP6138603B2 - 冷却装置、冷却装置の製造方法及び半導体装置 - Google Patents

冷却装置、冷却装置の製造方法及び半導体装置 Download PDF

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Publication number
JP6138603B2
JP6138603B2 JP2013131816A JP2013131816A JP6138603B2 JP 6138603 B2 JP6138603 B2 JP 6138603B2 JP 2013131816 A JP2013131816 A JP 2013131816A JP 2013131816 A JP2013131816 A JP 2013131816A JP 6138603 B2 JP6138603 B2 JP 6138603B2
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JP
Japan
Prior art keywords
substrate
pipe
flow path
cooling device
metal layer
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2013131816A
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English (en)
Japanese (ja)
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JP2015008169A (ja
JP2015008169A5 (enExample
Inventor
坂口　秀明
秀明 坂口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2013131816A priority Critical patent/JP6138603B2/ja
Priority to US14/311,416 priority patent/US9646924B2/en
Publication of JP2015008169A publication Critical patent/JP2015008169A/ja
Publication of JP2015008169A5 publication Critical patent/JP2015008169A5/ja
Application granted granted Critical
Publication of JP6138603B2 publication Critical patent/JP6138603B2/ja
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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
    • H01L23/473—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids by flowing liquids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894—Materials of the insulating layers or coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Cooling Or The Like Of Electrical Apparatus (AREA)
JP2013131816A 2013-06-24 2013-06-24 冷却装置、冷却装置の製造方法及び半導体装置 Active JP6138603B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2013131816A JP6138603B2 (ja) 2013-06-24 2013-06-24 冷却装置、冷却装置の製造方法及び半導体装置
US14/311,416 US9646924B2 (en) 2013-06-24 2014-06-23 Interposer, method for manufacturing interposer, and semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2013131816A JP6138603B2 (ja) 2013-06-24 2013-06-24 冷却装置、冷却装置の製造方法及び半導体装置

Publications (3)

Publication Number Publication Date
JP2015008169A JP2015008169A (ja) 2015-01-15
JP2015008169A5 JP2015008169A5 (enExample) 2016-03-10
JP6138603B2 true JP6138603B2 (ja) 2017-05-31

Family

ID=52110773

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2013131816A Active JP6138603B2 (ja) 2013-06-24 2013-06-24 冷却装置、冷却装置の製造方法及び半導体装置

Country Status (2)

Country Link
US (1) US9646924B2 (enExample)
JP (1) JP6138603B2 (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6274058B2 (ja) * 2014-09-22 2018-02-07 株式会社デンソー 電子装置、及び電子装置を備えた電子構造体
US10694641B2 (en) * 2016-04-29 2020-06-23 Intel Corporation Wickless capillary driven constrained vapor bubble heat pipes for application in electronic devices with various system platforms
JP7159620B2 (ja) * 2018-05-30 2022-10-25 富士電機株式会社 半導体装置、冷却モジュール、電力変換装置及び電動車両
US10763186B2 (en) * 2018-12-31 2020-09-01 Micron Technology, Inc. Package cooling by coil cavity
US11735495B2 (en) * 2019-02-27 2023-08-22 Intel Corporation Active package cooling structures using molded substrate packaging technology
US10872835B1 (en) * 2019-07-03 2020-12-22 Micron Technology, Inc. Semiconductor assemblies including vertically integrated circuits and methods of manufacturing the same
WO2021186782A1 (ja) * 2020-03-18 2021-09-23 株式会社村田製作所 回路基板モジュール
US12300579B2 (en) * 2021-06-14 2025-05-13 Intel Corporation Liquid cooled interposer for integrated circuit stack

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5119890B2 (enExample) 1971-11-29 1976-06-21
FR2578099B1 (fr) 1985-02-26 1987-12-04 Eurofarad Substrat monolithique pour composant electronique de puissance, et procede pour sa fabrication
US5870823A (en) * 1996-11-27 1999-02-16 International Business Machines Corporation Method of forming a multilayer electronic packaging substrate with integral cooling channels
US6219237B1 (en) 1998-08-31 2001-04-17 Micron Technology, Inc. Structure and method for an electronic assembly
JP4859520B2 (ja) 2006-04-28 2012-01-25 株式会社カネカ 血圧降下性ペプチドの吸着材、吸着方法および吸着装置
JP2008159619A (ja) * 2006-12-20 2008-07-10 Shinko Electric Ind Co Ltd 半導体装置
JP2010161184A (ja) * 2009-01-08 2010-07-22 Hitachi Ltd 半導体装置
US20120103575A1 (en) * 2010-11-03 2012-05-03 Hon Hai Precision Industry Co., Ltd. Cooling device
KR101739939B1 (ko) * 2011-03-16 2017-05-26 삼성전자주식회사 반도체 장치의 제조 방법
US8987891B2 (en) * 2012-03-05 2015-03-24 Centipede Systems, Inc. Heat sink apparatus for microelectronic devices
US8860212B1 (en) * 2013-04-15 2014-10-14 Freescale Semiconductor, Inc. Fluid cooled semiconductor die package

Also Published As

Publication number Publication date
US9646924B2 (en) 2017-05-09
JP2015008169A (ja) 2015-01-15
US20140376189A1 (en) 2014-12-25

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