JP6049877B2 - 集積回路のウェハ裏面の層からの基板貫通ビアの統合 - Google Patents

集積回路のウェハ裏面の層からの基板貫通ビアの統合 Download PDF

Info

Publication number
JP6049877B2
JP6049877B2 JP2015521717A JP2015521717A JP6049877B2 JP 6049877 B2 JP6049877 B2 JP 6049877B2 JP 2015521717 A JP2015521717 A JP 2015521717A JP 2015521717 A JP2015521717 A JP 2015521717A JP 6049877 B2 JP6049877 B2 JP 6049877B2
Authority
JP
Japan
Prior art keywords
layer
sti
pad
present disclosure
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2015521717A
Other languages
English (en)
Japanese (ja)
Other versions
JP2015527733A (ja
JP2015527733A5 (enExample
Inventor
ヴィディヤ・ラマチャンドラ
シーチュン・グ
Original Assignee
クアルコム，インコーポレイテッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by クアルコム，インコーポレイテッド filed Critical クアルコム，インコーポレイテッド
Publication of JP2015527733A publication Critical patent/JP2015527733A/ja
Publication of JP2015527733A5 publication Critical patent/JP2015527733A5/ja
Application granted granted Critical
Publication of JP6049877B2 publication Critical patent/JP6049877B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes)
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes) consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2015521717A 2012-07-09 2013-07-09 集積回路のウェハ裏面の層からの基板貫通ビアの統合 Expired - Fee Related JP6049877B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201261669611P 2012-07-09 2012-07-09
US61/669,611 2012-07-09
US13/790,625 2013-03-08
US13/790,625 US9219032B2 (en) 2012-07-09 2013-03-08 Integrating through substrate vias from wafer backside layers of integrated circuits
PCT/US2013/049686 WO2014011615A1 (en) 2012-07-09 2013-07-09 Integrating through substrate vias from wafer backside layers of integrated circuits

Publications (3)

Publication Number Publication Date
JP2015527733A JP2015527733A (ja) 2015-09-17
JP2015527733A5 JP2015527733A5 (enExample) 2016-04-28
JP6049877B2 true JP6049877B2 (ja) 2016-12-21

Family

ID=49877888

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2015521717A Expired - Fee Related JP6049877B2 (ja) 2012-07-09 2013-07-09 集積回路のウェハ裏面の層からの基板貫通ビアの統合

Country Status (7)

Country Link
US (1) US9219032B2 (enExample)
EP (1) EP2870628A1 (enExample)
JP (1) JP6049877B2 (enExample)
KR (1) KR101654794B1 (enExample)
CN (1) CN104428887B (enExample)
TW (1) TWI575652B (enExample)
WO (1) WO2014011615A1 (enExample)

Families Citing this family (49)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9245790B2 (en) * 2013-01-23 2016-01-26 GlobalFoundries, Inc. Integrated circuits and methods of forming the same with multiple embedded interconnect connection to same through-semiconductor via
US9252080B1 (en) 2014-10-15 2016-02-02 Globalfoundries Inc. Dielectric cover for a through silicon via
US9515017B2 (en) 2014-12-18 2016-12-06 Intel Corporation Ground via clustering for crosstalk mitigation
CN104600027B (zh) * 2015-01-30 2017-10-27 华进半导体封装先导技术研发中心有限公司 一种tsv通孔的制备工艺
CN104600026A (zh) * 2015-01-30 2015-05-06 华进半导体封装先导技术研发中心有限公司 Cis产品tsv孔底部pad表面绝缘层的刻蚀方法
CN106298627B (zh) * 2015-05-20 2019-06-28 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法和电子装置
WO2017052558A1 (en) * 2015-09-24 2017-03-30 Intel Corporation Techniques for revealing a backside of an integrated circuit device, and associated configurations
US9673275B2 (en) 2015-10-22 2017-06-06 Qualcomm Incorporated Isolated complementary metal-oxide semiconductor (CMOS) devices for radio-frequency (RF) circuits
US9786592B2 (en) * 2015-10-30 2017-10-10 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit structure and method of forming the same
WO2017150146A1 (ja) * 2016-02-29 2017-09-08 パナソニック・タワージャズセミコンダクター株式会社 半導体装置及びその製造方法
KR102652854B1 (ko) * 2016-08-17 2024-04-02 삼성전자주식회사 반도체 소자 및 그 제조 방법
US10446546B2 (en) * 2016-11-17 2019-10-15 Taiwan Semiconductor Manufacturing Company Limited Semiconductor structures and methods of forming the same
EP3324436B1 (en) * 2016-11-21 2020-08-05 IMEC vzw An integrated circuit chip with power delivery network on the backside of the chip
CN107644840A (zh) * 2017-08-31 2018-01-30 长江存储科技有限责任公司 用于三维存储器的晶圆三维集成引线工艺及其结构
US10607887B2 (en) * 2017-08-31 2020-03-31 Yangtze Memory Technologies Co., Ltd. Method for forming three-dimensional integrated wiring structure and semiconductor structure thereof
CN107644841B (zh) * 2017-08-31 2019-01-01 长江存储科技有限责任公司 用于三维存储器的晶圆三维集成引线工艺及其结构
CN107644838B (zh) * 2017-08-31 2019-01-01 长江存储科技有限责任公司 用于三维存储器的晶圆三维集成引线工艺及其结构
CN107644837B (zh) * 2017-08-31 2019-01-01 长江存储科技有限责任公司 用于三维存储器的晶圆三维集成引线工艺及其结构
CN107644836A (zh) * 2017-08-31 2018-01-30 长江存储科技有限责任公司 用于三维存储器的晶圆三维集成引线工艺及其结构
US10651087B2 (en) 2017-08-31 2020-05-12 Yangtze Memory Technologies Co., Ltd. Method for forming three-dimensional integrated wiring structure and semiconductor structure thereof
US10559520B2 (en) * 2017-09-29 2020-02-11 Qualcomm Incorporated Bulk layer transfer processing with backside silicidation
US11508619B2 (en) 2018-01-26 2022-11-22 Agency For Science, Technology And Research Electrical connection structure and method of forming the same
WO2019195428A1 (en) 2018-04-04 2019-10-10 Qorvo Us, Inc. Gallium-nitride-based module with enhanced electrical performance and process for making the same
US12046505B2 (en) 2018-04-20 2024-07-23 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same utilizing localized SOI formation
CN118213279A (zh) 2018-07-02 2024-06-18 Qorvo美国公司 Rf半导体装置及其制造方法
KR102521658B1 (ko) 2018-09-03 2023-04-13 삼성전자주식회사 반도체 칩 및 이의 제조 방법
KR102576062B1 (ko) 2018-11-07 2023-09-07 삼성전자주식회사 관통 실리콘 비아를 포함하는 반도체 소자 및 그 제조 방법
US11646242B2 (en) 2018-11-29 2023-05-09 Qorvo Us, Inc. Thermally enhanced semiconductor package with at least one heat extractor and process for making the same
WO2020153983A1 (en) 2019-01-23 2020-07-30 Qorvo Us, Inc. Rf semiconductor device and manufacturing method thereof
US12125825B2 (en) 2019-01-23 2024-10-22 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US12057374B2 (en) 2019-01-23 2024-08-06 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US12046483B2 (en) 2019-01-23 2024-07-23 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US11387157B2 (en) * 2019-01-23 2022-07-12 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US12046570B2 (en) 2019-01-23 2024-07-23 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US10937690B2 (en) * 2019-03-26 2021-03-02 Micron Technology, Inc. Selective dielectric deposition
US10991667B2 (en) * 2019-08-06 2021-04-27 Taiwan Semiconductor Manufacturing Co., Ltd. Isolation structure for bond pad structure
US11217547B2 (en) 2019-09-03 2022-01-04 Taiwan Semiconductor Manufacturing Company, Ltd. Bond pad structure with reduced step height and increased electrical isolation
US12074086B2 (en) 2019-11-01 2024-08-27 Qorvo Us, Inc. RF devices with nanotube particles for enhanced performance and methods of forming the same
US11923238B2 (en) 2019-12-12 2024-03-05 Qorvo Us, Inc. Method of forming RF devices with enhanced performance including attaching a wafer to a support carrier by a bonding technique without any polymer adhesive
US12129168B2 (en) 2019-12-23 2024-10-29 Qorvo Us, Inc. Microelectronics package with vertically stacked MEMS device and controller device
CN111508929B (zh) * 2020-04-17 2022-02-22 北京北方华创微电子装备有限公司 图形片及半导体中间产物
KR102777683B1 (ko) 2020-08-04 2025-03-10 에스케이하이닉스 주식회사 웨이퍼 대 웨이퍼 본딩 구조를 갖는 반도체 장치 및 그 제조방법
US11862535B2 (en) 2020-09-16 2024-01-02 Taiwan Semiconductor Manufacturing Company, Ltd. Through-substrate-via with reentrant profile
CN116583949A (zh) 2020-12-11 2023-08-11 Qorvo美国公司 多级3d堆叠式封装和其形成方法
CN112956018B (zh) * 2021-01-27 2022-06-21 英诺赛科(苏州)半导体有限公司 半导体器件结构及其制造方法
US12062571B2 (en) 2021-03-05 2024-08-13 Qorvo Us, Inc. Selective etching process for SiGe and doped epitaxial silicon
CN113394185A (zh) * 2021-06-10 2021-09-14 武汉新芯集成电路制造有限公司 半导体器件及其制作方法、芯片
US11810882B2 (en) * 2022-03-01 2023-11-07 Micron Technology, Inc. Solder based hybrid bonding for fine pitch and thin BLT interconnection
US20240038657A1 (en) * 2022-07-26 2024-02-01 Celestial Ai Inc. Via formed using a partial plug that extends into a substrate

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6638844B1 (en) 2002-07-29 2003-10-28 Chartered Semiconductor Manufacturing Ltd. Method of reducing substrate coupling/noise for radio frequency CMOS (RFCMOS) components in semiconductor technology by backside trench and fill
US7531407B2 (en) 2006-07-18 2009-05-12 International Business Machines Corporation Semiconductor integrated circuit devices having high-Q wafer backside inductors and methods of fabricating same
US7741218B2 (en) 2007-02-27 2010-06-22 Freescale Semiconductor, Inc. Conductive via formation utilizing electroplating
US7786584B2 (en) 2007-11-26 2010-08-31 Infineon Technologies Ag Through substrate via semiconductor components
JP2011515843A (ja) 2008-03-19 2011-05-19 アイメック 基板貫通バイアの作製方法
FR2930840B1 (fr) * 2008-04-30 2010-08-13 St Microelectronics Crolles 2 Procede de reprise de contact sur un circuit eclaire par la face arriere
JP5528430B2 (ja) * 2008-05-02 2014-06-25 アイメック 酸化層の形成方法
US7956442B2 (en) 2008-10-09 2011-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Backside connection to TSVs having redistribution lines
JP2011003645A (ja) * 2009-06-17 2011-01-06 Sharp Corp 半導体装置およびその製造方法
JP5101575B2 (ja) * 2009-07-28 2012-12-19 株式会社東芝 半導体装置およびその製造方法
JP4987928B2 (ja) 2009-09-24 2012-08-01 株式会社東芝 半導体装置の製造方法
JP2011108690A (ja) * 2009-11-12 2011-06-02 Panasonic Corp 半導体装置及びその製造方法
US8338939B2 (en) 2010-07-12 2012-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. TSV formation processes using TSV-last approach

Also Published As

Publication number Publication date
TWI575652B (zh) 2017-03-21
KR101654794B1 (ko) 2016-09-06
US20140008757A1 (en) 2014-01-09
JP2015527733A (ja) 2015-09-17
KR20150028845A (ko) 2015-03-16
TW201409612A (zh) 2014-03-01
WO2014011615A1 (en) 2014-01-16
EP2870628A1 (en) 2015-05-13
CN104428887B (zh) 2017-08-11
CN104428887A (zh) 2015-03-18
US9219032B2 (en) 2015-12-22

Similar Documents

Publication Publication Date Title
JP6049877B2 (ja) 集積回路のウェハ裏面の層からの基板貫通ビアの統合
JP5706055B2 (ja) Ｔｓｖの歪緩和のための構造および方法
JP6012763B2 (ja) 基板貫通ビアを集積回路の中間工程層に組み込むこと
US20240297099A1 (en) Self-aligned contact openings for backside through substrate vias
JP6068492B2 (ja) 低誘電率配線層に基板貫通ビアのパターンを形成するための低誘電率誘電体保護スペーサ
KR101918609B1 (ko) 집적회로 소자
CN101842886B (zh) 用于在半导体结构上制造次分辨率对准标记的方法及包含次分辨率对准标记的半导体结构
WO2019210617A1 (zh) 晶圆级系统封装方法及封装结构
CN113345857B (zh) 半导体元件及其制备方法
TW201909362A (zh) 用於著陸在不同接觸區階層的接觸方案
CN103515302B (zh) 半导体元件与制作方法
WO2011009063A1 (en) Barrier layer on polymer passivation for integrated circuit packaging
JP5845781B2 (ja) 半導体装置の製造方法
US11315904B2 (en) Semiconductor assembly and method of manufacturing the same
JP5751131B2 (ja) 半導体装置及びその製造方法
JP2015038932A (ja) 電子デバイス及びその製造方法
US20240162082A1 (en) Manufacturing method of semiconductor structure

Legal Events

Date Code Title Description
A529 Written submission of copy of amendment under article 34 pct

Free format text: JAPANESE INTERMEDIATE CODE: A529

Effective date: 20150108

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20160307

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20160307

A871 Explanation of circumstances concerning accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A871

Effective date: 20160307

A975 Report on accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A971005

Effective date: 20160607

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20160613

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20161024

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20161122

R150 Certificate of patent or registration of utility model

Ref document number: 6049877

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees