KR101654794B1 - 집적 회로들의 웨이퍼 후면 층들로부터 기판 관통 비아들의 통합 - Google Patents
집적 회로들의 웨이퍼 후면 층들로부터 기판 관통 비아들의 통합 Download PDFInfo
- Publication number
- KR101654794B1 KR101654794B1 KR1020157003194A KR20157003194A KR101654794B1 KR 101654794 B1 KR101654794 B1 KR 101654794B1 KR 1020157003194 A KR1020157003194 A KR 1020157003194A KR 20157003194 A KR20157003194 A KR 20157003194A KR 101654794 B1 KR101654794 B1 KR 101654794B1
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- substrate
- pad
- semiconductor device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05541—Structure
- H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes)
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes) consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201261669611P | 2012-07-09 | 2012-07-09 | |
| US61/669,611 | 2012-07-09 | ||
| US13/790,625 | 2013-03-08 | ||
| US13/790,625 US9219032B2 (en) | 2012-07-09 | 2013-03-08 | Integrating through substrate vias from wafer backside layers of integrated circuits |
| PCT/US2013/049686 WO2014011615A1 (en) | 2012-07-09 | 2013-07-09 | Integrating through substrate vias from wafer backside layers of integrated circuits |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20150028845A KR20150028845A (ko) | 2015-03-16 |
| KR101654794B1 true KR101654794B1 (ko) | 2016-09-06 |
Family
ID=49877888
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020157003194A Expired - Fee Related KR101654794B1 (ko) | 2012-07-09 | 2013-07-09 | 집적 회로들의 웨이퍼 후면 층들로부터 기판 관통 비아들의 통합 |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US9219032B2 (enExample) |
| EP (1) | EP2870628A1 (enExample) |
| JP (1) | JP6049877B2 (enExample) |
| KR (1) | KR101654794B1 (enExample) |
| CN (1) | CN104428887B (enExample) |
| TW (1) | TWI575652B (enExample) |
| WO (1) | WO2014011615A1 (enExample) |
Families Citing this family (49)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9245790B2 (en) * | 2013-01-23 | 2016-01-26 | GlobalFoundries, Inc. | Integrated circuits and methods of forming the same with multiple embedded interconnect connection to same through-semiconductor via |
| US9252080B1 (en) | 2014-10-15 | 2016-02-02 | Globalfoundries Inc. | Dielectric cover for a through silicon via |
| US9515017B2 (en) | 2014-12-18 | 2016-12-06 | Intel Corporation | Ground via clustering for crosstalk mitigation |
| CN104600027B (zh) * | 2015-01-30 | 2017-10-27 | 华进半导体封装先导技术研发中心有限公司 | 一种tsv通孔的制备工艺 |
| CN104600026A (zh) * | 2015-01-30 | 2015-05-06 | 华进半导体封装先导技术研发中心有限公司 | Cis产品tsv孔底部pad表面绝缘层的刻蚀方法 |
| CN106298627B (zh) * | 2015-05-20 | 2019-06-28 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件的制造方法和电子装置 |
| WO2017052558A1 (en) * | 2015-09-24 | 2017-03-30 | Intel Corporation | Techniques for revealing a backside of an integrated circuit device, and associated configurations |
| US9673275B2 (en) | 2015-10-22 | 2017-06-06 | Qualcomm Incorporated | Isolated complementary metal-oxide semiconductor (CMOS) devices for radio-frequency (RF) circuits |
| US9786592B2 (en) * | 2015-10-30 | 2017-10-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated circuit structure and method of forming the same |
| JP6568994B2 (ja) * | 2016-02-29 | 2019-08-28 | パナソニック・タワージャズセミコンダクター株式会社 | 半導体装置及びその製造方法 |
| KR102652854B1 (ko) * | 2016-08-17 | 2024-04-02 | 삼성전자주식회사 | 반도체 소자 및 그 제조 방법 |
| US10446546B2 (en) | 2016-11-17 | 2019-10-15 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor structures and methods of forming the same |
| EP3324436B1 (en) * | 2016-11-21 | 2020-08-05 | IMEC vzw | An integrated circuit chip with power delivery network on the backside of the chip |
| CN107644837B (zh) * | 2017-08-31 | 2019-01-01 | 长江存储科技有限责任公司 | 用于三维存储器的晶圆三维集成引线工艺及其结构 |
| US10607887B2 (en) | 2017-08-31 | 2020-03-31 | Yangtze Memory Technologies Co., Ltd. | Method for forming three-dimensional integrated wiring structure and semiconductor structure thereof |
| CN107644841B (zh) * | 2017-08-31 | 2019-01-01 | 长江存储科技有限责任公司 | 用于三维存储器的晶圆三维集成引线工艺及其结构 |
| CN107644840A (zh) * | 2017-08-31 | 2018-01-30 | 长江存储科技有限责任公司 | 用于三维存储器的晶圆三维集成引线工艺及其结构 |
| CN107644836A (zh) * | 2017-08-31 | 2018-01-30 | 长江存储科技有限责任公司 | 用于三维存储器的晶圆三维集成引线工艺及其结构 |
| CN107644838B (zh) * | 2017-08-31 | 2019-01-01 | 长江存储科技有限责任公司 | 用于三维存储器的晶圆三维集成引线工艺及其结构 |
| US10651087B2 (en) | 2017-08-31 | 2020-05-12 | Yangtze Memory Technologies Co., Ltd. | Method for forming three-dimensional integrated wiring structure and semiconductor structure thereof |
| US10559520B2 (en) * | 2017-09-29 | 2020-02-11 | Qualcomm Incorporated | Bulk layer transfer processing with backside silicidation |
| SG11202006672YA (en) | 2018-01-26 | 2020-08-28 | Agency Science Tech & Res | Electrical connection structure and method of forming the same |
| US12062700B2 (en) | 2018-04-04 | 2024-08-13 | Qorvo Us, Inc. | Gallium-nitride-based module with enhanced electrical performance and process for making the same |
| US12046505B2 (en) | 2018-04-20 | 2024-07-23 | Qorvo Us, Inc. | RF devices with enhanced performance and methods of forming the same utilizing localized SOI formation |
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| KR102521658B1 (ko) | 2018-09-03 | 2023-04-13 | 삼성전자주식회사 | 반도체 칩 및 이의 제조 방법 |
| KR102576062B1 (ko) | 2018-11-07 | 2023-09-07 | 삼성전자주식회사 | 관통 실리콘 비아를 포함하는 반도체 소자 및 그 제조 방법 |
| US11646242B2 (en) | 2018-11-29 | 2023-05-09 | Qorvo Us, Inc. | Thermally enhanced semiconductor package with at least one heat extractor and process for making the same |
| KR102771428B1 (ko) | 2019-01-23 | 2025-02-26 | 코르보 유에스, 인크. | Rf 반도체 디바이스 및 이를 형성하는 방법 |
| US12125825B2 (en) | 2019-01-23 | 2024-10-22 | Qorvo Us, Inc. | RF devices with enhanced performance and methods of forming the same |
| US12057374B2 (en) | 2019-01-23 | 2024-08-06 | Qorvo Us, Inc. | RF devices with enhanced performance and methods of forming the same |
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| US12129168B2 (en) | 2019-12-23 | 2024-10-29 | Qorvo Us, Inc. | Microelectronics package with vertically stacked MEMS device and controller device |
| CN111508929B (zh) * | 2020-04-17 | 2022-02-22 | 北京北方华创微电子装备有限公司 | 图形片及半导体中间产物 |
| KR102777683B1 (ko) | 2020-08-04 | 2025-03-10 | 에스케이하이닉스 주식회사 | 웨이퍼 대 웨이퍼 본딩 구조를 갖는 반도체 장치 및 그 제조방법 |
| US11862535B2 (en) | 2020-09-16 | 2024-01-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through-substrate-via with reentrant profile |
| EP4260369A2 (en) | 2020-12-11 | 2023-10-18 | Qorvo US, Inc. | Multi-level 3d stacked package and methods of forming the same |
| CN114975322A (zh) * | 2021-01-27 | 2022-08-30 | 英诺赛科(苏州)半导体有限公司 | 半导体器件结构 |
| WO2022186857A1 (en) | 2021-03-05 | 2022-09-09 | Qorvo Us, Inc. | Selective etching process for si-ge and doped epitaxial silicon |
| CN113394185A (zh) * | 2021-06-10 | 2021-09-14 | 武汉新芯集成电路制造有限公司 | 半导体器件及其制作方法、芯片 |
| US11810882B2 (en) | 2022-03-01 | 2023-11-07 | Micron Technology, Inc. | Solder based hybrid bonding for fine pitch and thin BLT interconnection |
| US20240038694A1 (en) * | 2022-07-26 | 2024-02-01 | Celestial Ai Inc. | Through-substrate via formed using a partial plug that stops before a substrate |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2009115449A1 (en) | 2008-03-19 | 2009-09-24 | Interuniversitair Microelektronica Centrum Vzw (Imec) | Method for fabricating through-substrate vias |
| US20090309232A1 (en) | 2008-04-30 | 2009-12-17 | Stmicroelectronics (Crolles 2) Sas | Method of making connections in a back-lit circuit |
| JP2011071239A (ja) | 2009-09-24 | 2011-04-07 | Toshiba Corp | 半導体装置の製造方法 |
| US20120007154A1 (en) | 2010-07-12 | 2012-01-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | TSV Formation Processes Using TSV-Last Approach |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6638844B1 (en) | 2002-07-29 | 2003-10-28 | Chartered Semiconductor Manufacturing Ltd. | Method of reducing substrate coupling/noise for radio frequency CMOS (RFCMOS) components in semiconductor technology by backside trench and fill |
| US7531407B2 (en) | 2006-07-18 | 2009-05-12 | International Business Machines Corporation | Semiconductor integrated circuit devices having high-Q wafer backside inductors and methods of fabricating same |
| US7741218B2 (en) | 2007-02-27 | 2010-06-22 | Freescale Semiconductor, Inc. | Conductive via formation utilizing electroplating |
| US7786584B2 (en) | 2007-11-26 | 2010-08-31 | Infineon Technologies Ag | Through substrate via semiconductor components |
| WO2009133196A1 (en) * | 2008-05-02 | 2009-11-05 | Interuniversity Micro-Electronics Centre (Imec) | Method for providing oxide layers |
| US7956442B2 (en) | 2008-10-09 | 2011-06-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Backside connection to TSVs having redistribution lines |
| JP2011003645A (ja) * | 2009-06-17 | 2011-01-06 | Sharp Corp | 半導体装置およびその製造方法 |
| JP5101575B2 (ja) * | 2009-07-28 | 2012-12-19 | 株式会社東芝 | 半導体装置およびその製造方法 |
| JP2011108690A (ja) * | 2009-11-12 | 2011-06-02 | Panasonic Corp | 半導体装置及びその製造方法 |
-
2013
- 2013-03-08 US US13/790,625 patent/US9219032B2/en active Active
- 2013-07-09 WO PCT/US2013/049686 patent/WO2014011615A1/en not_active Ceased
- 2013-07-09 KR KR1020157003194A patent/KR101654794B1/ko not_active Expired - Fee Related
- 2013-07-09 CN CN201380036280.5A patent/CN104428887B/zh active Active
- 2013-07-09 JP JP2015521717A patent/JP6049877B2/ja not_active Expired - Fee Related
- 2013-07-09 EP EP13739904.4A patent/EP2870628A1/en not_active Withdrawn
- 2013-07-09 TW TW102124641A patent/TWI575652B/zh active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2009115449A1 (en) | 2008-03-19 | 2009-09-24 | Interuniversitair Microelektronica Centrum Vzw (Imec) | Method for fabricating through-substrate vias |
| US20090309232A1 (en) | 2008-04-30 | 2009-12-17 | Stmicroelectronics (Crolles 2) Sas | Method of making connections in a back-lit circuit |
| JP2011071239A (ja) | 2009-09-24 | 2011-04-07 | Toshiba Corp | 半導体装置の製造方法 |
| US20120007154A1 (en) | 2010-07-12 | 2012-01-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | TSV Formation Processes Using TSV-Last Approach |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2015527733A (ja) | 2015-09-17 |
| EP2870628A1 (en) | 2015-05-13 |
| TW201409612A (zh) | 2014-03-01 |
| US20140008757A1 (en) | 2014-01-09 |
| CN104428887B (zh) | 2017-08-11 |
| US9219032B2 (en) | 2015-12-22 |
| KR20150028845A (ko) | 2015-03-16 |
| TWI575652B (zh) | 2017-03-21 |
| JP6049877B2 (ja) | 2016-12-21 |
| WO2014011615A1 (en) | 2014-01-16 |
| CN104428887A (zh) | 2015-03-18 |
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