TWI575652B - 自積體電路之晶圓背面層整合基板穿孔 - Google Patents
自積體電路之晶圓背面層整合基板穿孔 Download PDFInfo
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- TWI575652B TWI575652B TW102124641A TW102124641A TWI575652B TW I575652 B TWI575652 B TW I575652B TW 102124641 A TW102124641 A TW 102124641A TW 102124641 A TW102124641 A TW 102124641A TW I575652 B TWI575652 B TW I575652B
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- 239000000758 substrate Substances 0.000 title claims description 84
- 239000010410 layer Substances 0.000 claims description 298
- 238000000034 method Methods 0.000 claims description 90
- 239000004065 semiconductor Substances 0.000 claims description 73
- 238000002955 isolation Methods 0.000 claims description 57
- 238000005530 etching Methods 0.000 claims description 53
- 125000006850 spacer group Chemical group 0.000 claims description 46
- 239000000463 material Substances 0.000 claims description 42
- 239000000126 substance Substances 0.000 claims description 25
- 238000000151 deposition Methods 0.000 claims description 16
- 238000004519 manufacturing process Methods 0.000 claims description 11
- 238000004891 communication Methods 0.000 claims description 7
- 239000011229 interlayer Substances 0.000 claims description 7
- 239000000203 mixture Substances 0.000 claims description 7
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 7
- 229920000642 polymer Polymers 0.000 claims description 6
- 238000011049 filling Methods 0.000 claims description 5
- 229920002120 photoresistant polymer Polymers 0.000 claims description 4
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 3
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims description 2
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- 230000008569 process Effects 0.000 description 62
- 239000010408 film Substances 0.000 description 21
- 230000004888 barrier function Effects 0.000 description 16
- 230000015572 biosynthetic process Effects 0.000 description 12
- 230000008021 deposition Effects 0.000 description 9
- 238000004070 electrodeposition Methods 0.000 description 9
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- 238000005498 polishing Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 230000006870 function Effects 0.000 description 5
- 238000002161 passivation Methods 0.000 description 5
- 230000008901 benefit Effects 0.000 description 4
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- 229910044991 metal oxide Inorganic materials 0.000 description 4
- 150000004706 metal oxides Chemical class 0.000 description 4
- 238000001465 metallisation Methods 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- RUDFQVOCFDJEEF-UHFFFAOYSA-N yttrium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[Y+3].[Y+3] RUDFQVOCFDJEEF-UHFFFAOYSA-N 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- NFFIWVVINABMKP-UHFFFAOYSA-N methylidynetantalum Chemical compound [Ta]#C NFFIWVVINABMKP-UHFFFAOYSA-N 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 239000002243 precursor Substances 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
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- 230000007547 defect Effects 0.000 description 1
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- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
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- 230000010354 integration Effects 0.000 description 1
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- 230000007787 long-term memory Effects 0.000 description 1
- 230000006855 networking Effects 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 230000006403 short-term memory Effects 0.000 description 1
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- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05541—Structure
- H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes)
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes) consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201261669611P | 2012-07-09 | 2012-07-09 | |
| US13/790,625 US9219032B2 (en) | 2012-07-09 | 2013-03-08 | Integrating through substrate vias from wafer backside layers of integrated circuits |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201409612A TW201409612A (zh) | 2014-03-01 |
| TWI575652B true TWI575652B (zh) | 2017-03-21 |
Family
ID=49877888
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW102124641A TWI575652B (zh) | 2012-07-09 | 2013-07-09 | 自積體電路之晶圓背面層整合基板穿孔 |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US9219032B2 (enExample) |
| EP (1) | EP2870628A1 (enExample) |
| JP (1) | JP6049877B2 (enExample) |
| KR (1) | KR101654794B1 (enExample) |
| CN (1) | CN104428887B (enExample) |
| TW (1) | TWI575652B (enExample) |
| WO (1) | WO2014011615A1 (enExample) |
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| US9245790B2 (en) * | 2013-01-23 | 2016-01-26 | GlobalFoundries, Inc. | Integrated circuits and methods of forming the same with multiple embedded interconnect connection to same through-semiconductor via |
| US9252080B1 (en) | 2014-10-15 | 2016-02-02 | Globalfoundries Inc. | Dielectric cover for a through silicon via |
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| CN104600027B (zh) * | 2015-01-30 | 2017-10-27 | 华进半导体封装先导技术研发中心有限公司 | 一种tsv通孔的制备工艺 |
| CN104600026A (zh) * | 2015-01-30 | 2015-05-06 | 华进半导体封装先导技术研发中心有限公司 | Cis产品tsv孔底部pad表面绝缘层的刻蚀方法 |
| CN106298627B (zh) * | 2015-05-20 | 2019-06-28 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件的制造方法和电子装置 |
| WO2017052558A1 (en) * | 2015-09-24 | 2017-03-30 | Intel Corporation | Techniques for revealing a backside of an integrated circuit device, and associated configurations |
| US9673275B2 (en) | 2015-10-22 | 2017-06-06 | Qualcomm Incorporated | Isolated complementary metal-oxide semiconductor (CMOS) devices for radio-frequency (RF) circuits |
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| KR102652854B1 (ko) * | 2016-08-17 | 2024-04-02 | 삼성전자주식회사 | 반도체 소자 및 그 제조 방법 |
| US10446546B2 (en) * | 2016-11-17 | 2019-10-15 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor structures and methods of forming the same |
| EP3324436B1 (en) * | 2016-11-21 | 2020-08-05 | IMEC vzw | An integrated circuit chip with power delivery network on the backside of the chip |
| CN107644840A (zh) * | 2017-08-31 | 2018-01-30 | 长江存储科技有限责任公司 | 用于三维存储器的晶圆三维集成引线工艺及其结构 |
| US10607887B2 (en) * | 2017-08-31 | 2020-03-31 | Yangtze Memory Technologies Co., Ltd. | Method for forming three-dimensional integrated wiring structure and semiconductor structure thereof |
| CN107644841B (zh) * | 2017-08-31 | 2019-01-01 | 长江存储科技有限责任公司 | 用于三维存储器的晶圆三维集成引线工艺及其结构 |
| CN107644838B (zh) * | 2017-08-31 | 2019-01-01 | 长江存储科技有限责任公司 | 用于三维存储器的晶圆三维集成引线工艺及其结构 |
| CN107644837B (zh) * | 2017-08-31 | 2019-01-01 | 长江存储科技有限责任公司 | 用于三维存储器的晶圆三维集成引线工艺及其结构 |
| CN107644836A (zh) * | 2017-08-31 | 2018-01-30 | 长江存储科技有限责任公司 | 用于三维存储器的晶圆三维集成引线工艺及其结构 |
| US10651087B2 (en) | 2017-08-31 | 2020-05-12 | Yangtze Memory Technologies Co., Ltd. | Method for forming three-dimensional integrated wiring structure and semiconductor structure thereof |
| US10559520B2 (en) * | 2017-09-29 | 2020-02-11 | Qualcomm Incorporated | Bulk layer transfer processing with backside silicidation |
| US11508619B2 (en) | 2018-01-26 | 2022-11-22 | Agency For Science, Technology And Research | Electrical connection structure and method of forming the same |
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| US12046505B2 (en) | 2018-04-20 | 2024-07-23 | Qorvo Us, Inc. | RF devices with enhanced performance and methods of forming the same utilizing localized SOI formation |
| CN118213279A (zh) | 2018-07-02 | 2024-06-18 | Qorvo美国公司 | Rf半导体装置及其制造方法 |
| KR102521658B1 (ko) | 2018-09-03 | 2023-04-13 | 삼성전자주식회사 | 반도체 칩 및 이의 제조 방법 |
| KR102576062B1 (ko) | 2018-11-07 | 2023-09-07 | 삼성전자주식회사 | 관통 실리콘 비아를 포함하는 반도체 소자 및 그 제조 방법 |
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| US11387157B2 (en) * | 2019-01-23 | 2022-07-12 | Qorvo Us, Inc. | RF devices with enhanced performance and methods of forming the same |
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-
2013
- 2013-03-08 US US13/790,625 patent/US9219032B2/en active Active
- 2013-07-09 WO PCT/US2013/049686 patent/WO2014011615A1/en not_active Ceased
- 2013-07-09 EP EP13739904.4A patent/EP2870628A1/en not_active Withdrawn
- 2013-07-09 JP JP2015521717A patent/JP6049877B2/ja not_active Expired - Fee Related
- 2013-07-09 TW TW102124641A patent/TWI575652B/zh active
- 2013-07-09 CN CN201380036280.5A patent/CN104428887B/zh active Active
- 2013-07-09 KR KR1020157003194A patent/KR101654794B1/ko not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110089572A1 (en) * | 2008-03-19 | 2011-04-21 | Imec | Method for fabricating through substrate vias |
| US20090309232A1 (en) * | 2008-04-30 | 2009-12-17 | Stmicroelectronics (Crolles 2) Sas | Method of making connections in a back-lit circuit |
| US20100090318A1 (en) * | 2008-10-09 | 2010-04-15 | Kuo-Ching Hsu | Backside Connection to TSVs Having Redistribution Lines |
Also Published As
| Publication number | Publication date |
|---|---|
| KR101654794B1 (ko) | 2016-09-06 |
| US20140008757A1 (en) | 2014-01-09 |
| JP6049877B2 (ja) | 2016-12-21 |
| JP2015527733A (ja) | 2015-09-17 |
| KR20150028845A (ko) | 2015-03-16 |
| TW201409612A (zh) | 2014-03-01 |
| WO2014011615A1 (en) | 2014-01-16 |
| EP2870628A1 (en) | 2015-05-13 |
| CN104428887B (zh) | 2017-08-11 |
| CN104428887A (zh) | 2015-03-18 |
| US9219032B2 (en) | 2015-12-22 |
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