JP6032070B2 - 半導体装置、半導体装置の製造方法 - Google Patents
半導体装置、半導体装置の製造方法 Download PDFInfo
- Publication number
- JP6032070B2 JP6032070B2 JP2013050141A JP2013050141A JP6032070B2 JP 6032070 B2 JP6032070 B2 JP 6032070B2 JP 2013050141 A JP2013050141 A JP 2013050141A JP 2013050141 A JP2013050141 A JP 2013050141A JP 6032070 B2 JP6032070 B2 JP 6032070B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- semiconductor device
- wiring board
- holding body
- insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/01—Manufacture or treatment
- H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/01—Manufacture or treatment
- H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
- H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
- H10W70/65—Shapes or dispositions of interconnections
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/68—Shapes or dispositions thereof
- H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W44/00—Electrical arrangements for controlling or matching impedance
- H10W44/20—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W44/00—Electrical arrangements for controlling or matching impedance
- H10W44/20—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF]
- H10W44/203—Electrical connections
- H10W44/209—Vertical interconnections, e.g. vias
- H10W44/212—Coaxial feed-throughs in substrates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
- H10W70/63—Vias, e.g. via plugs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Combinations Of Printed Boards (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
- Physics & Mathematics (AREA)
- Geometry (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2013050141A JP6032070B2 (ja) | 2013-03-13 | 2013-03-13 | 半導体装置、半導体装置の製造方法 |
| TW103105153A TWI615933B (zh) | 2013-03-13 | 2014-02-17 | 半導體裝置及其製造方法 |
| CN201480009974.4A CN105009279B (zh) | 2013-03-13 | 2014-02-27 | 半导体器件及制造半导体器件的方法 |
| US14/765,929 US10332826B2 (en) | 2013-03-13 | 2014-02-27 | Semiconductor device and method of manufacturing semiconductor device |
| PCT/JP2014/001046 WO2014141607A1 (en) | 2013-03-13 | 2014-02-27 | Semiconductor device and method of manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2013050141A JP6032070B2 (ja) | 2013-03-13 | 2013-03-13 | 半導体装置、半導体装置の製造方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2014175642A JP2014175642A (ja) | 2014-09-22 |
| JP2014175642A5 JP2014175642A5 (https=) | 2015-03-05 |
| JP6032070B2 true JP6032070B2 (ja) | 2016-11-24 |
Family
ID=50349816
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2013050141A Expired - Fee Related JP6032070B2 (ja) | 2013-03-13 | 2013-03-13 | 半導体装置、半導体装置の製造方法 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US10332826B2 (https=) |
| JP (1) | JP6032070B2 (https=) |
| CN (1) | CN105009279B (https=) |
| TW (1) | TWI615933B (https=) |
| WO (1) | WO2014141607A1 (https=) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN207134353U (zh) * | 2017-08-31 | 2018-03-23 | 深圳市江波龙电子有限公司 | 移动终端及其芯片封装结构 |
| CN108987425B (zh) * | 2018-07-19 | 2020-09-18 | 豪威半导体(上海)有限责任公司 | 微led显示器及其制造方法 |
Family Cites Families (27)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0645401A (ja) * | 1992-07-23 | 1994-02-18 | Nec Corp | 半導体装置用パッケージ |
| JP2541102B2 (ja) * | 1993-06-23 | 1996-10-09 | 日本電気株式会社 | 同軸フリップチップ接続構造の形成方法 |
| JPH0878572A (ja) * | 1994-08-31 | 1996-03-22 | Hitachi Ltd | 半導体パッケージおよび、それの製造方法および、それを実装した回路ボードと電子機器 |
| JP2751913B2 (ja) * | 1996-03-28 | 1998-05-18 | 日本電気株式会社 | 半導体装置用パッケージ |
| JPH10335547A (ja) | 1997-05-29 | 1998-12-18 | Canon Inc | 電子回路装置及びその製造方法 |
| US5851337A (en) * | 1997-06-30 | 1998-12-22 | Caesar Technology Inc. | Method of connecting TEHS on PBGA and modified connecting structure |
| JP3629178B2 (ja) * | 2000-02-21 | 2005-03-16 | Necエレクトロニクス株式会社 | フリップチップ型半導体装置及びその製造方法 |
| US7120607B2 (en) * | 2000-06-16 | 2006-10-10 | Lenovo (Singapore) Pte. Ltd. | Business system and method using a distorted biometrics |
| JP4427874B2 (ja) | 2000-07-06 | 2010-03-10 | 住友ベークライト株式会社 | 多層配線板の製造方法および多層配線板 |
| US7059009B2 (en) * | 2002-07-19 | 2006-06-13 | Valeo Electrical Systems, Inc. | Windshield wiper drive linkage arm with grooves |
| US6650016B1 (en) * | 2002-10-01 | 2003-11-18 | International Business Machines Corporation | Selective C4 connection in IC packaging |
| US7105931B2 (en) * | 2003-01-07 | 2006-09-12 | Abbas Ismail Attarwala | Electronic package and method |
| US7394663B2 (en) * | 2003-02-18 | 2008-07-01 | Matsushita Electric Industrial Co., Ltd. | Electronic component built-in module and method of manufacturing the same |
| US7331500B2 (en) * | 2004-06-25 | 2008-02-19 | Intel Corporation | Solder bumps formation using solder paste with shape retaining attribute |
| US7045893B1 (en) | 2004-07-15 | 2006-05-16 | Amkor Technology, Inc. | Semiconductor package and method for manufacturing the same |
| JP2006295019A (ja) * | 2005-04-14 | 2006-10-26 | Fujitsu Ltd | 電子部品を基板に取り付け及び取り外す加熱装置 |
| KR20090012933A (ko) * | 2007-07-31 | 2009-02-04 | 삼성전자주식회사 | 반도체 패키지, 스택 모듈, 카드, 시스템 및 반도체패키지의 제조 방법 |
| US20100327452A1 (en) * | 2008-03-05 | 2010-12-30 | Hirotsugu Kobayashi | Mounting structure and method of manufacturing the same |
| US7516879B1 (en) * | 2008-07-02 | 2009-04-14 | International Business Machines Corporation | Method of producing coaxial solder bump connections using injection molding of solder |
| JP5228843B2 (ja) * | 2008-11-28 | 2013-07-03 | 富士通株式会社 | 半導体素子搭載用基板及び半導体装置 |
| JP5404513B2 (ja) | 2010-04-19 | 2014-02-05 | ソニー株式会社 | 半導体装置の製造方法 |
| JPWO2012029526A1 (ja) * | 2010-08-30 | 2013-10-28 | 住友ベークライト株式会社 | 半導体パッケージおよび半導体装置 |
| KR101677739B1 (ko) * | 2010-09-29 | 2016-11-21 | 삼성전자주식회사 | 반도체 패키지 및 그의 제조방법 |
| US8531021B2 (en) * | 2011-01-27 | 2013-09-10 | Unimicron Technology Corporation | Package stack device and fabrication method thereof |
| TWI433278B (zh) * | 2011-03-10 | 2014-04-01 | 矽品精密工業股份有限公司 | 無承載板之封裝件及其製法 |
| CN103975427B (zh) * | 2011-10-07 | 2017-03-01 | 沃尔泰拉半导体公司 | 互连衬底的功率管理应用 |
| WO2013054504A1 (ja) * | 2011-10-13 | 2013-04-18 | 住友ベークライト株式会社 | 半導体パッケージおよび半導体装置 |
-
2013
- 2013-03-13 JP JP2013050141A patent/JP6032070B2/ja not_active Expired - Fee Related
-
2014
- 2014-02-17 TW TW103105153A patent/TWI615933B/zh not_active IP Right Cessation
- 2014-02-27 US US14/765,929 patent/US10332826B2/en active Active
- 2014-02-27 WO PCT/JP2014/001046 patent/WO2014141607A1/en not_active Ceased
- 2014-02-27 CN CN201480009974.4A patent/CN105009279B/zh not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| WO2014141607A1 (en) | 2014-09-18 |
| US10332826B2 (en) | 2019-06-25 |
| CN105009279A (zh) | 2015-10-28 |
| TWI615933B (zh) | 2018-02-21 |
| JP2014175642A (ja) | 2014-09-22 |
| CN105009279B (zh) | 2018-04-17 |
| US20150380347A1 (en) | 2015-12-31 |
| TW201438172A (zh) | 2014-10-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111316434B (zh) | 具有差分同轴通孔的电子衬底 | |
| JP5715009B2 (ja) | 部品内蔵配線基板及びその製造方法 | |
| EP4220709B1 (en) | Ground via clustering for crosstalk mitigation | |
| CN102165584B (zh) | 用于已安装处理器的输入/输出架构及使用其的方法 | |
| US10187971B2 (en) | Wiring board and method of manufacturing wiring board | |
| CN105789847A (zh) | 天线整合式封装结构及其制造方法 | |
| US12309943B2 (en) | Circuit carrier and manufacturing method thereof and package structure | |
| CN104396008B (zh) | 半导体封装衬底、使用半导体封装衬底的封装系统及用于制造封装系统的方法 | |
| CN102638931A (zh) | 电子组件、使寄生电容最小的方法及制造电路板结构的方法 | |
| US9793241B2 (en) | Printed wiring board | |
| CN106068060A (zh) | 具有支撑图案的印刷电路板及其制造方法 | |
| CN104080280B (zh) | 一种封装基板单元及其制作方法和基板组件 | |
| CN103227164A (zh) | 半导体封装构造及其制造方法 | |
| JP6032070B2 (ja) | 半導体装置、半導体装置の製造方法 | |
| CN103716992A (zh) | 具有内嵌元件、内建定位件、及电磁屏障的线路板 | |
| EP2849226B1 (en) | Semiconductor package | |
| CN103681586A (zh) | 无核心封装基板及其制法 | |
| US10134693B2 (en) | Printed wiring board | |
| WO2013153717A1 (ja) | 電子機器及びその製造方法 | |
| US20250081348A1 (en) | Bridge printed circuit board embedded within another printed circuit board | |
| TWI517312B (zh) | 具有屏蔽蓋及屏蔽狹槽作爲內嵌元件之電磁屏障之線路板 | |
| JP2010519769A (ja) | 高速メモリパッケージ | |
| US20090001547A1 (en) | High-Density Fine Line Structure And Method Of Manufacturing The Same | |
| CN103779333B (zh) | 具有内嵌元件及电磁屏障的线路板 | |
| JP2017022151A (ja) | 多層配線基板及びその製造方法 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20150120 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20150120 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20160315 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20160509 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20160927 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20161010 |
|
| R151 | Written notification of patent or utility model registration |
Ref document number: 6032070 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R151 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| LAPS | Cancellation because of no payment of annual fees |