JP6029958B2 - 配線基板の製造方法 - Google Patents

配線基板の製造方法 Download PDF

Info

Publication number
JP6029958B2
JP6029958B2 JP2012265471A JP2012265471A JP6029958B2 JP 6029958 B2 JP6029958 B2 JP 6029958B2 JP 2012265471 A JP2012265471 A JP 2012265471A JP 2012265471 A JP2012265471 A JP 2012265471A JP 6029958 B2 JP6029958 B2 JP 6029958B2
Authority
JP
Japan
Prior art keywords
layer
wiring
support
substrate
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2012265471A
Other languages
English (en)
Japanese (ja)
Other versions
JP2014110390A (ja
JP2014110390A5 (enExample
Inventor
清水　規良
規良 清水
六川　昭雄
昭雄 六川
小山　利徳
利徳 小山
渉 金田
渉 金田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2012265471A priority Critical patent/JP6029958B2/ja
Priority to US14/090,076 priority patent/US9380707B2/en
Publication of JP2014110390A publication Critical patent/JP2014110390A/ja
Publication of JP2014110390A5 publication Critical patent/JP2014110390A5/ja
Application granted granted Critical
Publication of JP6029958B2 publication Critical patent/JP6029958B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/007—Manufacture or processing of a substrate for a printed circuit board supported by a temporary or sacrificial carrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12044—OLED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09509—Blind vias, i.e. vias having one side closed
    • H05K2201/09527—Inverse blind vias, i.e. bottoms outwards in multilayer PCB; Blind vias in centre of PCB having opposed bottoms
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • H05K3/205—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126—Assembling bases
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49128—Assembling formed circuit to base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
JP2012265471A 2012-12-04 2012-12-04 配線基板の製造方法 Active JP6029958B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2012265471A JP6029958B2 (ja) 2012-12-04 2012-12-04 配線基板の製造方法
US14/090,076 US9380707B2 (en) 2012-12-04 2013-11-26 Method of manufacturing wiring substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2012265471A JP6029958B2 (ja) 2012-12-04 2012-12-04 配線基板の製造方法

Publications (3)

Publication Number Publication Date
JP2014110390A JP2014110390A (ja) 2014-06-12
JP2014110390A5 JP2014110390A5 (enExample) 2015-12-24
JP6029958B2 true JP6029958B2 (ja) 2016-11-24

Family

ID=50824001

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2012265471A Active JP6029958B2 (ja) 2012-12-04 2012-12-04 配線基板の製造方法

Country Status (2)

Country Link
US (1) US9380707B2 (enExample)
JP (1) JP6029958B2 (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI566305B (zh) * 2014-10-29 2017-01-11 巨擘科技股份有限公司 製造三維積體電路的方法
TWI613781B (zh) * 2015-12-11 2018-02-01 I-Shou University 中介層結構及其製造方法
JP2017228647A (ja) * 2016-06-22 2017-12-28 富士通株式会社 樹脂インターポーザ及びそれを用いた半導体装置及び樹脂インターポーザの製造方法
US10840180B2 (en) 2016-10-06 2020-11-17 Mitsui Mining & Smelting Co., Ltd. Production method for multilayer wiring board
CN107611042B (zh) * 2017-08-24 2021-09-21 通富微电子股份有限公司 一种扇出型封装方法
CN107564880A (zh) * 2017-08-24 2018-01-09 通富微电子股份有限公司 一种扇出型封装器件
JP7052464B2 (ja) * 2018-03-22 2022-04-12 凸版印刷株式会社 微細配線層付きコアレス基板の製造方法、および半導体パッケージの製造方法
JP7202785B2 (ja) 2018-04-27 2023-01-12 新光電気工業株式会社 配線基板及び配線基板の製造方法
JP7321009B2 (ja) 2019-07-01 2023-08-04 新光電気工業株式会社 配線基板、接合型配線基板及び配線基板の製造方法
JP7398561B2 (ja) * 2019-11-18 2023-12-14 新光維医療科技（蘇州）股▲フン▼有限公司 一体化された小型溶接板構造およびその製造方法
JP7661664B2 (ja) * 2021-08-20 2025-04-15 新光電気工業株式会社 配線基板及びその製造方法
WO2025187310A1 (ja) * 2024-03-05 2025-09-12 株式会社ジャパンディスプレイ インターポーザの製造方法およびインターポーザ

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0716094B2 (ja) * 1986-03-31 1995-02-22 日立化成工業株式会社 配線板の製造法
US6565954B2 (en) * 1998-05-14 2003-05-20 Matsushita Electric Industrial Co., Ltd. Circuit board and method of manufacturing the same
JP2002190543A (ja) 2000-12-20 2002-07-05 Shinko Electric Ind Co Ltd 配線基板及びその製造方法
TWI312166B (en) 2001-09-28 2009-07-11 Toppan Printing Co Ltd Multi-layer circuit board, integrated circuit package, and manufacturing method for multi-layer circuit board
JP2004342988A (ja) 2003-05-19 2004-12-02 Shinko Electric Ind Co Ltd 半導体パッケージの製造方法、及び半導体装置の製造方法
JP2007036095A (ja) * 2005-07-29 2007-02-08 Toppan Printing Co Ltd 受動素子内蔵配線回路基板及びその製造方法
TWI295550B (en) * 2005-12-20 2008-04-01 Phoenix Prec Technology Corp Structure of circuit board and method for fabricating the same
KR100776248B1 (ko) * 2006-11-21 2007-11-16 삼성전기주식회사 인쇄회로기판 제조방법
KR100951449B1 (ko) * 2008-01-03 2010-04-07 삼성전기주식회사 인쇄회로기판 및 그 제조방법
KR101089986B1 (ko) * 2009-12-24 2011-12-05 삼성전기주식회사 캐리어기판, 그의 제조방법, 이를 이용한 인쇄회로기판 및 그의 제조방법

Also Published As

Publication number Publication date
JP2014110390A (ja) 2014-06-12
US9380707B2 (en) 2016-06-28
US20140150258A1 (en) 2014-06-05

Similar Documents

Publication Publication Date Title
JP6029958B2 (ja) 配線基板の製造方法
JP4072176B2 (ja) 多層配線基板の製造方法
JP5703010B2 (ja) 半導体パッケージ及びその製造方法
JP4055717B2 (ja) 半導体装置およびその製造方法
JP3945483B2 (ja) 半導体装置の製造方法
JP5864180B2 (ja) 半導体パッケージ及びその製造方法
US8209856B2 (en) Printed wiring board and method for manufacturing the same
US9136220B2 (en) Semiconductor package and method for manufacturing the semiconductor package
JP5367523B2 (ja) 配線基板及び配線基板の製造方法
JP7202785B2 (ja) 配線基板及び配線基板の製造方法
KR20160024802A (ko) 전자 부품 장치 및 그 제조 방법
US9374889B2 (en) Interposer and electronic component package
JP5406572B2 (ja) 電子部品内蔵配線基板及びその製造方法
US8766101B2 (en) Wiring substrate, method for manufacturing wiring substrate, and semiconductor package including wiring substrate
JP2011100793A (ja) 半導体パッケージの製造方法
JP5436837B2 (ja) 半導体装置内蔵基板の製造方法
JP2018006466A (ja) 配線基板、半導体装置、配線基板の製造方法
JP5355363B2 (ja) 半導体装置内蔵基板及びその製造方法
JP2008078683A (ja) 多層配線基板
JP2017201674A (ja) プリント配線板およびその製造方法
JP4209341B2 (ja) 半導体装置およびその製造方法
JP5511922B2 (ja) 配線基板とその製造方法
JP2005191157A (ja) 半導体装置およびその製造方法
JP2016225398A (ja) 半導体装置
JP2009064879A (ja) 半導体装置およびその製造方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20151104

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20151104

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20160915

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20161004

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20161019

R150 Certificate of patent or registration of utility model

Ref document number: 6029958

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150