JP6003449B2 - 半導体装置及びメモリの制御方法 - Google Patents

半導体装置及びメモリの制御方法 Download PDF

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Publication number
JP6003449B2
JP6003449B2 JP2012207076A JP2012207076A JP6003449B2 JP 6003449 B2 JP6003449 B2 JP 6003449B2 JP 2012207076 A JP2012207076 A JP 2012207076A JP 2012207076 A JP2012207076 A JP 2012207076A JP 6003449 B2 JP6003449 B2 JP 6003449B2
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Japan
Prior art keywords
signal
access
operation state
control unit
memory
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JP2012207076A
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English (en)
Japanese (ja)
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JP2014063279A5 (https=
JP2014063279A (ja
Inventor
康之 江口
康之 江口
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Socionext Inc
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Socionext Inc
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Priority to JP2012207076A priority Critical patent/JP6003449B2/ja
Priority to US14/028,249 priority patent/US9218855B2/en
Publication of JP2014063279A publication Critical patent/JP2014063279A/ja
Publication of JP2014063279A5 publication Critical patent/JP2014063279A5/ja
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/148—Details of power up or power down circuits, standby circuits or recovery circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Sources (AREA)
  • Memory System (AREA)
  • Dram (AREA)
JP2012207076A 2012-09-20 2012-09-20 半導体装置及びメモリの制御方法 Active JP6003449B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2012207076A JP6003449B2 (ja) 2012-09-20 2012-09-20 半導体装置及びメモリの制御方法
US14/028,249 US9218855B2 (en) 2012-09-20 2013-09-16 Semiconductor device and memory control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2012207076A JP6003449B2 (ja) 2012-09-20 2012-09-20 半導体装置及びメモリの制御方法

Publications (3)

Publication Number Publication Date
JP2014063279A JP2014063279A (ja) 2014-04-10
JP2014063279A5 JP2014063279A5 (https=) 2015-07-16
JP6003449B2 true JP6003449B2 (ja) 2016-10-05

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ID=50274336

Family Applications (1)

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JP2012207076A Active JP6003449B2 (ja) 2012-09-20 2012-09-20 半導体装置及びメモリの制御方法

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US (1) US9218855B2 (https=)
JP (1) JP6003449B2 (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6341795B2 (ja) * 2014-08-05 2018-06-13 ルネサスエレクトロニクス株式会社 マイクロコンピュータ及びマイクロコンピュータシステム
JP2016036944A (ja) * 2014-08-06 2016-03-22 シャープ株式会社 画像形成装置
KR102319392B1 (ko) * 2015-06-09 2021-11-01 에스케이하이닉스 주식회사 메모리 시스템 및 이의 동작 방법
US11200001B2 (en) * 2020-05-15 2021-12-14 Micron Technology, Inc. Management of power during memory device reset and initialization

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01260690A (ja) * 1988-04-08 1989-10-17 Fujitsu Ltd メモリアクセス制御方式
US5430881A (en) * 1990-12-28 1995-07-04 Dia Semicon Systems Incorporated Supervisory control method and power saving control unit for computer system
JP2868650B2 (ja) * 1991-07-24 1999-03-10 キヤノン株式会社 表示装置
US5835435A (en) * 1997-12-02 1998-11-10 Intel Corporation Method and apparatus for dynamically placing portions of a memory in a reduced power consumtion state
JPH11184554A (ja) * 1997-12-24 1999-07-09 Mitsubishi Electric Corp クロック制御タイプ情報処理装置
JP2002082829A (ja) * 2000-09-06 2002-03-22 Nec Kofu Ltd 消費電力制御装置及び消費電力制御方法
JP2002244917A (ja) * 2001-02-15 2002-08-30 Matsushita Electric Ind Co Ltd アクセス管理装置、およびプログラム
JP4458699B2 (ja) * 2001-03-06 2010-04-28 株式会社東芝 半導体集積回路
JP4765222B2 (ja) * 2001-08-09 2011-09-07 日本電気株式会社 Ｄｒａｍ装置
JP4104886B2 (ja) 2002-03-20 2008-06-18 株式会社ルネサステクノロジ 半導体装置
JP2004103153A (ja) * 2002-09-11 2004-04-02 Seiko Epson Corp 不揮発性半導体記憶装置の電圧発生回路
JP2005115906A (ja) * 2003-09-19 2005-04-28 Ricoh Co Ltd メモリ駆動システム
JP2005340879A (ja) * 2004-05-24 2005-12-08 Ricoh Co Ltd 画像形成装置
JP2005339310A (ja) 2004-05-28 2005-12-08 Renesas Technology Corp 半導体装置
JP2006099569A (ja) * 2004-09-30 2006-04-13 Kyocera Mita Corp メモリインタフェース回路及びクロック制御方法
JP2006171952A (ja) * 2004-12-14 2006-06-29 Renesas Technology Corp 半導体集積回路装置
JP4834434B2 (ja) * 2006-03-17 2011-12-14 富士通株式会社 記憶装置の電源制御方法
JP4851962B2 (ja) 2007-02-28 2012-01-11 株式会社東芝 メモリシステム
JP5228468B2 (ja) * 2007-12-17 2013-07-03 富士通セミコンダクター株式会社 システム装置およびシステム装置の動作方法
US9032235B2 (en) * 2012-07-31 2015-05-12 Kabushiki Kaisha Toshiba Semiconductor storage device and method for controlling the semiconductor storage device

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Publication number Publication date
US9218855B2 (en) 2015-12-22
JP2014063279A (ja) 2014-04-10
US20140078850A1 (en) 2014-03-20

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