JP5983236B2 - 半導体記憶装置 - Google Patents
半導体記憶装置 Download PDFInfo
- Publication number
- JP5983236B2 JP5983236B2 JP2012210399A JP2012210399A JP5983236B2 JP 5983236 B2 JP5983236 B2 JP 5983236B2 JP 2012210399 A JP2012210399 A JP 2012210399A JP 2012210399 A JP2012210399 A JP 2012210399A JP 5983236 B2 JP5983236 B2 JP 5983236B2
- Authority
- JP
- Japan
- Prior art keywords
- memory
- voltage
- signal
- line
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
- G06F3/064—Management of blocks
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/24—Bit-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
- G11C16/3427—Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Human Computer Interaction (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Read Only Memory (AREA)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2012210399A JP5983236B2 (ja) | 2012-09-25 | 2012-09-25 | 半導体記憶装置 |
| US14/031,911 US9417818B2 (en) | 2012-09-25 | 2013-09-19 | Semiconductor memory for capacitively biasing multiple source lines |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2012210399A JP5983236B2 (ja) | 2012-09-25 | 2012-09-25 | 半導体記憶装置 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2014067461A JP2014067461A (ja) | 2014-04-17 |
| JP2014067461A5 JP2014067461A5 (enExample) | 2015-07-16 |
| JP5983236B2 true JP5983236B2 (ja) | 2016-08-31 |
Family
ID=50340073
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2012210399A Active JP5983236B2 (ja) | 2012-09-25 | 2012-09-25 | 半導体記憶装置 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US9417818B2 (enExample) |
| JP (1) | JP5983236B2 (enExample) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6102146B2 (ja) * | 2012-09-25 | 2017-03-29 | 株式会社ソシオネクスト | 半導体記憶装置 |
| US9997253B1 (en) * | 2016-12-08 | 2018-06-12 | Cypress Semiconductor Corporation | Non-volatile memory array with memory gate line and source line scrambling |
| US10062440B1 (en) | 2017-06-20 | 2018-08-28 | Winbond Electronics Corp. | Non-volatile semiconductor memory device and reading method thereof |
| CN112614533B (zh) * | 2021-01-06 | 2021-11-02 | 长江存储科技有限责任公司 | 用于半导体器件的编程方法及半导体器件 |
Family Cites Families (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5687345A (en) | 1992-03-17 | 1997-11-11 | Hitachi, Ltd. | Microcomputer having CPU and built-in flash memory that is rewritable under control of the CPU analyzing a command supplied from an external device |
| JP3534781B2 (ja) | 1992-03-19 | 2004-06-07 | 株式会社ルネサステクノロジ | マイクロコンピュータ、及びフラッシュメモリ |
| JPH06314495A (ja) | 1993-04-28 | 1994-11-08 | Hitachi Ltd | 半導体記憶装置 |
| US5657268A (en) * | 1995-11-20 | 1997-08-12 | Texas Instruments Incorporated | Array-source line, bitline and wordline sequence in flash operations |
| US6300183B1 (en) * | 1999-03-19 | 2001-10-09 | Microchip Technology Incorporated | Independently programmable memory segments within a PMOS electrically erasable programmable read only memory array achieved by N-well separation and method therefor |
| JP2001291392A (ja) | 2000-04-10 | 2001-10-19 | Matsushita Electric Ind Co Ltd | 不揮発性半導体記憶装置 |
| JP2003123493A (ja) | 2001-10-12 | 2003-04-25 | Fujitsu Ltd | ソース電位を制御してプログラム動作を最適化した不揮発性メモリ |
| JP4240925B2 (ja) | 2002-07-03 | 2009-03-18 | パナソニック株式会社 | 半導体記憶装置及びその書き込み方法 |
| JP3962769B2 (ja) * | 2004-11-01 | 2007-08-22 | 株式会社Genusion | 不揮発性半導体記憶装置およびその書込方法 |
| JP4764142B2 (ja) * | 2005-11-11 | 2011-08-31 | 株式会社東芝 | 半導体記憶装置 |
| JP5059437B2 (ja) | 2007-02-06 | 2012-10-24 | 株式会社Genusion | 不揮発性半導体記憶装置 |
| US7894263B2 (en) * | 2007-09-28 | 2011-02-22 | Sandisk Corporation | High voltage generation and control in source-side injection programming of non-volatile memory |
| JP5483826B2 (ja) * | 2008-03-04 | 2014-05-07 | 株式会社Genusion | 不揮発性半導体記憶装置及びその書き込み方法 |
| JP5174493B2 (ja) | 2008-03-06 | 2013-04-03 | 株式会社日立製作所 | 半導体集積回路装置及びアイ開口マージン評価方法 |
| KR101644979B1 (ko) * | 2010-02-01 | 2016-08-03 | 삼성전자주식회사 | 불휘발성 메모리 장치 및 그것의 읽기 방법 |
| JP2013004123A (ja) * | 2011-06-14 | 2013-01-07 | Toshiba Corp | 不揮発性半導体記憶装置 |
| JP6102146B2 (ja) * | 2012-09-25 | 2017-03-29 | 株式会社ソシオネクスト | 半導体記憶装置 |
-
2012
- 2012-09-25 JP JP2012210399A patent/JP5983236B2/ja active Active
-
2013
- 2013-09-19 US US14/031,911 patent/US9417818B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| US9417818B2 (en) | 2016-08-16 |
| JP2014067461A (ja) | 2014-04-17 |
| US20140089570A1 (en) | 2014-03-27 |
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